[coreboot] New patch to review for coreboot: 4e5d8a6 Rename mainboard.c to ramstage.c
Christian Gmeiner (christian.gmeiner@gmail.com)
gerrit at coreboot.org
Tue Aug 7 09:51:42 CEST 2012
Christian Gmeiner (christian.gmeiner at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1416
-gerrit
commit 4e5d8a6b7aaa848109b58c4f706f663a65d63c9d
Author: Christian Gmeiner <christian.gmeiner at gmail.com>
Date: Tue Aug 7 09:48:29 2012 +0200
Rename mainboard.c to ramstage.c
This patch does more or less a simple rename of files to
make it more clear at which stage in the boot process mainboard.c
gets used.
Change-Id: If8af03b3558357c2fbb377268f9d798d03bd5cd1
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/arch/x86/include/arch/coreboot_tables.h | 2 +-
src/cpu/amd/sc520/raminit.c | 2 +-
src/mainboard/a-trend/atc-6220/mainboard.c | 25 -
src/mainboard/a-trend/atc-6220/ramstage.c | 25 +
src/mainboard/a-trend/atc-6240/mainboard.c | 25 -
src/mainboard/a-trend/atc-6240/ramstage.c | 25 +
src/mainboard/aaeon/pfm-540i_revb/mainboard.c | 37 -
src/mainboard/aaeon/pfm-540i_revb/ramstage.c | 37 +
src/mainboard/abit/be6-ii_v2_0/mainboard.c | 25 -
src/mainboard/abit/be6-ii_v2_0/ramstage.c | 25 +
src/mainboard/advansus/a785e-i/mainboard.c | 93 --
src/mainboard/advansus/a785e-i/ramstage.c | 93 ++
src/mainboard/advantech/pcm-5820/mainboard.c | 25 -
src/mainboard/advantech/pcm-5820/ramstage.c | 25 +
src/mainboard/amd/bimini_fam10/mainboard.c | 144 ----
src/mainboard/amd/bimini_fam10/ramstage.c | 144 ++++
src/mainboard/amd/db800/mainboard.c | 37 -
src/mainboard/amd/db800/ramstage.c | 37 +
src/mainboard/amd/dbm690t/mainboard.c | 201 -----
src/mainboard/amd/dbm690t/ramstage.c | 201 +++++
src/mainboard/amd/dinar/mainboard.c | 84 --
src/mainboard/amd/dinar/ramstage.c | 84 ++
src/mainboard/amd/inagua/mainboard.c | 92 --
src/mainboard/amd/inagua/ramstage.c | 92 ++
src/mainboard/amd/mahogany/mainboard.c | 117 ---
src/mainboard/amd/mahogany/ramstage.c | 117 +++
src/mainboard/amd/mahogany_fam10/mainboard.c | 118 ---
src/mainboard/amd/mahogany_fam10/ramstage.c | 118 +++
src/mainboard/amd/norwich/mainboard.c | 37 -
src/mainboard/amd/norwich/ramstage.c | 37 +
src/mainboard/amd/parmer/mainboard.c | 57 --
src/mainboard/amd/parmer/ramstage.c | 57 ++
src/mainboard/amd/persimmon/mainboard.c | 77 --
src/mainboard/amd/persimmon/ramstage.c | 77 ++
src/mainboard/amd/pistachio/mainboard.c | 270 ------
src/mainboard/amd/pistachio/ramstage.c | 270 ++++++
src/mainboard/amd/rumba/mainboard.c | 39 -
src/mainboard/amd/rumba/ramstage.c | 39 +
src/mainboard/amd/serengeti_cheetah/mainboard.c | 6 -
src/mainboard/amd/serengeti_cheetah/ramstage.c | 6 +
.../amd/serengeti_cheetah_fam10/mainboard.c | 29 -
.../amd/serengeti_cheetah_fam10/ramstage.c | 29 +
src/mainboard/amd/south_station/mainboard.c | 92 --
src/mainboard/amd/south_station/ramstage.c | 92 ++
src/mainboard/amd/thatcher/mainboard.c | 74 --
src/mainboard/amd/thatcher/ramstage.c | 74 ++
src/mainboard/amd/tilapia_fam10/mainboard.c | 295 -------
src/mainboard/amd/tilapia_fam10/ramstage.c | 295 +++++++
src/mainboard/amd/torpedo/mainboard.c | 68 --
src/mainboard/amd/torpedo/ramstage.c | 68 ++
src/mainboard/amd/union_station/mainboard.c | 65 --
src/mainboard/amd/union_station/ramstage.c | 65 ++
src/mainboard/aopen/dxplplusu/mainboard.c | 6 -
src/mainboard/aopen/dxplplusu/ramstage.c | 6 +
src/mainboard/arima/hdama/mainboard.c | 6 -
src/mainboard/arima/hdama/ramstage.c | 6 +
src/mainboard/artecgroup/dbe61/mainboard.c | 57 --
src/mainboard/artecgroup/dbe61/ramstage.c | 57 ++
src/mainboard/asi/mb_5blgp/mainboard.c | 25 -
src/mainboard/asi/mb_5blgp/ramstage.c | 25 +
src/mainboard/asi/mb_5blmp/mainboard.c | 26 -
src/mainboard/asi/mb_5blmp/ramstage.c | 26 +
src/mainboard/asrock/939a785gmh/mainboard.c | 137 ---
src/mainboard/asrock/939a785gmh/ramstage.c | 137 +++
src/mainboard/asrock/e350m1/mainboard.c | 64 --
src/mainboard/asrock/e350m1/ramstage.c | 64 ++
src/mainboard/asus/a8n_e/mainboard.c | 26 -
src/mainboard/asus/a8n_e/ramstage.c | 26 +
src/mainboard/asus/a8v-e_deluxe/mainboard.c | 27 -
src/mainboard/asus/a8v-e_deluxe/ramstage.c | 27 +
src/mainboard/asus/a8v-e_se/mainboard.c | 27 -
src/mainboard/asus/a8v-e_se/ramstage.c | 27 +
src/mainboard/asus/dsbf/mainboard.c | 40 -
src/mainboard/asus/dsbf/ramstage.c | 40 +
src/mainboard/asus/k8v-x/mainboard.c | 63 --
src/mainboard/asus/k8v-x/ramstage.c | 63 ++
src/mainboard/asus/m2n-e/mainboard.c | 38 -
src/mainboard/asus/m2n-e/ramstage.c | 38 +
src/mainboard/asus/m2v-mx_se/mainboard.c | 33 -
src/mainboard/asus/m2v-mx_se/ramstage.c | 33 +
src/mainboard/asus/m2v/mainboard.c | 59 --
src/mainboard/asus/m2v/ramstage.c | 59 ++
src/mainboard/asus/m4a78-em/mainboard.c | 133 ---
src/mainboard/asus/m4a78-em/ramstage.c | 133 +++
src/mainboard/asus/m4a785-m/mainboard.c | 209 -----
src/mainboard/asus/m4a785-m/ramstage.c | 209 +++++
src/mainboard/asus/m4a785t-m/mainboard.c | 21 -
src/mainboard/asus/m4a785t-m/ramstage.c | 21 +
src/mainboard/asus/m5a88-v/mainboard.c | 94 ---
src/mainboard/asus/m5a88-v/ramstage.c | 94 +++
src/mainboard/asus/mew-am/mainboard.c | 31 -
src/mainboard/asus/mew-am/ramstage.c | 31 +
src/mainboard/asus/mew-vm/mainboard.c | 11 -
src/mainboard/asus/mew-vm/ramstage.c | 11 +
src/mainboard/asus/p2b-d/mainboard.c | 25 -
src/mainboard/asus/p2b-d/ramstage.c | 25 +
src/mainboard/asus/p2b-ds/mainboard.c | 25 -
src/mainboard/asus/p2b-ds/ramstage.c | 25 +
src/mainboard/asus/p2b-f/mainboard.c | 25 -
src/mainboard/asus/p2b-f/ramstage.c | 25 +
src/mainboard/asus/p2b-ls/mainboard.c | 25 -
src/mainboard/asus/p2b-ls/ramstage.c | 25 +
src/mainboard/asus/p2b/mainboard.c | 25 -
src/mainboard/asus/p2b/ramstage.c | 25 +
src/mainboard/asus/p3b-f/mainboard.c | 25 -
src/mainboard/asus/p3b-f/ramstage.c | 25 +
src/mainboard/avalue/eax-785e/mainboard.c | 93 --
src/mainboard/avalue/eax-785e/ramstage.c | 93 ++
src/mainboard/axus/tc320/mainboard.c | 25 -
src/mainboard/axus/tc320/ramstage.c | 25 +
src/mainboard/azza/pt-6ibd/mainboard.c | 25 -
src/mainboard/azza/pt-6ibd/ramstage.c | 25 +
src/mainboard/bachmann/ot200/mainboard.c | 24 -
src/mainboard/bachmann/ot200/ramstage.c | 24 +
src/mainboard/bcom/winnet100/mainboard.c | 25 -
src/mainboard/bcom/winnet100/ramstage.c | 25 +
src/mainboard/bcom/winnetp680/mainboard.c | 26 -
src/mainboard/bcom/winnetp680/ramstage.c | 26 +
src/mainboard/bifferos/bifferboard/mainboard.c | 25 -
src/mainboard/bifferos/bifferboard/ramstage.c | 25 +
src/mainboard/biostar/m6tba/mainboard.c | 25 -
src/mainboard/biostar/m6tba/ramstage.c | 25 +
src/mainboard/broadcom/blast/mainboard.c | 6 -
src/mainboard/broadcom/blast/ramstage.c | 6 +
.../compaq/deskpro_en_sff_p600/mainboard.c | 25 -
.../compaq/deskpro_en_sff_p600/ramstage.c | 25 +
src/mainboard/digitallogic/adl855pc/mainboard.c | 6 -
src/mainboard/digitallogic/adl855pc/ramstage.c | 6 +
src/mainboard/digitallogic/msm586seg/mainboard.c | 135 ---
src/mainboard/digitallogic/msm586seg/ramstage.c | 135 +++
src/mainboard/digitallogic/msm586seg/romstage.c | 2 +-
src/mainboard/digitallogic/msm800sev/mainboard.c | 38 -
src/mainboard/digitallogic/msm800sev/ramstage.c | 38 +
src/mainboard/eaglelion/5bcm/mainboard.c | 6 -
src/mainboard/eaglelion/5bcm/ramstage.c | 6 +
src/mainboard/ecs/p6iwp-fe/mainboard.c | 31 -
src/mainboard/ecs/p6iwp-fe/ramstage.c | 31 +
src/mainboard/emulation/qemu-x86/mainboard.c | 76 --
src/mainboard/emulation/qemu-x86/ramstage.c | 76 ++
src/mainboard/getac/p470/mainboard.c | 104 ---
src/mainboard/getac/p470/ramstage.c | 104 +++
src/mainboard/gigabyte/ga-6bxc/mainboard.c | 25 -
src/mainboard/gigabyte/ga-6bxc/ramstage.c | 25 +
src/mainboard/gigabyte/ga-6bxe/mainboard.c | 25 -
src/mainboard/gigabyte/ga-6bxe/ramstage.c | 25 +
src/mainboard/gigabyte/ga_2761gxdk/mainboard.c | 30 -
src/mainboard/gigabyte/ga_2761gxdk/ramstage.c | 30 +
src/mainboard/gigabyte/m57sli/mainboard.c | 44 -
src/mainboard/gigabyte/m57sli/ramstage.c | 44 +
src/mainboard/gigabyte/ma785gm/mainboard.c | 155 ----
src/mainboard/gigabyte/ma785gm/ramstage.c | 155 ++++
src/mainboard/gigabyte/ma785gmt/mainboard.c | 266 ------
src/mainboard/gigabyte/ma785gmt/ramstage.c | 266 ++++++
src/mainboard/gigabyte/ma78gm/mainboard.c | 91 --
src/mainboard/gigabyte/ma78gm/ramstage.c | 91 ++
src/mainboard/hp/dl145_g1/mainboard.c | 28 -
src/mainboard/hp/dl145_g1/ramstage.c | 28 +
src/mainboard/hp/dl145_g3/mainboard.c | 33 -
src/mainboard/hp/dl145_g3/ramstage.c | 33 +
src/mainboard/hp/dl165_g6_fam10/mainboard.c | 33 -
src/mainboard/hp/dl165_g6_fam10/ramstage.c | 33 +
src/mainboard/hp/e_vectra_p2706t/mainboard.c | 31 -
src/mainboard/hp/e_vectra_p2706t/ramstage.c | 31 +
src/mainboard/ibase/mb899/mainboard.c | 237 ------
src/mainboard/ibase/mb899/ramstage.c | 237 ++++++
src/mainboard/ibm/e325/mainboard.c | 6 -
src/mainboard/ibm/e325/ramstage.c | 6 +
src/mainboard/ibm/e326/mainboard.c | 6 -
src/mainboard/ibm/e326/ramstage.c | 6 +
src/mainboard/iei/juki-511p/mainboard.c | 30 -
src/mainboard/iei/juki-511p/ramstage.c | 30 +
src/mainboard/iei/kino-780am2-fam10/mainboard.c | 73 --
src/mainboard/iei/kino-780am2-fam10/ramstage.c | 73 ++
src/mainboard/iei/nova4899r/mainboard.c | 30 -
src/mainboard/iei/nova4899r/ramstage.c | 30 +
src/mainboard/iei/pcisa-lx-800-r10/mainboard.c | 25 -
src/mainboard/iei/pcisa-lx-800-r10/ramstage.c | 25 +
src/mainboard/iei/pm-lx-800-r11/mainboard.c | 25 -
src/mainboard/iei/pm-lx-800-r11/ramstage.c | 25 +
src/mainboard/intel/d810e2cb/mainboard.c | 30 -
src/mainboard/intel/d810e2cb/ramstage.c | 30 +
src/mainboard/intel/d945gclf/mainboard.c | 28 -
src/mainboard/intel/d945gclf/ramstage.c | 28 +
src/mainboard/intel/eagleheights/mainboard.c | 35 -
src/mainboard/intel/eagleheights/ramstage.c | 35 +
src/mainboard/intel/emeraldlake2/mainboard.c | 249 ------
src/mainboard/intel/emeraldlake2/ramstage.c | 249 ++++++
src/mainboard/intel/jarrell/mainboard.c | 6 -
src/mainboard/intel/jarrell/ramstage.c | 6 +
src/mainboard/intel/mtarvon/mainboard.c | 26 -
src/mainboard/intel/mtarvon/ramstage.c | 26 +
src/mainboard/intel/truxton/mainboard.c | 26 -
src/mainboard/intel/truxton/ramstage.c | 26 +
src/mainboard/intel/xe7501devkit/mainboard.c | 6 -
src/mainboard/intel/xe7501devkit/ramstage.c | 6 +
src/mainboard/iwave/iWRainbowG6/mainboard.c | 40 -
src/mainboard/iwave/iWRainbowG6/ramstage.c | 40 +
src/mainboard/iwill/dk8_htx/mainboard.c | 5 -
src/mainboard/iwill/dk8_htx/ramstage.c | 5 +
src/mainboard/iwill/dk8s2/mainboard.c | 6 -
src/mainboard/iwill/dk8s2/ramstage.c | 6 +
src/mainboard/iwill/dk8x/mainboard.c | 6 -
src/mainboard/iwill/dk8x/ramstage.c | 6 +
src/mainboard/jetway/j7f24/mainboard.c | 26 -
src/mainboard/jetway/j7f24/ramstage.c | 26 +
src/mainboard/jetway/pa78vm5/mainboard.c | 120 ---
src/mainboard/jetway/pa78vm5/ramstage.c | 120 +++
src/mainboard/kontron/986lcd-m/mainboard.c | 283 -------
src/mainboard/kontron/986lcd-m/ramstage.c | 283 +++++++
src/mainboard/kontron/kt690/mainboard.c | 201 -----
src/mainboard/kontron/kt690/ramstage.c | 201 +++++
src/mainboard/lanner/em8510/mainboard.c | 26 -
src/mainboard/lanner/em8510/ramstage.c | 26 +
src/mainboard/lenovo/t60/mainboard.c | 104 ---
src/mainboard/lenovo/t60/ramstage.c | 104 +++
src/mainboard/lenovo/x60/mainboard.c | 116 ---
src/mainboard/lenovo/x60/ramstage.c | 116 +++
src/mainboard/lippert/frontrunner/mainboard.c | 6 -
src/mainboard/lippert/frontrunner/ramstage.c | 6 +
src/mainboard/lippert/hurricane-lx/mainboard.c | 88 --
src/mainboard/lippert/hurricane-lx/ramstage.c | 88 ++
src/mainboard/lippert/literunner-lx/mainboard.c | 92 --
src/mainboard/lippert/literunner-lx/ramstage.c | 92 ++
src/mainboard/lippert/roadrunner-lx/mainboard.c | 82 --
src/mainboard/lippert/roadrunner-lx/ramstage.c | 82 ++
src/mainboard/lippert/spacerunner-lx/mainboard.c | 87 --
src/mainboard/lippert/spacerunner-lx/ramstage.c | 87 ++
src/mainboard/mitac/6513wu/mainboard.c | 31 -
src/mainboard/mitac/6513wu/ramstage.c | 31 +
src/mainboard/msi/ms6119/mainboard.c | 25 -
src/mainboard/msi/ms6119/ramstage.c | 25 +
src/mainboard/msi/ms6147/mainboard.c | 25 -
src/mainboard/msi/ms6147/ramstage.c | 25 +
src/mainboard/msi/ms6156/mainboard.c | 25 -
src/mainboard/msi/ms6156/ramstage.c | 25 +
src/mainboard/msi/ms6178/mainboard.c | 31 -
src/mainboard/msi/ms6178/ramstage.c | 31 +
src/mainboard/msi/ms7135/mainboard.c | 25 -
src/mainboard/msi/ms7135/ramstage.c | 25 +
src/mainboard/msi/ms7260/mainboard.c | 41 -
src/mainboard/msi/ms7260/ramstage.c | 41 +
src/mainboard/msi/ms9185/mainboard.c | 30 -
src/mainboard/msi/ms9185/ramstage.c | 30 +
src/mainboard/msi/ms9282/mainboard.c | 44 -
src/mainboard/msi/ms9282/ramstage.c | 44 +
src/mainboard/msi/ms9652_fam10/mainboard.c | 44 -
src/mainboard/msi/ms9652_fam10/ramstage.c | 44 +
src/mainboard/nec/powermate2000/mainboard.c | 31 -
src/mainboard/nec/powermate2000/ramstage.c | 31 +
src/mainboard/newisys/khepri/mainboard.c | 6 -
src/mainboard/newisys/khepri/ramstage.c | 6 +
src/mainboard/nokia/ip530/mainboard.c | 25 -
src/mainboard/nokia/ip530/ramstage.c | 25 +
src/mainboard/nvidia/l1_2pvv/mainboard.c | 43 -
src/mainboard/nvidia/l1_2pvv/ramstage.c | 43 +
src/mainboard/pcengines/alix1c/mainboard.c | 38 -
src/mainboard/pcengines/alix1c/ramstage.c | 38 +
src/mainboard/pcengines/alix2d/mainboard.c | 38 -
src/mainboard/pcengines/alix2d/ramstage.c | 38 +
src/mainboard/rca/rm4100/mainboard.c | 44 -
src/mainboard/rca/rm4100/ramstage.c | 44 +
src/mainboard/roda/rk886ex/mainboard.c | 187 -----
src/mainboard/roda/rk886ex/ramstage.c | 187 +++++
src/mainboard/samsung/lumpy/mainboard.c | 331 --------
src/mainboard/samsung/lumpy/ramstage.c | 331 ++++++++
src/mainboard/samsung/stumpy/mainboard.c | 249 ------
src/mainboard/samsung/stumpy/ramstage.c | 249 ++++++
src/mainboard/siemens/sitemp_g1p1/mainboard.c | 881 --------------------
src/mainboard/siemens/sitemp_g1p1/ramstage.c | 881 ++++++++++++++++++++
src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c | 25 -
src/mainboard/soyo/sy-6ba-plus-iii/ramstage.c | 25 +
src/mainboard/sunw/ultra40/mainboard.c | 6 -
src/mainboard/sunw/ultra40/ramstage.c | 6 +
src/mainboard/supermicro/h8dme/mainboard.c | 25 -
src/mainboard/supermicro/h8dme/ramstage.c | 25 +
src/mainboard/supermicro/h8dmr/mainboard.c | 26 -
src/mainboard/supermicro/h8dmr/ramstage.c | 26 +
src/mainboard/supermicro/h8dmr_fam10/mainboard.c | 26 -
src/mainboard/supermicro/h8dmr_fam10/ramstage.c | 26 +
src/mainboard/supermicro/h8qgi/mainboard.c | 84 --
src/mainboard/supermicro/h8qgi/ramstage.c | 84 ++
src/mainboard/supermicro/h8qme_fam10/mainboard.c | 26 -
src/mainboard/supermicro/h8qme_fam10/ramstage.c | 26 +
src/mainboard/supermicro/h8scm_fam10/mainboard.c | 105 ---
src/mainboard/supermicro/h8scm_fam10/ramstage.c | 105 +++
src/mainboard/supermicro/x6dai_g/mainboard.c | 6 -
src/mainboard/supermicro/x6dai_g/ramstage.c | 6 +
src/mainboard/supermicro/x6dhe_g/mainboard.c | 6 -
src/mainboard/supermicro/x6dhe_g/ramstage.c | 6 +
src/mainboard/supermicro/x6dhe_g2/mainboard.c | 6 -
src/mainboard/supermicro/x6dhe_g2/ramstage.c | 6 +
src/mainboard/supermicro/x6dhr_ig/mainboard.c | 6 -
src/mainboard/supermicro/x6dhr_ig/ramstage.c | 6 +
src/mainboard/supermicro/x6dhr_ig2/mainboard.c | 6 -
src/mainboard/supermicro/x6dhr_ig2/ramstage.c | 6 +
src/mainboard/supermicro/x7db8/mainboard.c | 40 -
src/mainboard/supermicro/x7db8/ramstage.c | 40 +
src/mainboard/technexion/tim5690/mainboard.c | 257 ------
src/mainboard/technexion/tim5690/ramstage.c | 257 ++++++
src/mainboard/technexion/tim8690/mainboard.c | 160 ----
src/mainboard/technexion/tim8690/ramstage.c | 160 ++++
src/mainboard/technologic/ts5300/mainboard.c | 148 ----
src/mainboard/technologic/ts5300/ramstage.c | 148 ++++
src/mainboard/technologic/ts5300/romstage.c | 2 +-
src/mainboard/televideo/tc7020/mainboard.c | 26 -
src/mainboard/televideo/tc7020/ramstage.c | 26 +
src/mainboard/thomson/ip1000/mainboard.c | 167 ----
src/mainboard/thomson/ip1000/ramstage.c | 167 ++++
src/mainboard/traverse/geos/mainboard.c | 37 -
src/mainboard/traverse/geos/ramstage.c | 37 +
src/mainboard/tyan/s1846/mainboard.c | 25 -
src/mainboard/tyan/s1846/ramstage.c | 25 +
src/mainboard/tyan/s2735/mainboard.c | 6 -
src/mainboard/tyan/s2735/ramstage.c | 6 +
src/mainboard/tyan/s2850/mainboard.c | 6 -
src/mainboard/tyan/s2850/ramstage.c | 6 +
src/mainboard/tyan/s2875/mainboard.c | 6 -
src/mainboard/tyan/s2875/ramstage.c | 6 +
src/mainboard/tyan/s2880/mainboard.c | 6 -
src/mainboard/tyan/s2880/ramstage.c | 6 +
src/mainboard/tyan/s2881/mainboard.c | 27 -
src/mainboard/tyan/s2881/ramstage.c | 27 +
src/mainboard/tyan/s2882/mainboard.c | 6 -
src/mainboard/tyan/s2882/ramstage.c | 6 +
src/mainboard/tyan/s2885/mainboard.c | 6 -
src/mainboard/tyan/s2885/ramstage.c | 6 +
src/mainboard/tyan/s2891/mainboard.c | 6 -
src/mainboard/tyan/s2891/ramstage.c | 6 +
src/mainboard/tyan/s2892/mainboard.c | 6 -
src/mainboard/tyan/s2892/ramstage.c | 6 +
src/mainboard/tyan/s2895/mainboard.c | 6 -
src/mainboard/tyan/s2895/ramstage.c | 6 +
src/mainboard/tyan/s2912/mainboard.c | 26 -
src/mainboard/tyan/s2912/ramstage.c | 26 +
src/mainboard/tyan/s2912_fam10/mainboard.c | 26 -
src/mainboard/tyan/s2912_fam10/ramstage.c | 26 +
src/mainboard/tyan/s4880/mainboard.c | 6 -
src/mainboard/tyan/s4880/ramstage.c | 6 +
src/mainboard/tyan/s4882/mainboard.c | 6 -
src/mainboard/tyan/s4882/ramstage.c | 6 +
src/mainboard/via/epia-cn/mainboard.c | 26 -
src/mainboard/via/epia-cn/ramstage.c | 26 +
src/mainboard/via/epia-m/mainboard.c | 6 -
src/mainboard/via/epia-m/ramstage.c | 6 +
src/mainboard/via/epia-m700/mainboard.c | 25 -
src/mainboard/via/epia-m700/ramstage.c | 25 +
src/mainboard/via/epia-n/mainboard.c | 26 -
src/mainboard/via/epia-n/ramstage.c | 26 +
src/mainboard/via/epia/mainboard.c | 6 -
src/mainboard/via/epia/ramstage.c | 6 +
src/mainboard/via/pc2500e/mainboard.c | 25 -
src/mainboard/via/pc2500e/ramstage.c | 25 +
src/mainboard/via/vt8454c/mainboard.c | 27 -
src/mainboard/via/vt8454c/ramstage.c | 27 +
src/mainboard/winent/pl6064/mainboard.c | 37 -
src/mainboard/winent/pl6064/ramstage.c | 37 +
src/mainboard/wyse/s50/mainboard.c | 40 -
src/mainboard/wyse/s50/ramstage.c | 40 +
src/southbridge/amd/cimx/sb700/late.c | 2 +-
src/southbridge/amd/cimx/sb800/late.c | 2 +-
src/southbridge/amd/cimx/sb900/late.c | 2 +-
src/southbridge/amd/rs780/gfx.c | 2 +-
src/southbridge/amd/sb700/sata.c | 2 +-
src/southbridge/amd/sb700/sb700.h | 2 +-
src/southbridge/via/vt8237r/ide.c | 2 +-
366 files changed, 10779 insertions(+), 10779 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 306f239..e775d31 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -233,7 +233,7 @@ endif
# Things that appear in every board
romstage-srcs += $(objgenerated)/crt0.s
-ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
+ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ramstage.c
ifeq ($(CONFIG_GENERATE_MP_TABLE),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mptable.c
endif
diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h
index b177949..079c1a6 100644
--- a/src/arch/x86/include/arch/coreboot_tables.h
+++ b/src/arch/x86/include/arch/coreboot_tables.h
@@ -16,7 +16,7 @@ void lb_memory_range(struct lb_memory *mem,
*/
struct lb_memory *get_lb_mem(void);
-/* defined by mainboard.c if the mainboard requires extra resources */
+/* defined by ramstage.c if the mainboard requires extra resources */
int add_mainboard_resources(struct lb_memory *mem);
int add_northbridge_resources(struct lb_memory *mem);
diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c
index f3f7071..04e0def 100644
--- a/src/cpu/amd/sc520/raminit.c
+++ b/src/cpu/amd/sc520/raminit.c
@@ -90,7 +90,7 @@ void setupsc520(void)
/* PAR register setup */
/* set up the PAR registers as they are on the MSM586SEG */
/* moved to romstage.c by Stepan, Ron says: */
- /* NOTE: move this to mainboard.c ASAP */
+ /* NOTE: move this to ramstage.c ASAP */
setup_pars();
/* CPCSF register */
diff --git a/src/mainboard/a-trend/atc-6220/mainboard.c b/src/mainboard/a-trend/atc-6220/mainboard.c
deleted file mode 100644
index 26f18dd..0000000
--- a/src/mainboard/a-trend/atc-6220/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("A-Trend ATC-6220 Mainboard")
-};
diff --git a/src/mainboard/a-trend/atc-6220/ramstage.c b/src/mainboard/a-trend/atc-6220/ramstage.c
new file mode 100644
index 0000000..26f18dd
--- /dev/null
+++ b/src/mainboard/a-trend/atc-6220/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("A-Trend ATC-6220 Mainboard")
+};
diff --git a/src/mainboard/a-trend/atc-6240/mainboard.c b/src/mainboard/a-trend/atc-6240/mainboard.c
deleted file mode 100644
index 13f6e3f..0000000
--- a/src/mainboard/a-trend/atc-6240/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("A-Trend ATC-6240 Mainboard")
-};
diff --git a/src/mainboard/a-trend/atc-6240/ramstage.c b/src/mainboard/a-trend/atc-6240/ramstage.c
new file mode 100644
index 0000000..13f6e3f
--- /dev/null
+++ b/src/mainboard/a-trend/atc-6240/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("A-Trend ATC-6240 Mainboard")
+};
diff --git a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c
deleted file mode 100644
index 8f1412f..0000000
--- a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Mark Norman <mpnorman at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "AAEON PFM-540I_REVB ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "AAEON PFM-540I_REVB EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AAEON PFM-540I_REVB Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/aaeon/pfm-540i_revb/ramstage.c b/src/mainboard/aaeon/pfm-540i_revb/ramstage.c
new file mode 100644
index 0000000..8f1412f
--- /dev/null
+++ b/src/mainboard/aaeon/pfm-540i_revb/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Mark Norman <mpnorman at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "AAEON PFM-540I_REVB ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "AAEON PFM-540I_REVB EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AAEON PFM-540I_REVB Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/abit/be6-ii_v2_0/mainboard.c b/src/mainboard/abit/be6-ii_v2_0/mainboard.c
deleted file mode 100644
index c70df95..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Abit BE6-II V2.0 Mainboard")
-};
diff --git a/src/mainboard/abit/be6-ii_v2_0/ramstage.c b/src/mainboard/abit/be6-ii_v2_0/ramstage.c
new file mode 100644
index 0000000..c70df95
--- /dev/null
+++ b/src/mainboard/abit/be6-ii_v2_0/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Abit BE6-II V2.0 Mainboard")
+};
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
deleted file mode 100644
index 356ea1c..0000000
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "SBPLATFORM.h"
-
-
-u8 is_dev3_present(void);
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-void enable_int_gfx(void);
-
-/* GPIO6. */
-void enable_int_gfx(void)
-{
- volatile u8 *gpio_reg;
-
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
- /* make sure the Acpi MMIO(fed80000) is accessible */
- RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
-
- *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
- *(gpio_reg + 170) = 0x1; /* gpio_gate */
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
-
- *(gpio_reg + 0x6) = 0x8;
- *(gpio_reg + 170) = 0x0;
-}
-
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-
-/*************************************************
-* enable the dedicated function in A785E-I board.
-* This function called early than rs780_enable.
-*************************************************/
-static void a785e_i_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- enable_int_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ADVANSUS A785E-I Mainboard")
- .enable_dev = a785e_i_enable,
-};
diff --git a/src/mainboard/advansus/a785e-i/ramstage.c b/src/mainboard/advansus/a785e-i/ramstage.c
new file mode 100644
index 0000000..356ea1c
--- /dev/null
+++ b/src/mainboard/advansus/a785e-i/ramstage.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h"
+
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+ volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the Acpi MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+ *(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+ *(gpio_reg + 0x6) = 0x8;
+ *(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+
+/*************************************************
+* enable the dedicated function in A785E-I board.
+* This function called early than rs780_enable.
+*************************************************/
+static void a785e_i_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ADVANSUS A785E-I Mainboard")
+ .enable_dev = a785e_i_enable,
+};
diff --git a/src/mainboard/advantech/pcm-5820/mainboard.c b/src/mainboard/advantech/pcm-5820/mainboard.c
deleted file mode 100644
index 345c6f8..0000000
--- a/src/mainboard/advantech/pcm-5820/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Advantech PCM-5820 Mainboard")
-};
diff --git a/src/mainboard/advantech/pcm-5820/ramstage.c b/src/mainboard/advantech/pcm-5820/ramstage.c
new file mode 100644
index 0000000..345c6f8
--- /dev/null
+++ b/src/mainboard/advantech/pcm-5820/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Advantech PCM-5820 Mainboard")
+};
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
deleted file mode 100644
index aecb036..0000000
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb800/sb800.h>
-
-
-u8 is_dev3_present(void);
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-void enable_int_gfx(void);
-
-/* GPIO6. */
-void enable_int_gfx(void)
-{
- u8 byte;
-
- volatile u8 *gpio_reg;
-
- pm_iowrite(0xEA, 0x01); /* diable the PCIB */
- /* Disable Gec */
- byte = pm_ioread(0xF6);
- byte |= 1;
- pm_iowrite(0xF6, byte);
- /* make sure the fed80000 is accessible */
- byte = pm_ioread(0x24);
- byte |= 1;
- pm_iowrite(0x24, byte);
-
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
-
- *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
- *(gpio_reg + 170) = 0x1; /* gpio_gate */
-
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
-
- *(gpio_reg + 0x6) = 0x8;
- *(gpio_reg + 170) = 0x0;
-}
-
-/*
- * Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset(void)
-{
- /* GPIO 50h reset PCIe slot */
-/*
- u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
- u8 byte = ~(1 << 5);
- byte |= ~(1 << 6);
- *addr = byte;
-*/
-}
-
-void set_pcie_reset(void)
-{
- /* GPIO 50h reset PCIe slot */
-/*
- u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
- u8 byte = ~((1 << 5) | (1 << 6));
- *addr = byte;
-*/
-}
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-#if 0 /* not tested yet. */
-/********************************************************
-* bimini uses SB800 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66() */
-
-/*************************************************
-* enable the dedicated function in bimini board.
-* This function called early than rs780_enable.
-*************************************************/
-static void bimini_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- enable_int_gfx();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD Bimini Mainboard")
- .enable_dev = bimini_enable,
-};
diff --git a/src/mainboard/amd/bimini_fam10/ramstage.c b/src/mainboard/amd/bimini_fam10/ramstage.c
new file mode 100644
index 0000000..aecb036
--- /dev/null
+++ b/src/mainboard/amd/bimini_fam10/ramstage.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb800/sb800.h>
+
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+ u8 byte;
+
+ volatile u8 *gpio_reg;
+
+ pm_iowrite(0xEA, 0x01); /* diable the PCIB */
+ /* Disable Gec */
+ byte = pm_ioread(0xF6);
+ byte |= 1;
+ pm_iowrite(0xF6, byte);
+ /* make sure the fed80000 is accessible */
+ byte = pm_ioread(0x24);
+ byte |= 1;
+ pm_iowrite(0x24, byte);
+
+ gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+
+ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+ *(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+ gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+
+ *(gpio_reg + 0x6) = 0x8;
+ *(gpio_reg + 170) = 0x0;
+}
+
+/*
+ * Bimini uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset(void)
+{
+ /* GPIO 50h reset PCIe slot */
+/*
+ u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
+ u8 byte = ~(1 << 5);
+ byte |= ~(1 << 6);
+ *addr = byte;
+*/
+}
+
+void set_pcie_reset(void)
+{
+ /* GPIO 50h reset PCIe slot */
+/*
+ u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
+ u8 byte = ~((1 << 5) | (1 << 6));
+ *addr = byte;
+*/
+}
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+#if 0 /* not tested yet. */
+/********************************************************
+* bimini uses SB800 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif /* get_ide_dma66() */
+
+/*************************************************
+* enable the dedicated function in bimini board.
+* This function called early than rs780_enable.
+*************************************************/
+static void bimini_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ enable_int_gfx();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD Bimini Mainboard")
+ .enable_dev = bimini_enable,
+};
diff --git a/src/mainboard/amd/db800/mainboard.c b/src/mainboard/amd/db800/mainboard.c
deleted file mode 100644
index e841d07..0000000
--- a/src/mainboard/amd/db800/mainboard.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "AMD DB800 ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "AMD DB800 EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD DB800 Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/amd/db800/ramstage.c b/src/mainboard/amd/db800/ramstage.c
new file mode 100644
index 0000000..e841d07
--- /dev/null
+++ b/src/mainboard/amd/db800/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "AMD DB800 ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "AMD DB800 EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD DB800 Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
deleted file mode 100644
index 0121879..0000000
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/********************************************************
-* dbm690t uses a BCM5789 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by sb600 GPM3.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
-
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x40;
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-
- /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x80; /* 7:6=10 */
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-}
-
-/********************************************************
-* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- printk(BIOS_INFO, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in dbm690t board.
-* This function called early than rs690_enable.
-*************************************************/
-static void dbm690t_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- get_ide_dma66();
- set_thermal_config();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD DBM690T Mainboard")
- .enable_dev = dbm690t_enable,
-};
diff --git a/src/mainboard/amd/dbm690t/ramstage.c b/src/mainboard/amd/dbm690t/ramstage.c
new file mode 100644
index 0000000..0121879
--- /dev/null
+++ b/src/mainboard/amd/dbm690t/ramstage.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb600/sb600.h>
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+ u8 val);
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+
+/********************************************************
+* dbm690t uses a BCM5789 as on-board NIC.
+* It has a pin named LOW_POWER to enable it into LOW POWER state.
+* In order to run NIC, we should let it out of Low power state. This pin is
+* controlled by sb600 GPM3.
+* RRG4.2.3 GPM as GPIO
+* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
+* I/O C50, C51, C52, PM I/O94, 95, 96.
+* RRG4.2.3.1 GPM pins as Input
+* RRG4.2.3.2 GPM pins as Output
+********************************************************/
+static void enable_onboard_nic(void)
+{
+ u8 byte;
+
+ printk(BIOS_INFO, "%s.\n", __func__);
+
+ /* set index register 0C50h to 13h (miscellaneous control) */
+ outb(0x13, 0xC50); /* CMIndex */
+
+ /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x40;
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+
+ /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x80; /* 7:6=10 */
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+}
+
+/********************************************************
+* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ struct device *sm_dev;
+ struct device *ide_dev;
+
+ printk(BIOS_INFO, "%s.\n", __func__);
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb600 settings for thermal config */
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in dbm690t board.
+* This function called early than rs690_enable.
+*************************************************/
+static void dbm690t_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
+
+ enable_onboard_nic();
+ get_ide_dma66();
+ set_thermal_config();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD DBM690T Mainboard")
+ .enable_dev = dbm690t_enable,
+};
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
deleted file mode 100644
index af70ddc..0000000
--- a/src/mainboard/amd/dinar/mainboard.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <NbPlatform.h>
-
-//#define SMBUS_IO_BASE 0x6000
-
-void set_pcie_reset(void *nbconfig);
-void set_pcie_dereset(void *nbconfig);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
- //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
- u32 i;
- u32 val;
- u32 nb_addr;
-
- val = 0x00000007UL;
- AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
- for (i = 0; i < MAX_NB_COUNT; i ++) {
- nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
- LibNbPciIndexRMW(nb_addr,
- NB_HTIU_REGA8,
- AccessS3SaveWidth32,
- ~val,
- val,
- &(pConfig->Northbridges[i]));
- }
-}
-
-
-/*************************************************
- * enable the dedicated function in dinar board.
- *************************************************/
-static void dinar_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD DINAR Mainboard")
- .enable_dev = dinar_enable,
-};
diff --git a/src/mainboard/amd/dinar/ramstage.c b/src/mainboard/amd/dinar/ramstage.c
new file mode 100644
index 0000000..af70ddc
--- /dev/null
+++ b/src/mainboard/amd/dinar/ramstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <NbPlatform.h>
+
+//#define SMBUS_IO_BASE 0x6000
+
+void set_pcie_reset(void *nbconfig);
+void set_pcie_dereset(void *nbconfig);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void *nbconfig)
+{
+}
+
+/**
+ * Mainboard specific RD890 CIMx callback
+ * Release Resets to PCIe Links
+ * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie
+ */
+void set_pcie_dereset(void *nbconfig)
+{
+ //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+ u32 i;
+ u32 val;
+ u32 nb_addr;
+
+ val = 0x00000007UL;
+ AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
+ for (i = 0; i < MAX_NB_COUNT; i ++) {
+ nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
+ LibNbPciIndexRMW(nb_addr,
+ NB_HTIU_REGA8,
+ AccessS3SaveWidth32,
+ ~val,
+ val,
+ &(pConfig->Northbridges[i]));
+ }
+}
+
+
+/*************************************************
+ * enable the dedicated function in dinar board.
+ *************************************************/
+static void dinar_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD DINAR Mainboard")
+ .enable_dev = dinar_enable,
+};
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
deleted file mode 100644
index 9099a4d..0000000
--- a/src/mainboard/amd/inagua/mainboard.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-//#include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
- /**
- * GPIO32 Pcie Device DeAssert for APU
- * GPIO25 Pcie LAN, APU GPP2
- * GPIO02 MINIPCIE SLOT1, APU GPP3
- * GPIO50 Pcie Device DeAssert for Hudson Southbridge
- * GPIO05 Express Card, SB GPP0
- * GPIO26 NEC USB3.0GPPUSB, SB GPP1
- * GPIO00 MINIPCIE SLOT2, SB GPP2
- * GPIO05 Pcie X1 Slot, SB GPP3
- */
-
- /* Multi-function pins switch to GPIO0-35, these pins are shared with
- * PCI pins, make sure Husson PCI device is disabled.
- */
- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
-
- /* select IOMux to function1/2, corresponds to GPIO */
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
-
-
- /* output low */
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
-}
-
-
-/*************************************************
- * enable the dedicated function in INAGUA board.
- *************************************************/
-static void inagua_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- /* Inagua mainboard specific setting */
- set_pcie_dereset();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = inagua_enable,
-};
diff --git a/src/mainboard/amd/inagua/ramstage.c b/src/mainboard/amd/inagua/ramstage.c
new file mode 100644
index 0000000..9099a4d
--- /dev/null
+++ b/src/mainboard/amd/inagua/ramstage.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb800/sb800.h>
+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+ /**
+ * GPIO32 Pcie Device DeAssert for APU
+ * GPIO25 Pcie LAN, APU GPP2
+ * GPIO02 MINIPCIE SLOT1, APU GPP3
+ * GPIO50 Pcie Device DeAssert for Hudson Southbridge
+ * GPIO05 Express Card, SB GPP0
+ * GPIO26 NEC USB3.0GPPUSB, SB GPP1
+ * GPIO00 MINIPCIE SLOT2, SB GPP2
+ * GPIO05 Pcie X1 Slot, SB GPP3
+ */
+
+ /* Multi-function pins switch to GPIO0-35, these pins are shared with
+ * PCI pins, make sure Husson PCI device is disabled.
+ */
+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+
+ /* select IOMux to function1/2, corresponds to GPIO */
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
+
+
+ /* output low */
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
+}
+
+
+/*************************************************
+ * enable the dedicated function in INAGUA board.
+ *************************************************/
+static void inagua_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ /* Inagua mainboard specific setting */
+ set_pcie_dereset();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = inagua_enable,
+};
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
deleted file mode 100644
index 66d0d28..0000000
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-/*
- * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-void set_pcie_reset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-#if 0 /* not tested yet */
-/********************************************************
-* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66 */
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mahogany_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD MAHOGANY Mainboard")
- .enable_dev = mahogany_enable,
-};
diff --git a/src/mainboard/amd/mahogany/ramstage.c b/src/mainboard/amd/mahogany/ramstage.c
new file mode 100644
index 0000000..66d0d28
--- /dev/null
+++ b/src/mainboard/amd/mahogany/ramstage.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+/*
+ * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+#if 0 /* not tested yet */
+/********************************************************
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif /* get_ide_dma66 */
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+/*************************************************
+* enable the dedicated function in mahogany board.
+* This function called early than rs780_enable.
+*************************************************/
+static void mahogany_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD MAHOGANY Mainboard")
+ .enable_dev = mahogany_enable,
+};
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
deleted file mode 100644
index d1701fd..0000000
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-/*
- * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-void set_pcie_reset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-#if 0 /* not tested yet. */
-/********************************************************
-* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66() */
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mahogany_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD MAHOGANY Mainboard")
- .enable_dev = mahogany_enable,
-};
diff --git a/src/mainboard/amd/mahogany_fam10/ramstage.c b/src/mainboard/amd/mahogany_fam10/ramstage.c
new file mode 100644
index 0000000..d1701fd
--- /dev/null
+++ b/src/mainboard/amd/mahogany_fam10/ramstage.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+/*
+ * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+#if 0 /* not tested yet. */
+/********************************************************
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif /* get_ide_dma66() */
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in mahogany board.
+* This function called early than rs780_enable.
+*************************************************/
+static void mahogany_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD MAHOGANY Mainboard")
+ .enable_dev = mahogany_enable,
+};
diff --git a/src/mainboard/amd/norwich/mainboard.c b/src/mainboard/amd/norwich/mainboard.c
deleted file mode 100644
index c735abb..0000000
--- a/src/mainboard/amd/norwich/mainboard.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Norwich ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "Norwich EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD Norwich Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/amd/norwich/ramstage.c b/src/mainboard/amd/norwich/ramstage.c
new file mode 100644
index 0000000..c735abb
--- /dev/null
+++ b/src/mainboard/amd/norwich/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Norwich ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "Norwich EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD Norwich Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
deleted file mode 100644
index 095f02f..0000000
--- a/src/mainboard/amd/parmer/mainboard.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <arch/acpi.h>
-#include "BiosCallOuts.h"
-#include <cpu/amd/agesa/s3_resume.h>
-#include "agesawrapper.h"
-
-/*************************************************
- * enable the dedicated function in parmer board.
- *************************************************/
-static void parmer_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- /*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the approriate AGESA/CIMx resume functions.
- */
-#if CONFIG_HAVE_ACPI_RESUME == 1
- acpi_slp_type = acpi_get_sleep_type();
- if (acpi_slp_type == 3)
- agesawrapper_fchs3earlyrestore();
-#endif
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = parmer_enable,
-};
diff --git a/src/mainboard/amd/parmer/ramstage.c b/src/mainboard/amd/parmer/ramstage.c
new file mode 100644
index 0000000..095f02f
--- /dev/null
+++ b/src/mainboard/amd/parmer/ramstage.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include "BiosCallOuts.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include "agesawrapper.h"
+
+/*************************************************
+ * enable the dedicated function in parmer board.
+ *************************************************/
+static void parmer_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ /*
+ * The mainboard is the first place that we get control in ramstage. Check
+ * for S3 resume and call the approriate AGESA/CIMx resume functions.
+ */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ acpi_slp_type = acpi_get_sleep_type();
+ if (acpi_slp_type == 3)
+ agesawrapper_fchs3earlyrestore();
+#endif
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = parmer_enable,
+};
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
deleted file mode 100644
index 3bf05db..0000000
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb800/sb800.h>
-#include <arch/acpi.h>
-#include "BiosCallOuts.h"
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cpu/amd/mtrr.h>
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
-/*************************************************
-* enable the dedicated function in persimmon board.
-*************************************************/
-static void persimmon_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-/*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the approriate AGESA/CIMx resume functions.
- */
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = acpi_get_sleep_type();
-#endif
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = persimmon_enable,
-};
diff --git a/src/mainboard/amd/persimmon/ramstage.c b/src/mainboard/amd/persimmon/ramstage.c
new file mode 100644
index 0000000..3bf05db
--- /dev/null
+++ b/src/mainboard/amd/persimmon/ramstage.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb800/sb800.h>
+#include <arch/acpi.h>
+#include "BiosCallOuts.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/amd/mtrr.h>
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+
+/*************************************************
+* enable the dedicated function in persimmon board.
+*************************************************/
+static void persimmon_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+/*
+ * The mainboard is the first place that we get control in ramstage. Check
+ * for S3 resume and call the approriate AGESA/CIMx resume functions.
+ */
+#if CONFIG_HAVE_ACPI_RESUME
+ acpi_slp_type = acpi_get_sleep_type();
+#endif
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = persimmon_enable,
+};
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
deleted file mode 100644
index 32912f4..0000000
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7475_ADDRESS 0x2E
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7475_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
-#define ADT7475_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
-
-
-/********************************************************
-* pistachio uses a BCM5787 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by GPM8.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-* The R77 (on BRASS) / R81 (on Bronze) is not load!
-* So NIC can work whether this function runs.
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* enable GPM8 output */
- byte = pm_ioread(0x95);
- byte &= 0xfe;
- pm_iowrite(0x95, byte);
-
- /* GPM8 outputs low. */
- byte = pm_ioread(0x94);
- byte &= 0xfe;
- pm_iowrite(0x94, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte, byte2;
- u16 word;
- u32 dword;
- device_t sm_dev;
-
- /* set adt7475 */
- ADT7475_write_byte(0x40, 0x04);
- /* Config Register 6 */
- ADT7475_write_byte(0x10, 0x00);
- /* Config Register 7 */
- ADT7475_write_byte(0x11, 0x00);
-
- /* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
- ADT7475_write_byte(0x7c, 0xa0);
- /* No offset for remote 2 */
- ADT7475_write_byte(0x72, 0x00);
- /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
- ADT7475_write_byte(0x5c, 0x02);
- /* PWM 3 configuration register Case fan controlled by 690 temp */
- ADT7475_write_byte(0x5e, 0x42);
-
- /* remote 1 low temp limit */
- ADT7475_write_byte(0x4e, 0x00);
- /* remote 1 High temp limit (90C) */
- ADT7475_write_byte(0x4f, 0x9a);
-
- /* remote2 Low Temp Limit */
- ADT7475_write_byte(0x52, 0x00);
- /* remote2 High Limit (90C) */
- ADT7475_write_byte(0x53, 0x9a);
-
- /* remote 1 therm temp limit (95C) */
- ADT7475_write_byte(0x6a, 0x9f);
- /* remote 2 therm temp limit (95C) */
- ADT7475_write_byte(0x6c, 0x9f);
-
- /* PWM 1 minimum duty cycle (37%) */
- ADT7475_write_byte(0x64, 0x60);
- /* PWM 1 Maximum duty cycle (100%) */
- ADT7475_write_byte(0x38, 0xff);
- /* PWM 3 minimum duty cycle (37%) */
- ADT7475_write_byte(0x66, 0x60);
- /* PWM 3 Maximum Duty Cycle (100%) */
- ADT7475_write_byte(0x3a, 0xff);
-
- /* Remote 1 temperature Tmin (32C) */
- ADT7475_write_byte(0x67, 0x60);
- /* Remote 2 temperature Tmin (32C) */
- ADT7475_write_byte(0x69, 0x60);
- /* remote 1 Trange (53C ramp range) */
- ADT7475_write_byte(0x5f, 0xe8);
- /* remote 2 Trange (53C ramp range) */
- ADT7475_write_byte(0x61, 0xe8);
-
- /* PWM2 Duty cycle */
- ADT7475_write_byte(0x65, 0x00);
- /* PWM2 Disabled */
- ADT7475_write_byte(0x5d, 0x80);
- /* PWM2 Max Duty Cycle */
- ADT7475_write_byte(0x39, 0x00);
-
- /* Config Register 3 - enable smbalert & therm */
- ADT7475_write_byte(0x78, 0x03);
- /* Config Register 4 - enable therm output */
- ADT7475_write_byte(0x7d, 0x09);
- /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
- ADT7475_write_byte(0x75, 0x2a);
- /* Config Register 1 Set Start bit */
- ADT7475_write_byte(0x40, 0x05);
- /* Read status register to clear any old errors */
- byte2 = ADT7475_read_byte(0x42);
- byte = ADT7475_read_byte(0x41);
-
- /* remote 1 temperature offset */
- ADT7475_write_byte(0x70, 0x00);
-
- printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
- byte2, byte);
-
- /* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
- /* set GPM5 as GPM5, not DDR3_memory disable */
- byte = pm_ioread(0x8f);
- byte |= 1 << 6; /* enable GPE */
- pm_iowrite(0x8f, byte);
-
- /* GPM5 as GPIO not USB OC */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword = pci_read_config32(sm_dev, 0x64);
- dword |= 1 << 19;
- pci_write_config32(sm_dev, 0x64, dword);
-
- /* Enable Client Management Index/Data registers */
- dword = pci_read_config32(sm_dev, 0x78);
- dword |= 1 << 11; /* Cms_enable */
- pci_write_config32(sm_dev, 0x78, dword);
-
- /* MiscfuncEnable */
- byte = pci_read_config8(sm_dev, 0x41);
- byte |= (1 << 5);
- pci_write_config8(sm_dev, 0x41, byte);
-
- /* set GPM5 as input */
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51); /* CMData */
- byte &= 0x3f;
- byte |= 1 << 6;
- outb(byte, 0xC51);
- /* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */
- byte = inb(0xc52); /* GpmPort */
- byte |= 1 << 5;
- outb(byte, 0xc52);
- /* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
- byte = inb(0xc51);
- byte &= 0x3f;
- outb(byte, 0xc51);
-
- /* trigger SCI/SMI */
- byte = pm_ioread(0x34);
- byte &= 0xcf;
- pm_iowrite(0x34, byte);
-
- /* set GPM5 to not wake from s5 */
- byte = pm_ioread(0x77);
- byte &= ~(1 << 5);
- pm_iowrite(0x77, byte);
-
- /* trigger on falling edge */
- byte = pm_ioread(0x38);
- byte &= ~(1 << 2);
- pm_iowrite(0x38, byte);
-
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in pistachio board.
-* This function called early than rs690_enable.
-*************************************************/
-static void pistachio_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- set_thermal_config();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD Pistachio Mainboard")
- .enable_dev = pistachio_enable,
-};
diff --git a/src/mainboard/amd/pistachio/ramstage.c b/src/mainboard/amd/pistachio/ramstage.c
new file mode 100644
index 0000000..32912f4
--- /dev/null
+++ b/src/mainboard/amd/pistachio/ramstage.c
@@ -0,0 +1,270 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb600/sb600.h>
+
+#define ADT7475_ADDRESS 0x2E
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+ u8 val);
+#define ADT7475_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
+#define ADT7475_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
+
+
+/********************************************************
+* pistachio uses a BCM5787 as on-board NIC.
+* It has a pin named LOW_POWER to enable it into LOW POWER state.
+* In order to run NIC, we should let it out of Low power state. This pin is
+* controlled by GPM8.
+* RRG4.2.3 GPM as GPIO
+* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
+* I/O C50, C51, C52, PM I/O94, 95, 96.
+* RRG4.2.3.1 GPM pins as Input
+* RRG4.2.3.2 GPM pins as Output
+* The R77 (on BRASS) / R81 (on Bronze) is not load!
+* So NIC can work whether this function runs.
+********************************************************/
+static void enable_onboard_nic(void)
+{
+ u8 byte;
+
+ printk(BIOS_INFO, "%s.\n", __func__);
+
+ /* enable GPM8 output */
+ byte = pm_ioread(0x95);
+ byte &= 0xfe;
+ pm_iowrite(0x95, byte);
+
+ /* GPM8 outputs low. */
+ byte = pm_ioread(0x94);
+ byte &= 0xfe;
+ pm_iowrite(0x94, byte);
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte, byte2;
+ u16 word;
+ u32 dword;
+ device_t sm_dev;
+
+ /* set adt7475 */
+ ADT7475_write_byte(0x40, 0x04);
+ /* Config Register 6 */
+ ADT7475_write_byte(0x10, 0x00);
+ /* Config Register 7 */
+ ADT7475_write_byte(0x11, 0x00);
+
+ /* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
+ ADT7475_write_byte(0x7c, 0xa0);
+ /* No offset for remote 2 */
+ ADT7475_write_byte(0x72, 0x00);
+ /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
+ ADT7475_write_byte(0x5c, 0x02);
+ /* PWM 3 configuration register Case fan controlled by 690 temp */
+ ADT7475_write_byte(0x5e, 0x42);
+
+ /* remote 1 low temp limit */
+ ADT7475_write_byte(0x4e, 0x00);
+ /* remote 1 High temp limit (90C) */
+ ADT7475_write_byte(0x4f, 0x9a);
+
+ /* remote2 Low Temp Limit */
+ ADT7475_write_byte(0x52, 0x00);
+ /* remote2 High Limit (90C) */
+ ADT7475_write_byte(0x53, 0x9a);
+
+ /* remote 1 therm temp limit (95C) */
+ ADT7475_write_byte(0x6a, 0x9f);
+ /* remote 2 therm temp limit (95C) */
+ ADT7475_write_byte(0x6c, 0x9f);
+
+ /* PWM 1 minimum duty cycle (37%) */
+ ADT7475_write_byte(0x64, 0x60);
+ /* PWM 1 Maximum duty cycle (100%) */
+ ADT7475_write_byte(0x38, 0xff);
+ /* PWM 3 minimum duty cycle (37%) */
+ ADT7475_write_byte(0x66, 0x60);
+ /* PWM 3 Maximum Duty Cycle (100%) */
+ ADT7475_write_byte(0x3a, 0xff);
+
+ /* Remote 1 temperature Tmin (32C) */
+ ADT7475_write_byte(0x67, 0x60);
+ /* Remote 2 temperature Tmin (32C) */
+ ADT7475_write_byte(0x69, 0x60);
+ /* remote 1 Trange (53C ramp range) */
+ ADT7475_write_byte(0x5f, 0xe8);
+ /* remote 2 Trange (53C ramp range) */
+ ADT7475_write_byte(0x61, 0xe8);
+
+ /* PWM2 Duty cycle */
+ ADT7475_write_byte(0x65, 0x00);
+ /* PWM2 Disabled */
+ ADT7475_write_byte(0x5d, 0x80);
+ /* PWM2 Max Duty Cycle */
+ ADT7475_write_byte(0x39, 0x00);
+
+ /* Config Register 3 - enable smbalert & therm */
+ ADT7475_write_byte(0x78, 0x03);
+ /* Config Register 4 - enable therm output */
+ ADT7475_write_byte(0x7d, 0x09);
+ /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
+ ADT7475_write_byte(0x75, 0x2a);
+ /* Config Register 1 Set Start bit */
+ ADT7475_write_byte(0x40, 0x05);
+ /* Read status register to clear any old errors */
+ byte2 = ADT7475_read_byte(0x42);
+ byte = ADT7475_read_byte(0x41);
+
+ /* remote 1 temperature offset */
+ ADT7475_write_byte(0x70, 0x00);
+
+ printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
+ byte2, byte);
+
+ /* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
+ /* set GPM5 as GPM5, not DDR3_memory disable */
+ byte = pm_ioread(0x8f);
+ byte |= 1 << 6; /* enable GPE */
+ pm_iowrite(0x8f, byte);
+
+ /* GPM5 as GPIO not USB OC */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ dword = pci_read_config32(sm_dev, 0x64);
+ dword |= 1 << 19;
+ pci_write_config32(sm_dev, 0x64, dword);
+
+ /* Enable Client Management Index/Data registers */
+ dword = pci_read_config32(sm_dev, 0x78);
+ dword |= 1 << 11; /* Cms_enable */
+ pci_write_config32(sm_dev, 0x78, dword);
+
+ /* MiscfuncEnable */
+ byte = pci_read_config8(sm_dev, 0x41);
+ byte |= (1 << 5);
+ pci_write_config8(sm_dev, 0x41, byte);
+
+ /* set GPM5 as input */
+ /* set index register 0C50h to 13h (miscellaneous control) */
+ outb(0x13, 0xC50); /* CMIndex */
+ /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
+ byte = inb(0xC51); /* CMData */
+ byte &= 0x3f;
+ byte |= 1 << 6;
+ outb(byte, 0xC51);
+ /* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */
+ byte = inb(0xc52); /* GpmPort */
+ byte |= 1 << 5;
+ outb(byte, 0xc52);
+ /* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
+ byte = inb(0xc51);
+ byte &= 0x3f;
+ outb(byte, 0xc51);
+
+ /* trigger SCI/SMI */
+ byte = pm_ioread(0x34);
+ byte &= 0xcf;
+ pm_iowrite(0x34, byte);
+
+ /* set GPM5 to not wake from s5 */
+ byte = pm_ioread(0x77);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x77, byte);
+
+ /* trigger on falling edge */
+ byte = pm_ioread(0x38);
+ byte &= ~(1 << 2);
+ pm_iowrite(0x38, byte);
+
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in pistachio board.
+* This function called early than rs690_enable.
+*************************************************/
+static void pistachio_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
+
+ enable_onboard_nic();
+ set_thermal_config();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD Pistachio Mainboard")
+ .enable_dev = pistachio_enable,
+};
diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c
deleted file mode 100644
index 42547cc..0000000
--- a/src/mainboard/amd/rumba/mainboard.c
+++ /dev/null
@@ -1,39 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-
-static void init(struct device *dev)
-{
- device_t nic = NULL;
- unsigned bus = 0;
- unsigned devfn = PCI_DEVFN(0xd, 0);
- int nicirq = 1;
-
- printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);
-
- if (nicirq) {
- printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n",
- __func__, bus, devfn, nicirq);
- nic = dev_find_slot(bus, devfn);
- if (! nic){
- printk(BIOS_ERR, "Could not find NIC\n");
- } else {
- pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);
- }
- }
- printk(BIOS_DEBUG, "AMD RUMBA EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD Rumba Mainboard")
- .enable_dev = enable_dev,
-};
-
diff --git a/src/mainboard/amd/rumba/ramstage.c b/src/mainboard/amd/rumba/ramstage.c
new file mode 100644
index 0000000..42547cc
--- /dev/null
+++ b/src/mainboard/amd/rumba/ramstage.c
@@ -0,0 +1,39 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void init(struct device *dev)
+{
+ device_t nic = NULL;
+ unsigned bus = 0;
+ unsigned devfn = PCI_DEVFN(0xd, 0);
+ int nicirq = 1;
+
+ printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);
+
+ if (nicirq) {
+ printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n",
+ __func__, bus, devfn, nicirq);
+ nic = dev_find_slot(bus, devfn);
+ if (! nic){
+ printk(BIOS_ERR, "Could not find NIC\n");
+ } else {
+ pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);
+ }
+ }
+ printk(BIOS_DEBUG, "AMD RUMBA EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD Rumba Mainboard")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c
deleted file mode 100644
index a156f2e..0000000
--- a/src/mainboard/amd/serengeti_cheetah/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD Serengeti Cheetah Mainboard")
-};
-
diff --git a/src/mainboard/amd/serengeti_cheetah/ramstage.c b/src/mainboard/amd/serengeti_cheetah/ramstage.c
new file mode 100644
index 0000000..a156f2e
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD Serengeti Cheetah Mainboard")
+};
+
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
deleted file mode 100644
index 9984bd6..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD family 10 Cheetah mainboard")
-};
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/ramstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/ramstage.c
new file mode 100644
index 0000000..9984bd6
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/ramstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD family 10 Cheetah mainboard")
+};
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
deleted file mode 100644
index dbfce2b..0000000
--- a/src/mainboard/amd/south_station/mainboard.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-/**
- * Southstation using SB GPIO 17/18 to control the Red/Green LED
- * These two LEDs can be used to show the OS booting status.
- */
-static void southstation_led_init(void)
-{
-#define GPIO_FUNCTION 2 //GPIO function
-#define SB_GPIO_REG17 17 //Red Light
-#define SB_GPIO_REG18 18 //Green Light
-
- /* multi-function pins switch to GPIO0-35 */
- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
-
- /* select IOMux to function2, corresponds to GPIO */
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
-
- /* Lighting test */
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
- mdelay(100);
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
-}
-
-
-/*************************************************
-* enable the dedicated function in southstation board.
-*************************************************/
-static void southstation_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- southstation_led_init();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = southstation_enable,
-};
diff --git a/src/mainboard/amd/south_station/ramstage.c b/src/mainboard/amd/south_station/ramstage.c
new file mode 100644
index 0000000..dbfce2b
--- /dev/null
+++ b/src/mainboard/amd/south_station/ramstage.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+/**
+ * Southstation using SB GPIO 17/18 to control the Red/Green LED
+ * These two LEDs can be used to show the OS booting status.
+ */
+static void southstation_led_init(void)
+{
+#define GPIO_FUNCTION 2 //GPIO function
+#define SB_GPIO_REG17 17 //Red Light
+#define SB_GPIO_REG18 18 //Green Light
+
+ /* multi-function pins switch to GPIO0-35 */
+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+
+ /* select IOMux to function2, corresponds to GPIO */
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
+
+ /* Lighting test */
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
+ mdelay(100);
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
+}
+
+
+/*************************************************
+* enable the dedicated function in southstation board.
+*************************************************/
+static void southstation_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ southstation_led_init();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = southstation_enable,
+};
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
deleted file mode 100644
index b2a01d4..0000000
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <arch/acpi.h>
-#include "BiosCallOuts.h"
-#include <cpu/amd/agesa/s3_resume.h>
-#include "agesawrapper.h"
-
-/*************************************************
- * enable the dedicated function in thatcher board.
- *************************************************/
-static void thatcher_enable(device_t dev)
-{
- msr_t msr;
-
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- msr = rdmsr(0xC0011020);
- msr.lo &= ~(1 << 28);
- wrmsr(0xC0011020, msr);
-
- msr = rdmsr(0xC0011022);
- msr.lo &= ~(1 << 4);
- msr.lo &= ~(1 << 13);
- wrmsr(0xC0011022, msr);
-
- msr = rdmsr(0xC0011023);
- msr.lo &= ~(1 << 23);
- wrmsr(0xC0011023, msr);
-
- /*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the approriate AGESA/CIMx resume functions.
- */
-#if CONFIG_HAVE_ACPI_RESUME == 1
- acpi_slp_type = acpi_get_sleep_type();
- if (acpi_slp_type == 3)
- agesawrapper_fchs3earlyrestore();
-
-#endif
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = thatcher_enable,
-};
diff --git a/src/mainboard/amd/thatcher/ramstage.c b/src/mainboard/amd/thatcher/ramstage.c
new file mode 100644
index 0000000..b2a01d4
--- /dev/null
+++ b/src/mainboard/amd/thatcher/ramstage.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include "BiosCallOuts.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include "agesawrapper.h"
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void thatcher_enable(device_t dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(0xC0011020);
+ msr.lo &= ~(1 << 28);
+ wrmsr(0xC0011020, msr);
+
+ msr = rdmsr(0xC0011022);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(0xC0011022, msr);
+
+ msr = rdmsr(0xC0011023);
+ msr.lo &= ~(1 << 23);
+ wrmsr(0xC0011023, msr);
+
+ /*
+ * The mainboard is the first place that we get control in ramstage. Check
+ * for S3 resume and call the approriate AGESA/CIMx resume functions.
+ */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ acpi_slp_type = acpi_get_sleep_type();
+ if (acpi_slp_type == 3)
+ agesawrapper_fchs3earlyrestore();
+
+#endif
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = thatcher_enable,
+};
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
deleted file mode 100644
index f655513..0000000
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include "southbridge/amd/sb700/smbus.h"
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-void set_pcie_dereset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 1 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte |= ((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 1 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word |= (1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 0 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte &= ~((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 0 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-#if 0 /* TODO: */
-/********************************************************
-* tilapia uses SB700 GPIO8 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 4); /* Set Gpio8 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif
-
-/*
- * justify the dev3 is exist or not
- */
-u8 is_dev3_present(void)
-{
- u16 word;
- device_t sm_dev;
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
-
- /* read the GPIO68 input status */
- word = pci_read_config16(sm_dev, 0x7e);
-
- if(word & (1 << 10)){
- /*not exist*/
- return 0;
- }else{
- /*exist*/
- return 1;
- }
-}
-
-
-/*
- * set gpio40 gfx
- */
-static void set_gpio40_gfx(void)
-{
- u8 byte;
- u32 dword;
- device_t sm_dev;
- /* disable the GPIO40 as CLKREQ2# function */
- byte = pm_ioread(0xd3);
- byte &= ~(1 << 7);
- pm_iowrite(0xd3, byte);
-
- /* disable the GPIO40 as CLKREQ3# function */
- byte = pm_ioread(0xd4);
- byte &= ~(1 << 0);
- pm_iowrite(0xd4, byte);
-
- /* enable pull up for GPIO68 */
- byte = pm2_ioread(0xf1);
- byte &= ~(1 << 4);
- pm2_iowrite(0xf1, byte);
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /*if the dev3 is present, set the gfx to 2x8 lanes*/
- /*otherwise set the gfx to 1x16 lanes*/
- if(is_dev3_present()){
-
- printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword |= (1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
-
- }else{
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
- }
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb700 settings for thermal config */
- /* set SB700 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in tilapia board.
-* This function called early than rs780_enable.
-*************************************************/
-static void tilapia_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
- set_thermal_config();
- set_gpio40_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD TILAPIA Mainboard")
- .enable_dev = tilapia_enable,
-};
diff --git a/src/mainboard/amd/tilapia_fam10/ramstage.c b/src/mainboard/amd/tilapia_fam10/ramstage.c
new file mode 100644
index 0000000..f655513
--- /dev/null
+++ b/src/mainboard/amd/tilapia_fam10/ramstage.c
@@ -0,0 +1,295 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 1 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte |= ((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 1 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= (1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 0 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte &= ~((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 0 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word &= ~(1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+#if 0 /* TODO: */
+/********************************************************
+* tilapia uses SB700 GPIO8 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 4); /* Set Gpio8 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif
+
+/*
+ * justify the dev3 is exist or not
+ */
+u8 is_dev3_present(void)
+{
+ u16 word;
+ device_t sm_dev;
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* put the GPIO68 output to tristate */
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= 1 << 6;
+ pci_write_config16(sm_dev, 0x7e,word);
+
+ /* read the GPIO68 input status */
+ word = pci_read_config16(sm_dev, 0x7e);
+
+ if(word & (1 << 10)){
+ /*not exist*/
+ return 0;
+ }else{
+ /*exist*/
+ return 1;
+ }
+}
+
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+ u8 byte;
+ u32 dword;
+ device_t sm_dev;
+ /* disable the GPIO40 as CLKREQ2# function */
+ byte = pm_ioread(0xd3);
+ byte &= ~(1 << 7);
+ pm_iowrite(0xd3, byte);
+
+ /* disable the GPIO40 as CLKREQ3# function */
+ byte = pm_ioread(0xd4);
+ byte &= ~(1 << 0);
+ pm_iowrite(0xd4, byte);
+
+ /* enable pull up for GPIO68 */
+ byte = pm2_ioread(0xf1);
+ byte &= ~(1 << 4);
+ pm2_iowrite(0xf1, byte);
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /*if the dev3 is present, set the gfx to 2x8 lanes*/
+ /*otherwise set the gfx to 1x16 lanes*/
+ if(is_dev3_present()){
+
+ printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword |= (1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+
+ }else{
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+ }
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb700 settings for thermal config */
+ /* set SB700 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in tilapia board.
+* This function called early than rs780_enable.
+*************************************************/
+static void tilapia_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+ set_thermal_config();
+ set_gpio40_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD TILAPIA Mainboard")
+ .enable_dev = tilapia_enable,
+};
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
deleted file mode 100644
index 91e3ead..0000000
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-//#include <southbridge/amd/sb900/sb900.h>
-
-#define ONE_MB 0x100000
-//#define SMBUS_IO_BASE 0x6000
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
-/*************************************************
-* enable the dedicated function in torpedo board.
-*************************************************/
-static void torpedo_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = torpedo_enable,
-};
diff --git a/src/mainboard/amd/torpedo/ramstage.c b/src/mainboard/amd/torpedo/ramstage.c
new file mode 100644
index 0000000..91e3ead
--- /dev/null
+++ b/src/mainboard/amd/torpedo/ramstage.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb900/sb900.h>
+
+#define ONE_MB 0x100000
+//#define SMBUS_IO_BASE 0x6000
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+
+/*************************************************
+* enable the dedicated function in torpedo board.
+*************************************************/
+static void torpedo_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = torpedo_enable,
+};
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
deleted file mode 100644
index d8324bc..0000000
--- a/src/mainboard/amd/union_station/mainboard.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
-/*************************************************
-* enable the dedicated function in unionstation board.
-*************************************************/
-static void unionstation_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = unionstation_enable,
-};
diff --git a/src/mainboard/amd/union_station/ramstage.c b/src/mainboard/amd/union_station/ramstage.c
new file mode 100644
index 0000000..d8324bc
--- /dev/null
+++ b/src/mainboard/amd/union_station/ramstage.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+
+/*************************************************
+* enable the dedicated function in unionstation board.
+*************************************************/
+static void unionstation_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = unionstation_enable,
+};
diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c
deleted file mode 100644
index 0688914..0000000
--- a/src/mainboard/aopen/dxplplusu/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AOpen DXPL Plus-U Mainboard")
-};
-
diff --git a/src/mainboard/aopen/dxplplusu/ramstage.c b/src/mainboard/aopen/dxplplusu/ramstage.c
new file mode 100644
index 0000000..0688914
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AOpen DXPL Plus-U Mainboard")
+};
+
diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c
deleted file mode 100644
index df658e2..0000000
--- a/src/mainboard/arima/hdama/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Arima HDAMA Mainboard")
-};
-
diff --git a/src/mainboard/arima/hdama/ramstage.c b/src/mainboard/arima/hdama/ramstage.c
new file mode 100644
index 0000000..df658e2
--- /dev/null
+++ b/src/mainboard/arima/hdama/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Arima HDAMA Mainboard")
+};
+
diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c
deleted file mode 100644
index 649f955..0000000
--- a/src/mainboard/artecgroup/dbe61/mainboard.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright (C) 2007 Advanced Micro Devices
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-static void init_gpio(void)
-{
- msr_t msr;
- printk(BIOS_DEBUG, "Checking GPIO module...\n");
-
- msr = rdmsr(MDD_LBAR_GPIO);
- printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
-}
-
-static void init(struct device *dev)
-{
- // BOARD-SPECIFIC INIT
- printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
-
- init_gpio();
-
- printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Artec Group dbe61 Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/artecgroup/dbe61/ramstage.c b/src/mainboard/artecgroup/dbe61/ramstage.c
new file mode 100644
index 0000000..649f955
--- /dev/null
+++ b/src/mainboard/artecgroup/dbe61/ramstage.c
@@ -0,0 +1,57 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+static void init_gpio(void)
+{
+ msr_t msr;
+ printk(BIOS_DEBUG, "Checking GPIO module...\n");
+
+ msr = rdmsr(MDD_LBAR_GPIO);
+ printk(BIOS_DEBUG, "DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
+}
+
+static void init(struct device *dev)
+{
+ // BOARD-SPECIFIC INIT
+ printk(BIOS_DEBUG, "ARTECGROUP DBE61 ENTER %s\n", __func__);
+
+ init_gpio();
+
+ printk(BIOS_DEBUG, "ARTECGROUP DBE61 EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Artec Group dbe61 Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/asi/mb_5blgp/mainboard.c b/src/mainboard/asi/mb_5blgp/mainboard.c
deleted file mode 100644
index 7a466bd..0000000
--- a/src/mainboard/asi/mb_5blgp/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASI MB-5BLGP Mainboard")
-};
diff --git a/src/mainboard/asi/mb_5blgp/ramstage.c b/src/mainboard/asi/mb_5blgp/ramstage.c
new file mode 100644
index 0000000..7a466bd
--- /dev/null
+++ b/src/mainboard/asi/mb_5blgp/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASI MB-5BLGP Mainboard")
+};
diff --git a/src/mainboard/asi/mb_5blmp/mainboard.c b/src/mainboard/asi/mb_5blmp/mainboard.c
deleted file mode 100644
index 9aaf14d..0000000
--- a/src/mainboard/asi/mb_5blmp/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
-};
-
diff --git a/src/mainboard/asi/mb_5blmp/ramstage.c b/src/mainboard/asi/mb_5blmp/ramstage.c
new file mode 100644
index 0000000..9aaf14d
--- /dev/null
+++ b/src/mainboard/asi/mb_5blmp/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
+};
+
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
deleted file mode 100644
index 7526c6b..0000000
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-static void pcie_rst_toggle(u8 val) {
- u8 byte;
-
- byte = pm_ioread(0x8d);
- byte &= ~(3 << 1);
- pm_iowrite(0x8d, byte);
-
- byte = pm_ioread(0x94);
- /* Output enable */
- byte &= ~(3 << 2);
- /* Toggle GPM8, GPM9 */
- byte &= ~(3 << 0);
- byte |= val;
- pm_iowrite(0x94, byte);
-}
-
-void set_pcie_dereset()
-{
- pcie_rst_toggle(0x3);
-}
-
-void set_pcie_reset()
-{
- pcie_rst_toggle(0x0);
-}
-
-#if 0 /* not tested yet */
-/********************************************************
-* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66 */
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mb_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Asrock 939A785GMH/128M Mainboard")
- .enable_dev = mb_enable,
-};
-
-/* override the default SATA PHY setup */
-void sb7xx_51xx_setup_sata_phys(struct device *dev) {
- /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
- pci_write_config16(dev, 0x86, 0x2c00);
-
- /* RPR7.6.2 SATA GENI PHY ports setting */
- pci_write_config32(dev, 0x88, 0x01B48016);
- pci_write_config32(dev, 0x8c, 0x01B48016);
- pci_write_config32(dev, 0x90, 0x01B48016);
- pci_write_config32(dev, 0x94, 0x01B48016);
- pci_write_config32(dev, 0x98, 0x01B48016);
- pci_write_config32(dev, 0x9C, 0x01B48016);
-
- /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
- pci_write_config16(dev, 0xA0, 0xA07A);
- pci_write_config16(dev, 0xA2, 0xA07A);
- pci_write_config16(dev, 0xA4, 0xA07A);
- pci_write_config16(dev, 0xA6, 0xA07A);
- pci_write_config16(dev, 0xA8, 0xA07A);
- pci_write_config16(dev, 0xAA, 0xA0FF);
-}
diff --git a/src/mainboard/asrock/939a785gmh/ramstage.c b/src/mainboard/asrock/939a785gmh/ramstage.c
new file mode 100644
index 0000000..7526c6b
--- /dev/null
+++ b/src/mainboard/asrock/939a785gmh/ramstage.c
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+
+static void pcie_rst_toggle(u8 val) {
+ u8 byte;
+
+ byte = pm_ioread(0x8d);
+ byte &= ~(3 << 1);
+ pm_iowrite(0x8d, byte);
+
+ byte = pm_ioread(0x94);
+ /* Output enable */
+ byte &= ~(3 << 2);
+ /* Toggle GPM8, GPM9 */
+ byte &= ~(3 << 0);
+ byte |= val;
+ pm_iowrite(0x94, byte);
+}
+
+void set_pcie_dereset()
+{
+ pcie_rst_toggle(0x3);
+}
+
+void set_pcie_reset()
+{
+ pcie_rst_toggle(0x0);
+}
+
+#if 0 /* not tested yet */
+/********************************************************
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif /* get_ide_dma66 */
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in mahogany board.
+* This function called early than rs780_enable.
+*************************************************/
+static void mb_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Asrock 939A785GMH/128M Mainboard")
+ .enable_dev = mb_enable,
+};
+
+/* override the default SATA PHY setup */
+void sb7xx_51xx_setup_sata_phys(struct device *dev) {
+ /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+ pci_write_config16(dev, 0x86, 0x2c00);
+
+ /* RPR7.6.2 SATA GENI PHY ports setting */
+ pci_write_config32(dev, 0x88, 0x01B48016);
+ pci_write_config32(dev, 0x8c, 0x01B48016);
+ pci_write_config32(dev, 0x90, 0x01B48016);
+ pci_write_config32(dev, 0x94, 0x01B48016);
+ pci_write_config32(dev, 0x98, 0x01B48016);
+ pci_write_config32(dev, 0x9C, 0x01B48016);
+
+ /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+ pci_write_config16(dev, 0xA0, 0xA07A);
+ pci_write_config16(dev, 0xA2, 0xA07A);
+ pci_write_config16(dev, 0xA4, 0xA07A);
+ pci_write_config16(dev, 0xA6, 0xA07A);
+ pci_write_config16(dev, 0xA8, 0xA07A);
+ pci_write_config16(dev, 0xAA, 0xA0FF);
+}
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
deleted file mode 100644
index 9a76cce..0000000
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-//#include <southbridge/amd/sb800/sb800.h>
-
-//#define SMBUS_IO_BASE 0x6000
-
-/**
- * TODO
- * SB CIMx callback
- */
-void set_pcie_reset(void)
-{
-}
-
-/**
- * TODO
- * mainboard specific SB CIMx callback
- */
-void set_pcie_dereset(void)
-{
-}
-
-
-/*************************************************
-* enable the dedicated function in e350m1 board.
-*************************************************/
-static void e350m1_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = e350m1_enable,
-};
diff --git a/src/mainboard/asrock/e350m1/ramstage.c b/src/mainboard/asrock/e350m1/ramstage.c
new file mode 100644
index 0000000..9a76cce
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/ramstage.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb800/sb800.h>
+
+//#define SMBUS_IO_BASE 0x6000
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+
+/*************************************************
+* enable the dedicated function in e350m1 board.
+*************************************************/
+static void e350m1_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = e350m1_enable,
+};
diff --git a/src/mainboard/asus/a8n_e/mainboard.c b/src/mainboard/asus/a8n_e/mainboard.c
deleted file mode 100644
index aedca67..0000000
--- a/src/mainboard/asus/a8n_e/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Philipp Degler <pdegler at rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS A8N-E Mainboard")
-};
diff --git a/src/mainboard/asus/a8n_e/ramstage.c b/src/mainboard/asus/a8n_e/ramstage.c
new file mode 100644
index 0000000..aedca67
--- /dev/null
+++ b/src/mainboard/asus/a8n_e/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Philipp Degler <pdegler at rumms.uni-mannheim.de>
+ * (Thanks to LSRA University of Mannheim for their support)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS A8N-E Mainboard")
+};
diff --git a/src/mainboard/asus/a8v-e_deluxe/mainboard.c b/src/mainboard/asus/a8v-e_deluxe/mainboard.c
deleted file mode 100644
index cb38be2..0000000
--- a/src/mainboard/asus/a8v-e_deluxe/mainboard.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS A8V-E Deluxe Mainboard")
-};
diff --git a/src/mainboard/asus/a8v-e_deluxe/ramstage.c b/src/mainboard/asus/a8v-e_deluxe/ramstage.c
new file mode 100644
index 0000000..cb38be2
--- /dev/null
+++ b/src/mainboard/asus/a8v-e_deluxe/ramstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS A8V-E Deluxe Mainboard")
+};
diff --git a/src/mainboard/asus/a8v-e_se/mainboard.c b/src/mainboard/asus/a8v-e_se/mainboard.c
deleted file mode 100644
index c119e1c..0000000
--- a/src/mainboard/asus/a8v-e_se/mainboard.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS A8V-E SE Mainboard")
-};
diff --git a/src/mainboard/asus/a8v-e_se/ramstage.c b/src/mainboard/asus/a8v-e_se/ramstage.c
new file mode 100644
index 0000000..c119e1c
--- /dev/null
+++ b/src/mainboard/asus/a8v-e_se/ramstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS A8V-E SE Mainboard")
+};
diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c
deleted file mode 100644
index 618eca9..0000000
--- a/src/mainboard/asus/dsbf/mainboard.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <delay.h>
-#include <arch/coreboot_tables.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-
-static void mainboard_enable(device_t dev)
-{
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/asus/dsbf/ramstage.c b/src/mainboard/asus/dsbf/ramstage.c
new file mode 100644
index 0000000..618eca9
--- /dev/null
+++ b/src/mainboard/asus/dsbf/ramstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
deleted file mode 100644
index 82d8ba0..0000000
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- device_t lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- /* select function GPIO29 for pin AB9 */
- pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 29 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 8 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS K8V-X Mainboard")
-};
diff --git a/src/mainboard/asus/k8v-x/ramstage.c b/src/mainboard/asus/k8v-x/ramstage.c
new file mode 100644
index 0000000..82d8ba0
--- /dev/null
+++ b/src/mainboard/asus/k8v-x/ramstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+
+u32 vt8237_ide_80pin_detect(struct device *dev)
+{
+ device_t lpc_dev;
+ u16 acpi_io_base;
+ u32 gpio_in;
+ u32 res;
+
+ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+ if (!lpc_dev)
+ return 0;
+
+ acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
+ if (!acpi_io_base)
+ return 0;
+
+ /* select function GPIO29 for pin AB9 */
+ pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
+
+ gpio_in = inl(acpi_io_base + 0x48);
+ /* bit 29 for primary port, clear if unconnected or 80-pin cable */
+ res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
+ /* bit 8 for secondary port, clear if unconnected or 80-pin cable */
+ res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
+
+ printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
+ res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
+ printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
+ res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
+
+ return res;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS K8V-X Mainboard")
+};
diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c
deleted file mode 100644
index 0d7013f..0000000
--- a/src/mainboard/asus/m2n-e/mainboard.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include "hda_verb.h"
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS M2N-E Mainboard")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/asus/m2n-e/ramstage.c b/src/mainboard/asus/m2n-e/ramstage.c
new file mode 100644
index 0000000..0d7013f
--- /dev/null
+++ b/src/mainboard/asus/m2n-e/ramstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2N-E Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
deleted file mode 100644
index 5e3c720..0000000
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <boot/tables.h>
-#include <southbridge/via/k8t890/k8t890.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS M2V-MX SE Mainboard")
-};
diff --git a/src/mainboard/asus/m2v-mx_se/ramstage.c b/src/mainboard/asus/m2v-mx_se/ramstage.c
new file mode 100644
index 0000000..5e3c720
--- /dev/null
+++ b/src/mainboard/asus/m2v-mx_se/ramstage.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <boot/tables.h>
+#include <southbridge/via/k8t890/k8t890.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2V-MX SE Mainboard")
+};
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
deleted file mode 100644
index 2a44851..0000000
--- a/src/mainboard/asus/m2v/mainboard.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- device_t lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 9 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1<<9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 4 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS M2V")
-};
diff --git a/src/mainboard/asus/m2v/ramstage.c b/src/mainboard/asus/m2v/ramstage.c
new file mode 100644
index 0000000..2a44851
--- /dev/null
+++ b/src/mainboard/asus/m2v/ramstage.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+
+u32 vt8237_ide_80pin_detect(struct device *dev)
+{
+ device_t lpc_dev;
+ u16 acpi_io_base;
+ u32 gpio_in;
+ u32 res;
+
+ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+ if (!lpc_dev)
+ return 0;
+
+ acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
+ if (!acpi_io_base)
+ return 0;
+
+ gpio_in = inl(acpi_io_base + 0x48);
+ /* bit 9 for primary port, clear if unconnected or 80-pin cable */
+ res = gpio_in & (1<<9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
+ /* bit 4 for secondary port, clear if unconnected or 80-pin cable */
+ res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
+
+ printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
+ res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
+ printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
+ res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
+
+ return res;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2V")
+};
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
deleted file mode 100644
index 738e854..0000000
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-void set_pcie_dereset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 1 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte |= ((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 1 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word |= (1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 0 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte &= ~((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 0 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * justify the dev3 is exist or not
- * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown if it will work at all for this board.
- */
-u8 is_dev3_present(void)
-{
- u16 word;
- device_t sm_dev;
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
-
- /* read the GPIO68 input status */
- word = pci_read_config16(sm_dev, 0x7e);
-
- if(word & (1 << 10)){
- /*not exist*/
- return 0;
- }else{
- /*exist*/
- return 1;
- }
-}
-
-
-/*************************************************
-* enable the dedicated function in this board.
-* This function called early than rs780_enable.
-*************************************************/
-static void m4a78em_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
- /* set_thermal_config(); */
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS M4A78-EM Mainboard")
- .enable_dev = m4a78em_enable,
-};
diff --git a/src/mainboard/asus/m4a78-em/ramstage.c b/src/mainboard/asus/m4a78-em/ramstage.c
new file mode 100644
index 0000000..738e854
--- /dev/null
+++ b/src/mainboard/asus/m4a78-em/ramstage.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 1 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte |= ((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 1 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= (1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 0 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte &= ~((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 0 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word &= ~(1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * justify the dev3 is exist or not
+ * NOTE: This just copied from AMD Tilapia code.
+ * It is completly unknown if it will work at all for this board.
+ */
+u8 is_dev3_present(void)
+{
+ u16 word;
+ device_t sm_dev;
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* put the GPIO68 output to tristate */
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= 1 << 6;
+ pci_write_config16(sm_dev, 0x7e,word);
+
+ /* read the GPIO68 input status */
+ word = pci_read_config16(sm_dev, 0x7e);
+
+ if(word & (1 << 10)){
+ /*not exist*/
+ return 0;
+ }else{
+ /*exist*/
+ return 1;
+ }
+}
+
+
+/*************************************************
+* enable the dedicated function in this board.
+* This function called early than rs780_enable.
+*************************************************/
+static void m4a78em_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+ /* set_thermal_config(); */
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M4A78-EM Mainboard")
+ .enable_dev = m4a78em_enable,
+};
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
deleted file mode 100644
index 5230f84..0000000
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-void set_pcie_dereset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 1 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte |= ((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 1 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word |= (1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 0 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte &= ~((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 0 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * justify the dev3 is exist or not
- * NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown it it will work at all for ASUS M4A785-M.
- */
-u8 is_dev3_present(void)
-{
- u16 word;
- device_t sm_dev;
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
-
- /* read the GPIO68 input status */
- word = pci_read_config16(sm_dev, 0x7e);
-
- if(word & (1 << 10)){
- /*not exist*/
- return 0;
- }else{
- /*exist*/
- return 1;
- }
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb700 settings for thermal config */
- /* set SB700 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in this board.
-* This function called early than rs780_enable.
-*************************************************/
-static void m4a785m_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
- set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
-#ifdef CONFIG_BOARD_ASUS_M4A785TM
- CHIP_NAME("ASUS M4A785T-M Mainboard")
-#else
- CHIP_NAME("ASUS M4A785-M Mainboard")
-#endif
- .enable_dev = m4a785m_enable,
-};
diff --git a/src/mainboard/asus/m4a785-m/ramstage.c b/src/mainboard/asus/m4a785-m/ramstage.c
new file mode 100644
index 0000000..5230f84
--- /dev/null
+++ b/src/mainboard/asus/m4a785-m/ramstage.c
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 1 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte |= ((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 1 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= (1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 0 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte &= ~((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 0 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word &= ~(1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * justify the dev3 is exist or not
+ * NOTE: This just copied from AMD Tilapia code.
+ * It is completly unknown it it will work at all for ASUS M4A785-M.
+ */
+u8 is_dev3_present(void)
+{
+ u16 word;
+ device_t sm_dev;
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* put the GPIO68 output to tristate */
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= 1 << 6;
+ pci_write_config16(sm_dev, 0x7e,word);
+
+ /* read the GPIO68 input status */
+ word = pci_read_config16(sm_dev, 0x7e);
+
+ if(word & (1 << 10)){
+ /*not exist*/
+ return 0;
+ }else{
+ /*exist*/
+ return 1;
+ }
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb700 settings for thermal config */
+ /* set SB700 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in this board.
+* This function called early than rs780_enable.
+*************************************************/
+static void m4a785m_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+ set_thermal_config();
+}
+
+struct chip_operations mainboard_ops = {
+#ifdef CONFIG_BOARD_ASUS_M4A785TM
+ CHIP_NAME("ASUS M4A785T-M Mainboard")
+#else
+ CHIP_NAME("ASUS M4A785-M Mainboard")
+#endif
+ .enable_dev = m4a785m_enable,
+};
diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c
deleted file mode 100644
index 76a2a68..0000000
--- a/src/mainboard/asus/m4a785t-m/mainboard.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "../m4a785-m/mainboard.c"
diff --git a/src/mainboard/asus/m4a785t-m/ramstage.c b/src/mainboard/asus/m4a785t-m/ramstage.c
new file mode 100644
index 0000000..10f17ea
--- /dev/null
+++ b/src/mainboard/asus/m4a785t-m/ramstage.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "../m4a785-m/ramstage.c"
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
deleted file mode 100644
index bbb1482..0000000
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "SBPLATFORM.h"
-
-
-u8 is_dev3_present(void);
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-void enable_int_gfx(void);
-
-/* GPIO6. */
-void enable_int_gfx(void)
-{
- volatile u8 *gpio_reg;
-
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
- /* make sure the MMIO(fed80000) is accessible */
- RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
-
- *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
- *(gpio_reg + 170) = 0x1; /* gpio_gate */
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
-
- *(gpio_reg + 0x6) = 0x8;
- *(gpio_reg + 170) = 0x0;
-}
-
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-
-/*************************************************
-* enable the dedicated function in M5A88-V board.
-* This function called early than rs780_enable.
-*************************************************/
-static void m5a88pm_v_enable(device_t dev)
-{
-
- printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- enable_int_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS M5A88-V Mainboard")
- .enable_dev = m5a88pm_v_enable,
-};
diff --git a/src/mainboard/asus/m5a88-v/ramstage.c b/src/mainboard/asus/m5a88-v/ramstage.c
new file mode 100644
index 0000000..bbb1482
--- /dev/null
+++ b/src/mainboard/asus/m5a88-v/ramstage.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h"
+
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+ volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+ *(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+ *(gpio_reg + 0x6) = 0x8;
+ *(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+
+/*************************************************
+* enable the dedicated function in M5A88-V board.
+* This function called early than rs780_enable.
+*************************************************/
+static void m5a88pm_v_enable(device_t dev)
+{
+
+ printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M5A88-V Mainboard")
+ .enable_dev = m5a88pm_v_enable,
+};
diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c
deleted file mode 100644
index 6409dab..0000000
--- a/src/mainboard/asus/mew-am/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS MEW-AM Mainboard")
-};
diff --git a/src/mainboard/asus/mew-am/ramstage.c b/src/mainboard/asus/mew-am/ramstage.c
new file mode 100644
index 0000000..6409dab
--- /dev/null
+++ b/src/mainboard/asus/mew-am/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS MEW-AM Mainboard")
+};
diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c
deleted file mode 100644
index 2e43be2..0000000
--- a/src/mainboard/asus/mew-vm/mainboard.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS MEW-VM Mainboard")
-};
diff --git a/src/mainboard/asus/mew-vm/ramstage.c b/src/mainboard/asus/mew-vm/ramstage.c
new file mode 100644
index 0000000..2e43be2
--- /dev/null
+++ b/src/mainboard/asus/mew-vm/ramstage.c
@@ -0,0 +1,11 @@
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS MEW-VM Mainboard")
+};
diff --git a/src/mainboard/asus/p2b-d/mainboard.c b/src/mainboard/asus/p2b-d/mainboard.c
deleted file mode 100644
index 3fe9dc4..0000000
--- a/src/mainboard/asus/p2b-d/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P2B-D Mainboard")
-};
diff --git a/src/mainboard/asus/p2b-d/ramstage.c b/src/mainboard/asus/p2b-d/ramstage.c
new file mode 100644
index 0000000..3fe9dc4
--- /dev/null
+++ b/src/mainboard/asus/p2b-d/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P2B-D Mainboard")
+};
diff --git a/src/mainboard/asus/p2b-ds/mainboard.c b/src/mainboard/asus/p2b-ds/mainboard.c
deleted file mode 100644
index c874137..0000000
--- a/src/mainboard/asus/p2b-ds/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P2B-DS Mainboard")
-};
diff --git a/src/mainboard/asus/p2b-ds/ramstage.c b/src/mainboard/asus/p2b-ds/ramstage.c
new file mode 100644
index 0000000..c874137
--- /dev/null
+++ b/src/mainboard/asus/p2b-ds/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P2B-DS Mainboard")
+};
diff --git a/src/mainboard/asus/p2b-f/mainboard.c b/src/mainboard/asus/p2b-f/mainboard.c
deleted file mode 100644
index e5d2e14..0000000
--- a/src/mainboard/asus/p2b-f/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P2B-F Mainboard")
-};
diff --git a/src/mainboard/asus/p2b-f/ramstage.c b/src/mainboard/asus/p2b-f/ramstage.c
new file mode 100644
index 0000000..e5d2e14
--- /dev/null
+++ b/src/mainboard/asus/p2b-f/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P2B-F Mainboard")
+};
diff --git a/src/mainboard/asus/p2b-ls/mainboard.c b/src/mainboard/asus/p2b-ls/mainboard.c
deleted file mode 100644
index 9f250f4..0000000
--- a/src/mainboard/asus/p2b-ls/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P2B-LS Mainboard")
-};
diff --git a/src/mainboard/asus/p2b-ls/ramstage.c b/src/mainboard/asus/p2b-ls/ramstage.c
new file mode 100644
index 0000000..9f250f4
--- /dev/null
+++ b/src/mainboard/asus/p2b-ls/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P2B-LS Mainboard")
+};
diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c
deleted file mode 100644
index 527dc7a..0000000
--- a/src/mainboard/asus/p2b/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P2B Mainboard")
-};
diff --git a/src/mainboard/asus/p2b/ramstage.c b/src/mainboard/asus/p2b/ramstage.c
new file mode 100644
index 0000000..527dc7a
--- /dev/null
+++ b/src/mainboard/asus/p2b/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P2B Mainboard")
+};
diff --git a/src/mainboard/asus/p3b-f/mainboard.c b/src/mainboard/asus/p3b-f/mainboard.c
deleted file mode 100644
index 9b41c79..0000000
--- a/src/mainboard/asus/p3b-f/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ASUS P3B-F Mainboard")
-};
diff --git a/src/mainboard/asus/p3b-f/ramstage.c b/src/mainboard/asus/p3b-f/ramstage.c
new file mode 100644
index 0000000..9b41c79
--- /dev/null
+++ b/src/mainboard/asus/p3b-f/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS P3B-F Mainboard")
+};
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
deleted file mode 100644
index 0cc655e..0000000
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "SBPLATFORM.h"
-
-
-u8 is_dev3_present(void);
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-void enable_int_gfx(void);
-
-/* GPIO6. */
-void enable_int_gfx(void)
-{
- volatile u8 *gpio_reg;
-
-#ifdef UNUSED_CODE
- RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
- RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
-#endif
- /* make sure the Acpi MMIO(fed80000) is accessible */
- RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
-
- *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
- *(gpio_reg + 170) = 0x1; /* gpio_gate */
-
- gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
-
- *(gpio_reg + 0x6) = 0x8;
- *(gpio_reg + 170) = 0x0;
-}
-
-void set_pcie_dereset()
-{
-}
-
-void set_pcie_reset(void)
-{
-}
-
-u8 is_dev3_present(void)
-{
- return 1;
-}
-
-
-/*************************************************
-* enable the dedicated function in EAX-785E board.
-* This function called early than rs780_enable.
-*************************************************/
-static void eax_785e(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- set_pcie_dereset();
- enable_int_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = eax_785e,
-};
diff --git a/src/mainboard/avalue/eax-785e/ramstage.c b/src/mainboard/avalue/eax-785e/ramstage.c
new file mode 100644
index 0000000..0cc655e
--- /dev/null
+++ b/src/mainboard/avalue/eax-785e/ramstage.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "SBPLATFORM.h"
+
+
+u8 is_dev3_present(void);
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+void enable_int_gfx(void);
+
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+ volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the Acpi MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+ *(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+ *(gpio_reg + 0x6) = 0x8;
+ *(gpio_reg + 170) = 0x0;
+}
+
+void set_pcie_dereset()
+{
+}
+
+void set_pcie_reset(void)
+{
+}
+
+u8 is_dev3_present(void)
+{
+ return 1;
+}
+
+
+/*************************************************
+* enable the dedicated function in EAX-785E board.
+* This function called early than rs780_enable.
+*************************************************/
+static void eax_785e(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ set_pcie_dereset();
+ enable_int_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = eax_785e,
+};
diff --git a/src/mainboard/axus/tc320/mainboard.c b/src/mainboard/axus/tc320/mainboard.c
deleted file mode 100644
index af52755..0000000
--- a/src/mainboard/axus/tc320/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AXUS TC320 Mainboard")
-};
diff --git a/src/mainboard/axus/tc320/ramstage.c b/src/mainboard/axus/tc320/ramstage.c
new file mode 100644
index 0000000..af52755
--- /dev/null
+++ b/src/mainboard/axus/tc320/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AXUS TC320 Mainboard")
+};
diff --git a/src/mainboard/azza/pt-6ibd/mainboard.c b/src/mainboard/azza/pt-6ibd/mainboard.c
deleted file mode 100644
index 483f328..0000000
--- a/src/mainboard/azza/pt-6ibd/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AZZA PT-6IBD Mainboard")
-};
diff --git a/src/mainboard/azza/pt-6ibd/ramstage.c b/src/mainboard/azza/pt-6ibd/ramstage.c
new file mode 100644
index 0000000..483f328
--- /dev/null
+++ b/src/mainboard/azza/pt-6ibd/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AZZA PT-6IBD Mainboard")
+};
diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c
deleted file mode 100644
index 76b3c53..0000000
--- a/src/mainboard/bachmann/ot200/mainboard.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
-};
diff --git a/src/mainboard/bachmann/ot200/ramstage.c b/src/mainboard/bachmann/ot200/ramstage.c
new file mode 100644
index 0000000..76b3c53
--- /dev/null
+++ b/src/mainboard/bachmann/ot200/ramstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Bachmann electronic GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+};
diff --git a/src/mainboard/bcom/winnet100/mainboard.c b/src/mainboard/bcom/winnet100/mainboard.c
deleted file mode 100644
index 13089df..0000000
--- a/src/mainboard/bcom/winnet100/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("BCOM WinNET100 Mainboard")
-};
diff --git a/src/mainboard/bcom/winnet100/ramstage.c b/src/mainboard/bcom/winnet100/ramstage.c
new file mode 100644
index 0000000..13089df
--- /dev/null
+++ b/src/mainboard/bcom/winnet100/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Juergen Beisert <juergen at kreuzholzen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("BCOM WinNET100 Mainboard")
+};
diff --git a/src/mainboard/bcom/winnetp680/mainboard.c b/src/mainboard/bcom/winnetp680/mainboard.c
deleted file mode 100644
index 26fc5e3..0000000
--- a/src/mainboard/bcom/winnetp680/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("BCOM WinNET P680 Mainboard")
-};
diff --git a/src/mainboard/bcom/winnetp680/ramstage.c b/src/mainboard/bcom/winnetp680/ramstage.c
new file mode 100644
index 0000000..26fc5e3
--- /dev/null
+++ b/src/mainboard/bcom/winnetp680/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("BCOM WinNET P680 Mainboard")
+};
diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c
deleted file mode 100644
index f3387a3..0000000
--- a/src/mainboard/bifferos/bifferboard/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Bifferos Bifferboard")
-};
-
diff --git a/src/mainboard/bifferos/bifferboard/ramstage.c b/src/mainboard/bifferos/bifferboard/ramstage.c
new file mode 100644
index 0000000..f3387a3
--- /dev/null
+++ b/src/mainboard/bifferos/bifferboard/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Bifferos Bifferboard")
+};
+
diff --git a/src/mainboard/biostar/m6tba/mainboard.c b/src/mainboard/biostar/m6tba/mainboard.c
deleted file mode 100644
index 6795284..0000000
--- a/src/mainboard/biostar/m6tba/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Biostar M6TBA Mainboard")
-};
diff --git a/src/mainboard/biostar/m6tba/ramstage.c b/src/mainboard/biostar/m6tba/ramstage.c
new file mode 100644
index 0000000..6795284
--- /dev/null
+++ b/src/mainboard/biostar/m6tba/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Biostar M6TBA Mainboard")
+};
diff --git a/src/mainboard/broadcom/blast/mainboard.c b/src/mainboard/broadcom/blast/mainboard.c
deleted file mode 100644
index c556bd5..0000000
--- a/src/mainboard/broadcom/blast/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Broadcom Blast Mainboard")
-};
-
diff --git a/src/mainboard/broadcom/blast/ramstage.c b/src/mainboard/broadcom/blast/ramstage.c
new file mode 100644
index 0000000..c556bd5
--- /dev/null
+++ b/src/mainboard/broadcom/blast/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Broadcom Blast Mainboard")
+};
+
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c b/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c
deleted file mode 100644
index d4abb63..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Compaq Deskpro EN SFF P600 Mainboard")
-};
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/ramstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/ramstage.c
new file mode 100644
index 0000000..d4abb63
--- /dev/null
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Compaq Deskpro EN SFF P600 Mainboard")
+};
diff --git a/src/mainboard/digitallogic/adl855pc/mainboard.c b/src/mainboard/digitallogic/adl855pc/mainboard.c
deleted file mode 100644
index 41c34e4..0000000
--- a/src/mainboard/digitallogic/adl855pc/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("DIGITAL-LOGIC ADL855PC Mainboard")
-};
-
diff --git a/src/mainboard/digitallogic/adl855pc/ramstage.c b/src/mainboard/digitallogic/adl855pc/ramstage.c
new file mode 100644
index 0000000..41c34e4
--- /dev/null
+++ b/src/mainboard/digitallogic/adl855pc/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("DIGITAL-LOGIC ADL855PC Mainboard")
+};
+
diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c
deleted file mode 100644
index 8f2d8c6..0000000
--- a/src/mainboard/digitallogic/msm586seg/mainboard.c
+++ /dev/null
@@ -1,135 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <cpu/amd/sc520.h>
-
-
-static void irqdump(void)
-{
- volatile unsigned char *irq;
- void *mmcr;
- int i;
- int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
- 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
- 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
- 0xd30, 0xd31, 0xd32, 0xd33,
- 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
- 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
- -1};
- mmcr = (void *) 0xfffef000;
-
- printk(BIOS_ERR, "mmcr is %p\n", mmcr);
- for(i = 0; irqlist[i] >= 0; i++) {
- irq = mmcr + irqlist[i];
- printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
- }
-
-}
-
-/* TODO: finish up mmcr struct in sc520.h, and;
- - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
-*/
-static void enable_dev(struct device *dev)
-{
- //volatile struct mmcrpic *pic = MMCRPIC;
- volatile struct mmcr *mmcr = MMCRDEFAULT;
-
- /* msm586seg has this register set to a weird value.
- * follow the board, not the manual!
- */
-
- /* currently, nothing in the device to use, so ignore it. */
- printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
-
-
- /* from fuctory bios */
- /* NOTE: the following interrupt settings made interrupts work
- * for hard drive, and serial, but not for ethernet
- */
- /* just do what they say and nobody gets hurt. */
- mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
- /* all ints to level */
- mmcr->pic.mpicmode = 0;
- mmcr->pic.sl1picmode = 0;
- mmcr->pic.sl2picmode = 0x80;
-
- mmcr->pic.intpinpol = 0;
-
- mmcr->pic.pit0map = 1;
- mmcr->pic.uart1map = 0xc;
- mmcr->pic.uart2map = 0xb;
- mmcr->pic.rtcmap = 3;
- mmcr->pic.ferrmap = 8;
- mmcr->pic.gp0imap = 6;
- mmcr->pic.gp1imap = 2;
- mmcr->pic.gp2imap = 7;
- mmcr->pic.gp6imap = 0x15;
- mmcr->pic.gp7imap = 0x16;
- mmcr->pic.gp10imap = 0x9;
- mmcr->pic.gp9imap = 0x4;
-
- irqdump();
- printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
-
- printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
- printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
-
- /* The following block has NOT proven sufficient to get
- * the VGA hardware to talk to us
- */
- /* let's set some mmcr stuff per the BIOS settings */
- mmcr->dbctl.dbctl = 0x10;
- mmcr->sysarb.ctl = 6;
- mmcr->sysarb.menb = 0xf;
- mmcr->sysarb.prictl = 0xc0000f0f;
- /* this is bios setting, depends on sysarb above */
- mmcr->hostbridge.ctl = 0x108;
- printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
-
- /* pio */
- mmcr->pio.data31_16 = 0xffbf;
-
- /* pci stuff */
- mmcr->pic.pciintamap = 0xa;
-
- /* END block where vga hardware still will not talk to us */
- /* all we get from VGA I/O addresses are ffff etc.
- */
- mmcr->sysmap.adddecctl = 0x10;
-
- /* VGA now talks to us, so this adddecctl was the trick.
- * still no interrupts from enet.
- * Let's try fixing the piodata stuff, as there may be
- * some wire there not documented.
- */
- mmcr->pio.data31_16 = 0xffbf;
- /* also, our sl?picmode needs to match fuctory bios */
- mmcr->pic.sl1picmode = 0x80;
- mmcr->pic.sl2picmode = 0x0;
- /* and, finally, they do set gp5imap and we don't.
- */
- mmcr->pic.gp5imap = 0xd;
- /* remaining problem: almost certainly, the irq table is bogus
- * NO SHOCK as it came from fuctory bios.
- * but let's try these 4 changes for now and see what shakes.
- */
- /* still not interrupts. */
- /* their IRQ table is wrong. Just hardwire it */
- {
- unsigned char pciints[4] = {15, 15, 15, 15};
- pci_assign_irqs(0, 12, pciints);
- }
- /* the assigned failed but we just noticed -- there is no
- * dma mapping, and selftest on e100 requires that dma work
- */
- /* follow fuctory here */
- mmcr->dmacontrol.extchanmapa = 0x3210;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
- .enable_dev = enable_dev
-};
-
diff --git a/src/mainboard/digitallogic/msm586seg/ramstage.c b/src/mainboard/digitallogic/msm586seg/ramstage.c
new file mode 100644
index 0000000..8f2d8c6
--- /dev/null
+++ b/src/mainboard/digitallogic/msm586seg/ramstage.c
@@ -0,0 +1,135 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/amd/sc520.h>
+
+
+static void irqdump(void)
+{
+ volatile unsigned char *irq;
+ void *mmcr;
+ int i;
+ int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
+ 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
+ 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
+ 0xd30, 0xd31, 0xd32, 0xd33,
+ 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
+ 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
+ -1};
+ mmcr = (void *) 0xfffef000;
+
+ printk(BIOS_ERR, "mmcr is %p\n", mmcr);
+ for(i = 0; irqlist[i] >= 0; i++) {
+ irq = mmcr + irqlist[i];
+ printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
+ }
+
+}
+
+/* TODO: finish up mmcr struct in sc520.h, and;
+ - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
+*/
+static void enable_dev(struct device *dev)
+{
+ //volatile struct mmcrpic *pic = MMCRPIC;
+ volatile struct mmcr *mmcr = MMCRDEFAULT;
+
+ /* msm586seg has this register set to a weird value.
+ * follow the board, not the manual!
+ */
+
+ /* currently, nothing in the device to use, so ignore it. */
+ printk(BIOS_ERR, "digital logic msm586 seg ENTER %s\n", __func__);
+
+
+ /* from fuctory bios */
+ /* NOTE: the following interrupt settings made interrupts work
+ * for hard drive, and serial, but not for ethernet
+ */
+ /* just do what they say and nobody gets hurt. */
+ mmcr->pic.pcicr = 0 ; // M_GINT_MODE | M_S1_MODE | M_S2_MODE;
+ /* all ints to level */
+ mmcr->pic.mpicmode = 0;
+ mmcr->pic.sl1picmode = 0;
+ mmcr->pic.sl2picmode = 0x80;
+
+ mmcr->pic.intpinpol = 0;
+
+ mmcr->pic.pit0map = 1;
+ mmcr->pic.uart1map = 0xc;
+ mmcr->pic.uart2map = 0xb;
+ mmcr->pic.rtcmap = 3;
+ mmcr->pic.ferrmap = 8;
+ mmcr->pic.gp0imap = 6;
+ mmcr->pic.gp1imap = 2;
+ mmcr->pic.gp2imap = 7;
+ mmcr->pic.gp6imap = 0x15;
+ mmcr->pic.gp7imap = 0x16;
+ mmcr->pic.gp10imap = 0x9;
+ mmcr->pic.gp9imap = 0x4;
+
+ irqdump();
+ printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
+
+ printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20);
+ printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
+
+ /* The following block has NOT proven sufficient to get
+ * the VGA hardware to talk to us
+ */
+ /* let's set some mmcr stuff per the BIOS settings */
+ mmcr->dbctl.dbctl = 0x10;
+ mmcr->sysarb.ctl = 6;
+ mmcr->sysarb.menb = 0xf;
+ mmcr->sysarb.prictl = 0xc0000f0f;
+ /* this is bios setting, depends on sysarb above */
+ mmcr->hostbridge.ctl = 0x108;
+ printk(BIOS_ERR, "digital logic msm586 seg EXIT %s\n", __func__);
+
+ /* pio */
+ mmcr->pio.data31_16 = 0xffbf;
+
+ /* pci stuff */
+ mmcr->pic.pciintamap = 0xa;
+
+ /* END block where vga hardware still will not talk to us */
+ /* all we get from VGA I/O addresses are ffff etc.
+ */
+ mmcr->sysmap.adddecctl = 0x10;
+
+ /* VGA now talks to us, so this adddecctl was the trick.
+ * still no interrupts from enet.
+ * Let's try fixing the piodata stuff, as there may be
+ * some wire there not documented.
+ */
+ mmcr->pio.data31_16 = 0xffbf;
+ /* also, our sl?picmode needs to match fuctory bios */
+ mmcr->pic.sl1picmode = 0x80;
+ mmcr->pic.sl2picmode = 0x0;
+ /* and, finally, they do set gp5imap and we don't.
+ */
+ mmcr->pic.gp5imap = 0xd;
+ /* remaining problem: almost certainly, the irq table is bogus
+ * NO SHOCK as it came from fuctory bios.
+ * but let's try these 4 changes for now and see what shakes.
+ */
+ /* still not interrupts. */
+ /* their IRQ table is wrong. Just hardwire it */
+ {
+ unsigned char pciints[4] = {15, 15, 15, 15};
+ pci_assign_irqs(0, 12, pciints);
+ }
+ /* the assigned failed but we just noticed -- there is no
+ * dma mapping, and selftest on e100 requires that dma work
+ */
+ /* follow fuctory here */
+ mmcr->dmacontrol.extchanmapa = 0x3210;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard")
+ .enable_dev = enable_dev
+};
+
diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c
index a293842..499a710 100644
--- a/src/mainboard/digitallogic/msm586seg/romstage.c
+++ b/src/mainboard/digitallogic/msm586seg/romstage.c
@@ -16,7 +16,7 @@ void setup_pars(void)
/* set up the PAR registers as they are on the MSM586SEG */
par = (unsigned long *) 0xfffef088;
- /* NOTE: move this to mainboard.c ASAP */
+ /* NOTE: move this to ramstage.c ASAP */
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c
deleted file mode 100644
index 3ade3d6..0000000
--- a/src/mainboard/digitallogic/msm800sev/mainboard.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("DIGITAL-LOGIC MSM800SEV Mainboard")
- .enable_dev = enable_dev,
-};
-
diff --git a/src/mainboard/digitallogic/msm800sev/ramstage.c b/src/mainboard/digitallogic/msm800sev/ramstage.c
new file mode 100644
index 0000000..3ade3d6
--- /dev/null
+++ b/src/mainboard/digitallogic/msm800sev/ramstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "MSM800SEV ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "MSM800SEV EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("DIGITAL-LOGIC MSM800SEV Mainboard")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/mainboard/eaglelion/5bcm/mainboard.c b/src/mainboard/eaglelion/5bcm/mainboard.c
deleted file mode 100644
index e1c499e..0000000
--- a/src/mainboard/eaglelion/5bcm/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Eaglelion 5BCM Mainboard")
-};
-
diff --git a/src/mainboard/eaglelion/5bcm/ramstage.c b/src/mainboard/eaglelion/5bcm/ramstage.c
new file mode 100644
index 0000000..e1c499e
--- /dev/null
+++ b/src/mainboard/eaglelion/5bcm/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Eaglelion 5BCM Mainboard")
+};
+
diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c
deleted file mode 100644
index 667ac5e..0000000
--- a/src/mainboard/ecs/p6iwp-fe/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Anders Jenbo <anders at jenbo.dk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("ECS P6IWP-Fe Mainboard")
-};
diff --git a/src/mainboard/ecs/p6iwp-fe/ramstage.c b/src/mainboard/ecs/p6iwp-fe/ramstage.c
new file mode 100644
index 0000000..667ac5e
--- /dev/null
+++ b/src/mainboard/ecs/p6iwp-fe/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders at jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ECS P6IWP-Fe Mainboard")
+};
diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c
deleted file mode 100644
index f8d0da7..0000000
--- a/src/mainboard/emulation/qemu-x86/mainboard.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/keyboard.h>
-#include <arch/io.h>
-
-/* not sure how these are routed in qemu */
-static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 };
-
-static void qemu_nb_init(device_t dev)
-{
- /* Map memory at 0xc0000 - 0xfffff */
- int i;
- uint8_t v = pci_read_config8(dev, 0x59);
- v |= 0x30;
- pci_write_config8(dev, 0x59, v);
- for (i=0; i<6; i++)
- pci_write_config8(dev, 0x5a + i, 0x33);
-
- /* This sneaked in here, because Qemu does not
- * emulate a SuperIO chip
- */
- pc_keyboard_init(0);
-
- /* The PIRQ table is not working well for interrupt routing purposes.
- * so we'll just set the IRQ directly.
- */
- printk(BIOS_INFO, "setting ethernet\n");
- pci_assign_irqs(0, 3, enetIrqs);
-}
-
-static struct device_operations nb_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = qemu_nb_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver nb_driver __pci_driver = {
- .ops = &nb_operations,
- .vendor = 0x8086,
- .device = 0x1237,
-};
-
-static void qemu_init(device_t dev)
-{
- /* The VGA OPROM already lives at 0xc0000,
- * force coreboot to use it.
- */
- dev->on_mainboard = 1;
-
- /* Now do the usual initialization */
- pci_dev_init(dev);
-}
-
-static struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = qemu_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = 0x1013,
- .device = 0x00b8,
-};
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("QEMU Mainboard")
-};
-
diff --git a/src/mainboard/emulation/qemu-x86/ramstage.c b/src/mainboard/emulation/qemu-x86/ramstage.c
new file mode 100644
index 0000000..f8d0da7
--- /dev/null
+++ b/src/mainboard/emulation/qemu-x86/ramstage.c
@@ -0,0 +1,76 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+
+/* not sure how these are routed in qemu */
+static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 };
+
+static void qemu_nb_init(device_t dev)
+{
+ /* Map memory at 0xc0000 - 0xfffff */
+ int i;
+ uint8_t v = pci_read_config8(dev, 0x59);
+ v |= 0x30;
+ pci_write_config8(dev, 0x59, v);
+ for (i=0; i<6; i++)
+ pci_write_config8(dev, 0x5a + i, 0x33);
+
+ /* This sneaked in here, because Qemu does not
+ * emulate a SuperIO chip
+ */
+ pc_keyboard_init(0);
+
+ /* The PIRQ table is not working well for interrupt routing purposes.
+ * so we'll just set the IRQ directly.
+ */
+ printk(BIOS_INFO, "setting ethernet\n");
+ pci_assign_irqs(0, 3, enetIrqs);
+}
+
+static struct device_operations nb_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = qemu_nb_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver nb_driver __pci_driver = {
+ .ops = &nb_operations,
+ .vendor = 0x8086,
+ .device = 0x1237,
+};
+
+static void qemu_init(device_t dev)
+{
+ /* The VGA OPROM already lives at 0xc0000,
+ * force coreboot to use it.
+ */
+ dev->on_mainboard = 1;
+
+ /* Now do the usual initialization */
+ pci_dev_init(dev);
+}
+
+static struct device_operations vga_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = qemu_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver vga_driver __pci_driver = {
+ .ops = &vga_operations,
+ .vendor = 0x1013,
+ .device = 0x00b8,
+};
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("QEMU Mainboard")
+};
+
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
deleted file mode 100644
index 83b4718..0000000
--- a/src/mainboard/getac/p470/mainboard.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <delay.h>
-#include "hda_verb.h"
-
-#include "ec_oem.c"
-
-#define MAX_LCD_BRIGHTNESS 0xd8
-
-static void ec_enable(void)
-{
- u16 keymap;
- /* Enable Hotkey SCI */
-
- /* Fn key map; F1 = [0] ... F12 = [11] */
- keymap = 0x5f1;
- send_ec_oem_command(0x45);
- send_ec_oem_data(0x09); // SCI
- // send_ec_oem_data(0x08); // SMI#
- send_ec_oem_data(keymap >> 8);
- send_ec_oem_data(keymap & 0xff);
-
- /* Enable Backlight */
- ec_write(0x17, MAX_LCD_BRIGHTNESS);
-
- /* Notify EC system is in ACPI mode */
- send_ec_oem_command(0x5e);
- send_ec_oem_data(0xea);
- send_ec_oem_data(0x0c);
- send_ec_oem_data(0x01);
-}
-
-static void pcie_limit_power(void)
-{
-#if 0
- // This piece of code needs further debugging as it crashes the
- // machine. It should set the slot numbers and enable power
- // limitation for the PCIe slots.
-
- device_t dev;
-
- dev = dev_find_slot(0, PCI_DEVFN(28,0));
- if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
-
- dev = dev_find_slot(0, PCI_DEVFN(28,1));
- if (dev) pci_write_config32(dev, 0x54, 0x0018a0e0);
-
- dev = dev_find_slot(0, PCI_DEVFN(28,2));
- if (dev) pci_write_config32(dev, 0x54, 0x0020a0e0);
-
- dev = dev_find_slot(0, PCI_DEVFN(28,3));
- if (dev) pci_write_config32(dev, 0x54, 0x0028a0e0);
-#endif
-}
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_init(device_t dev)
-{
- ec_enable();
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses(). Is there no mainboard_init()?
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- pcie_limit_power();
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Getac P470 Rugged Notebook")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/getac/p470/ramstage.c b/src/mainboard/getac/p470/ramstage.c
new file mode 100644
index 0000000..83b4718
--- /dev/null
+++ b/src/mainboard/getac/p470/ramstage.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include "hda_verb.h"
+
+#include "ec_oem.c"
+
+#define MAX_LCD_BRIGHTNESS 0xd8
+
+static void ec_enable(void)
+{
+ u16 keymap;
+ /* Enable Hotkey SCI */
+
+ /* Fn key map; F1 = [0] ... F12 = [11] */
+ keymap = 0x5f1;
+ send_ec_oem_command(0x45);
+ send_ec_oem_data(0x09); // SCI
+ // send_ec_oem_data(0x08); // SMI#
+ send_ec_oem_data(keymap >> 8);
+ send_ec_oem_data(keymap & 0xff);
+
+ /* Enable Backlight */
+ ec_write(0x17, MAX_LCD_BRIGHTNESS);
+
+ /* Notify EC system is in ACPI mode */
+ send_ec_oem_command(0x5e);
+ send_ec_oem_data(0xea);
+ send_ec_oem_data(0x0c);
+ send_ec_oem_data(0x01);
+}
+
+static void pcie_limit_power(void)
+{
+#if 0
+ // This piece of code needs further debugging as it crashes the
+ // machine. It should set the slot numbers and enable power
+ // limitation for the PCIe slots.
+
+ device_t dev;
+
+ dev = dev_find_slot(0, PCI_DEVFN(28,0));
+ if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
+
+ dev = dev_find_slot(0, PCI_DEVFN(28,1));
+ if (dev) pci_write_config32(dev, 0x54, 0x0018a0e0);
+
+ dev = dev_find_slot(0, PCI_DEVFN(28,2));
+ if (dev) pci_write_config32(dev, 0x54, 0x0020a0e0);
+
+ dev = dev_find_slot(0, PCI_DEVFN(28,3));
+ if (dev) pci_write_config32(dev, 0x54, 0x0028a0e0);
+#endif
+}
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_init(device_t dev)
+{
+ ec_enable();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses(). Is there no mainboard_init()?
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ pcie_limit_power();
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Getac P470 Rugged Notebook")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/gigabyte/ga-6bxc/mainboard.c b/src/mainboard/gigabyte/ga-6bxc/mainboard.c
deleted file mode 100644
index d43a577..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE GA-6BXC Mainboard")
-};
diff --git a/src/mainboard/gigabyte/ga-6bxc/ramstage.c b/src/mainboard/gigabyte/ga-6bxc/ramstage.c
new file mode 100644
index 0000000..d43a577
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxc/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE GA-6BXC Mainboard")
+};
diff --git a/src/mainboard/gigabyte/ga-6bxe/mainboard.c b/src/mainboard/gigabyte/ga-6bxe/mainboard.c
deleted file mode 100644
index 281d841..0000000
--- a/src/mainboard/gigabyte/ga-6bxe/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Anders Jenbo <anders at jenbo.dk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE GA-6BXE Mainboard")
-};
diff --git a/src/mainboard/gigabyte/ga-6bxe/ramstage.c b/src/mainboard/gigabyte/ga-6bxe/ramstage.c
new file mode 100644
index 0000000..281d841
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-6bxe/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Anders Jenbo <anders at jenbo.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE GA-6BXE Mainboard")
+};
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
deleted file mode 100644
index e8b8969..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
-};
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ramstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ramstage.c
new file mode 100644
index 0000000..e8b8969
--- /dev/null
+++ b/src/mainboard/gigabyte/ga_2761gxdk/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
+ * Written by Morgan Tsai <my_tsai at sis.com> for SiS.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
+};
diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c
deleted file mode 100644
index dffa769..0000000
--- a/src/mainboard/gigabyte/m57sli/mainboard.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-// #include "hda_verb.h"
-
-static void verb_setup(void)
-{
- /* TODO: Add a correct hda_verb.h file for this board. */
- // cim_verb_data = mainboard_cim_verb_data;
- // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE GA-M57SLI Mainboard")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/gigabyte/m57sli/ramstage.c b/src/mainboard/gigabyte/m57sli/ramstage.c
new file mode 100644
index 0000000..dffa769
--- /dev/null
+++ b/src/mainboard/gigabyte/m57sli/ramstage.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+// #include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ /* TODO: Add a correct hda_verb.h file for this board. */
+ // cim_verb_data = mainboard_cim_verb_data;
+ // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE GA-M57SLI Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
deleted file mode 100644
index c65fbb6..0000000
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Alec Ari <neotheuser at ymail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-int is_dev3_present(void);
-
-void set_pcie_dereset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 1 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte |= ((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 1 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word |= (1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 0 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte &= ~((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 0 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * dev3 does not exist on ma785gm
- */
-int is_dev3_present(void)
-{
- return 0;
-}
-
-/*
- * set gpio40 gfx
- */
-static void set_gpio40_gfx(void)
-{
- u8 byte;
-// u16 word;
- u32 dword;
- device_t sm_dev;
- /* disable the GPIO40 as CLKREQ2# function */
- byte = pm_ioread(0xd3);
- byte &= ~(1 << 7);
- pm_iowrite(0xd3, byte);
-
- /* disable the GPIO40 as CLKREQ3# function */
- byte = pm_ioread(0xd4);
- byte &= ~(1 << 0);
- pm_iowrite(0xd4, byte);
-
- /* enable pull up for GPIO68 */
- byte = pm2_ioread(0xf1);
- byte &= ~(1 << 4);
- pm2_iowrite(0xf1, byte);
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* set the gfx to 1x16 lanes */
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
-}
-
-/*************************************************
-* enable the dedicated function in ma785gm board.
-* This function called early than rs780_enable.
-*************************************************/
-static void ma785gm_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
- set_gpio40_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE MA785GM-US2H Mainboard")
- .enable_dev = ma785gm_enable,
-};
diff --git a/src/mainboard/gigabyte/ma785gm/ramstage.c b/src/mainboard/gigabyte/ma785gm/ramstage.c
new file mode 100644
index 0000000..c65fbb6
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/ramstage.c
@@ -0,0 +1,155 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+int is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 1 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte |= ((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 1 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= (1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 0 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte &= ~((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 0 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word &= ~(1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * dev3 does not exist on ma785gm
+ */
+int is_dev3_present(void)
+{
+ return 0;
+}
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+ u8 byte;
+// u16 word;
+ u32 dword;
+ device_t sm_dev;
+ /* disable the GPIO40 as CLKREQ2# function */
+ byte = pm_ioread(0xd3);
+ byte &= ~(1 << 7);
+ pm_iowrite(0xd3, byte);
+
+ /* disable the GPIO40 as CLKREQ3# function */
+ byte = pm_ioread(0xd4);
+ byte &= ~(1 << 0);
+ pm_iowrite(0xd4, byte);
+
+ /* enable pull up for GPIO68 */
+ byte = pm2_ioread(0xf1);
+ byte &= ~(1 << 4);
+ pm2_iowrite(0xf1, byte);
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* set the gfx to 1x16 lanes */
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+}
+
+/*************************************************
+* enable the dedicated function in ma785gm board.
+* This function called early than rs780_enable.
+*************************************************/
+static void ma785gm_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+ set_gpio40_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE MA785GM-US2H Mainboard")
+ .enable_dev = ma785gm_enable,
+};
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
deleted file mode 100644
index 3c26c6a..0000000
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-int is_dev3_present(void);
-
-void set_pcie_dereset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 1 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte |= ((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 1 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word |= (1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset()
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
- /* set 0 to bit2 :disable GPM8 as AZ_RST output */
- byte = pm_ioread(0x8d);
- byte &= ~((1 << 1) | (1 << 2));
- pm_iowrite(0x8d, byte);
-
- /* set the GPM8 and GPM9 output enable and the value to 0 */
- byte = pm_ioread(0x94);
- byte &= ~((1 << 2) | (1 << 3));
- byte &= ~((1 << 0) | (1 << 1));
- pm_iowrite(0x94, byte);
-
- /* set the GPIO65 output enable and the value is 0 */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x7e);
- word &= ~(1 << 0);
- word &= ~(1 << 4);
- pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * justify the dev3 is exist or not
- */
-int is_dev3_present(void)
-{
- u16 word;
- device_t sm_dev;
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* put the GPIO68 output to tristate */
- word = pci_read_config16(sm_dev, 0x7e);
- word |= 1 << 6;
- pci_write_config16(sm_dev, 0x7e,word);
-
- /* read the GPIO68 input status */
- word = pci_read_config16(sm_dev, 0x7e);
-
- if(word & (1 << 10)){
- /*not exist*/
- return 0;
- }else{
- /*exist*/
- return 1;
- }
-}
-
-/*
- * set gpio40 gfx
- */
-static void set_gpio40_gfx(void)
-{
- u8 byte;
-// u16 word;
- u32 dword;
- device_t sm_dev;
- /* disable the GPIO40 as CLKREQ2# function */
- byte = pm_ioread(0xd3);
- byte &= ~(1 << 7);
- pm_iowrite(0xd3, byte);
-
- /* disable the GPIO40 as CLKREQ3# function */
- byte = pm_ioread(0xd4);
- byte &= ~(1 << 0);
- pm_iowrite(0xd4, byte);
-
- /* enable pull up for GPIO68 */
- byte = pm2_ioread(0xf1);
- byte &= ~(1 << 4);
- pm2_iowrite(0xf1, byte);
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /*if the dev3 is present, set the gfx to 2x8 lanes*/
- /*otherwise set the gfx to 1x16 lanes*/
- if(is_dev3_present()){
-
- printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword |= (1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
-
- }else{
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
- }
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb700 settings for thermal config */
- /* set SB700 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in ma785gmt board.
-* This function called early than rs780_enable.
-*************************************************/
-static void ma785gmt_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
- set_thermal_config();
- set_gpio40_gfx();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard")
- .enable_dev = ma785gmt_enable,
-};
diff --git a/src/mainboard/gigabyte/ma785gmt/ramstage.c b/src/mainboard/gigabyte/ma785gmt/ramstage.c
new file mode 100644
index 0000000..3c26c6a
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gmt/ramstage.c
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+int is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 1 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte |= ((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 1 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= (1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+ /* set 0 to bit2 :disable GPM8 as AZ_RST output */
+ byte = pm_ioread(0x8d);
+ byte &= ~((1 << 1) | (1 << 2));
+ pm_iowrite(0x8d, byte);
+
+ /* set the GPM8 and GPM9 output enable and the value to 0 */
+ byte = pm_ioread(0x94);
+ byte &= ~((1 << 2) | (1 << 3));
+ byte &= ~((1 << 0) | (1 << 1));
+ pm_iowrite(0x94, byte);
+
+ /* set the GPIO65 output enable and the value is 0 */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x7e);
+ word &= ~(1 << 0);
+ word &= ~(1 << 4);
+ pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * justify the dev3 is exist or not
+ */
+int is_dev3_present(void)
+{
+ u16 word;
+ device_t sm_dev;
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* put the GPIO68 output to tristate */
+ word = pci_read_config16(sm_dev, 0x7e);
+ word |= 1 << 6;
+ pci_write_config16(sm_dev, 0x7e,word);
+
+ /* read the GPIO68 input status */
+ word = pci_read_config16(sm_dev, 0x7e);
+
+ if(word & (1 << 10)){
+ /*not exist*/
+ return 0;
+ }else{
+ /*exist*/
+ return 1;
+ }
+}
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+ u8 byte;
+// u16 word;
+ u32 dword;
+ device_t sm_dev;
+ /* disable the GPIO40 as CLKREQ2# function */
+ byte = pm_ioread(0xd3);
+ byte &= ~(1 << 7);
+ pm_iowrite(0xd3, byte);
+
+ /* disable the GPIO40 as CLKREQ3# function */
+ byte = pm_ioread(0xd4);
+ byte &= ~(1 << 0);
+ pm_iowrite(0xd4, byte);
+
+ /* enable pull up for GPIO68 */
+ byte = pm2_ioread(0xf1);
+ byte &= ~(1 << 4);
+ pm2_iowrite(0xf1, byte);
+
+ /* access the smbus extended register */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /*if the dev3 is present, set the gfx to 2x8 lanes*/
+ /*otherwise set the gfx to 1x16 lanes*/
+ if(is_dev3_present()){
+
+ printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword |= (1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+
+ }else{
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
+ }
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb700 settings for thermal config */
+ /* set SB700 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in ma785gmt board.
+* This function called early than rs780_enable.
+*************************************************/
+static void ma785gmt_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+ set_thermal_config();
+ set_gpio40_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard")
+ .enable_dev = ma785gmt_enable,
+};
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
deleted file mode 100644
index ba9baf4..0000000
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-/*
- * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-void set_pcie_reset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in board.
-* This function called early than rs780_enable.
-*************************************************/
-static void ma78gm_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("GIGABYTE MA78GM-US2H")
- .enable_dev = ma78gm_enable,
-};
diff --git a/src/mainboard/gigabyte/ma78gm/ramstage.c b/src/mainboard/gigabyte/ma78gm/ramstage.c
new file mode 100644
index 0000000..ba9baf4
--- /dev/null
+++ b/src/mainboard/gigabyte/ma78gm/ramstage.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+/*
+ * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in board.
+* This function called early than rs780_enable.
+*************************************************/
+static void ma78gm_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("GIGABYTE MA78GM-US2H")
+ .enable_dev = ma78gm_enable,
+};
diff --git a/src/mainboard/hp/dl145_g1/mainboard.c b/src/mainboard/hp/dl145_g1/mainboard.c
deleted file mode 100644
index fde9d22..0000000
--- a/src/mainboard/hp/dl145_g1/mainboard.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan
- * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
- * Copyright (C) 2007 Ward Vandewege <ward at gnu.org>
- * Copyright (C) 2010 FOI Oskar Enoksson <oskeno at foi.se>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("HP ProLiant DL145 G1 Mainboard")
-};
diff --git a/src/mainboard/hp/dl145_g1/ramstage.c b/src/mainboard/hp/dl145_g1/ramstage.c
new file mode 100644
index 0000000..fde9d22
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/ramstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
+ * Copyright (C) 2007 Ward Vandewege <ward at gnu.org>
+ * Copyright (C) 2010 FOI Oskar Enoksson <oskeno at foi.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP ProLiant DL145 G1 Mainboard")
+};
diff --git a/src/mainboard/hp/dl145_g3/mainboard.c b/src/mainboard/hp/dl145_g3/mainboard.c
deleted file mode 100644
index 81f074e..0000000
--- a/src/mainboard/hp/dl145_g3/mainboard.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler at rumms.uni-mannheim.de> for Uni of Mannheim.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for University of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("HP ProLiant DL145 G3 Mainboard")
-};
diff --git a/src/mainboard/hp/dl145_g3/ramstage.c b/src/mainboard/hp/dl145_g3/ramstage.c
new file mode 100644
index 0000000..81f074e
--- /dev/null
+++ b/src/mainboard/hp/dl145_g3/ramstage.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler at rumms.uni-mannheim.de> for Uni of Mannheim.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for University of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP ProLiant DL145 G3 Mainboard")
+};
diff --git a/src/mainboard/hp/dl165_g6_fam10/mainboard.c b/src/mainboard/hp/dl165_g6_fam10/mainboard.c
deleted file mode 100644
index 97f2fb7..0000000
--- a/src/mainboard/hp/dl165_g6_fam10/mainboard.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the LinuxBIOS project.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler at rumms.uni-mannheim.de> for Uni of Mannheim.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for University of Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)")
-};
diff --git a/src/mainboard/hp/dl165_g6_fam10/ramstage.c b/src/mainboard/hp/dl165_g6_fam10/ramstage.c
new file mode 100644
index 0000000..97f2fb7
--- /dev/null
+++ b/src/mainboard/hp/dl165_g6_fam10/ramstage.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler at rumms.uni-mannheim.de> for Uni of Mannheim.
+ *
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for University of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)")
+};
diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c
deleted file mode 100644
index 80e6f61..0000000
--- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("HP e-Vectra P2706T Mainboard")
-};
diff --git a/src/mainboard/hp/e_vectra_p2706t/ramstage.c b/src/mainboard/hp/e_vectra_p2706t/ramstage.c
new file mode 100644
index 0000000..80e6f61
--- /dev/null
+++ b/src/mainboard/hp/e_vectra_p2706t/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("HP e-Vectra P2706T Mainboard")
+};
diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c
deleted file mode 100644
index 4e3d606..0000000
--- a/src/mainboard/ibase/mb899/mainboard.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <device/device.h>
-#include <console/console.h>
-#include <boot/tables.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/io.h>
-#include <arch/coreboot_tables.h>
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f40: /* Boot Panel Type */
- // M.x86.R_AX = 0x015f; // Supported but failed
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = 3; // Display ID
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-
-static void int15_install(void)
-{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-}
-#endif
-
-/* Hardware Monitor */
-
-static u16 hwm_base = 0x290;
-
-static void hwm_write(u8 reg, u8 value)
-{
- outb(reg, hwm_base + 0x05);
- outb(value, hwm_base + 0x06);
-}
-
-static void hwm_bank(u8 bank)
-{
- hwm_write(0x4e, bank);
-}
-
-#define FAN_CRUISE_CONTROL_DISABLED 0
-#define FAN_CRUISE_CONTROL_SPEED 1
-#define FAN_CRUISE_CONTROL_THERMAL 2
-
-#define FAN_SPEED_5625 0
-//#define FAN_TEMPERATURE_30DEGC 0
-
-struct fan_speed {
- u8 fan_in;
- u16 fan_speed;
-};
-
-// FANIN Target Speed Register
-// FANIN = 337500 / RPM
-struct fan_speed fan_speeds[] = {
- { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
- { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
- { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
- { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
-};
-
-struct temperature {
- u8 deg_celsius;
- u8 deg_fahrenheit;
-};
-
-struct temperature temperatures[] = {
- { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
- { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
- { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
- { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
-};
-
-static void hwm_setup(void)
-{
- int cpufan_control = 0, sysfan_control = 0;
- int cpufan_speed = 0, sysfan_speed = 0;
- int cpufan_temperature = 0, sysfan_temperature = 0;
-
- if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
- cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
- if (get_option(&cpufan_speed, "cpufan_speed") < 0)
- cpufan_speed = FAN_SPEED_5625;
- //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
- // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
-
- if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
- sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
- if (get_option(&sysfan_speed, "sysfan_speed") < 0)
- sysfan_speed = FAN_SPEED_5625;
- //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
- // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
-
- // hwm_write(0x31, 0x20); // AVCC high limit
- // hwm_write(0x34, 0x06); // VIN2 low limit
-
- hwm_bank(0);
- hwm_write(0x59, 0x20); // Diode Selection
- hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
-
- hwm_bank(4);
- hwm_write(0x54, 0xf1); // SYSTIN temperature offset
- hwm_write(0x55, 0x19); // CPUTIN temperature offset
- hwm_write(0x56, 0xfc); // AUXTIN temperature offset
-
- hwm_bank(0x80); // Default
-
- u8 fan_config = 0;
- // 00 FANOUT is Manual Mode
- // 01 FANOUT is Thermal Cruise Mode
- // 10 FANOUT is Fan Speed Cruise Mode
- switch (cpufan_control) {
- case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
- case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
- }
- switch (sysfan_control) {
- case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
- case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
- }
- // This register must be written first
- hwm_write(0x04, fan_config);
-
- switch (cpufan_control) {
- case FAN_CRUISE_CONTROL_SPEED:
- printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
- fan_speeds[cpufan_speed].fan_speed);
- hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
- break;
- case FAN_CRUISE_CONTROL_THERMAL:
- printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
- temperatures[cpufan_temperature].deg_celsius,
- temperatures[cpufan_temperature].deg_fahrenheit);
- hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
- break;
- }
-
- switch (sysfan_control) {
- case FAN_CRUISE_CONTROL_SPEED:
- printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
- fan_speeds[sysfan_speed].fan_speed);
- hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
- break;
- case FAN_CRUISE_CONTROL_THERMAL:
- printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
- temperatures[sysfan_temperature].deg_celsius,
- temperatures[sysfan_temperature].deg_fahrenheit);
- hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
- break;
- }
-
- hwm_write(0x0e, 0x02); // Fan Output Step Down Time
- hwm_write(0x0f, 0x02); // Fan Output Step Up Time
-
- hwm_write(0x47, 0xaf); // FAN divisor register
- hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
-
- hwm_write(0x40, 0x01); // Init, but no SMI#
-}
-
-/* Audio Setup */
-
-extern u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
- // Default VERB is fine on this mainboard.
- cim_verb_data = NULL;
- cim_verb_data_size = 0;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
- verb_setup();
- hwm_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("iBASE MB899 Mainboard")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/ibase/mb899/ramstage.c b/src/mainboard/ibase/mb899/ramstage.c
new file mode 100644
index 0000000..4e3d606
--- /dev/null
+++ b/src/mainboard/ibase/mb899/ramstage.c
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <boot/tables.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/coreboot_tables.h>
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f35: /* Boot Display */
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = 3; // Display ID
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+
+static void int15_install(void)
+{
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+/* Hardware Monitor */
+
+static u16 hwm_base = 0x290;
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, hwm_base + 0x05);
+ outb(value, hwm_base + 0x06);
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x4e, bank);
+}
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+static void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") < 0)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") < 0)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
+
+/* Audio Setup */
+
+extern u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ // Default VERB is fine on this mainboard.
+ cim_verb_data = NULL;
+ cim_verb_data_size = 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+ hwm_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("iBASE MB899 Mainboard")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c
deleted file mode 100644
index 136ffaf..0000000
--- a/src/mainboard/ibm/e325/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IBM eServer 325 Mainboard")
-};
-
diff --git a/src/mainboard/ibm/e325/ramstage.c b/src/mainboard/ibm/e325/ramstage.c
new file mode 100644
index 0000000..136ffaf
--- /dev/null
+++ b/src/mainboard/ibm/e325/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IBM eServer 325 Mainboard")
+};
+
diff --git a/src/mainboard/ibm/e326/mainboard.c b/src/mainboard/ibm/e326/mainboard.c
deleted file mode 100644
index bd5ebc5..0000000
--- a/src/mainboard/ibm/e326/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IBM eServer 326 Mainboard")
-};
-
diff --git a/src/mainboard/ibm/e326/ramstage.c b/src/mainboard/ibm/e326/ramstage.c
new file mode 100644
index 0000000..bd5ebc5
--- /dev/null
+++ b/src/mainboard/ibm/e326/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IBM eServer 326 Mainboard")
+};
+
diff --git a/src/mainboard/iei/juki-511p/mainboard.c b/src/mainboard/iei/juki-511p/mainboard.c
deleted file mode 100644
index e5714cf..0000000
--- a/src/mainboard/iei/juki-511p/mainboard.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IEI JUKI-511P Mainboard")
-};
diff --git a/src/mainboard/iei/juki-511p/ramstage.c b/src/mainboard/iei/juki-511p/ramstage.c
new file mode 100644
index 0000000..e5714cf
--- /dev/null
+++ b/src/mainboard/iei/juki-511p/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IEI JUKI-511P Mainboard")
+};
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
deleted file mode 100644
index 44cbfcd..0000000
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-/* TODO - Need to find GPIO for PCIE slot.
- * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- /* PCIE slot not yet supported.*/
-}
-
-void set_pcie_reset()
-{
- /* PCIE slot not yet supported.*/
-}
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in kino board.
-* This function called early than rs780_enable.
-*************************************************/
-static void kino_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IEI Kino-780AM2 Mainboard")
- .enable_dev = kino_enable,
-};
diff --git a/src/mainboard/iei/kino-780am2-fam10/ramstage.c b/src/mainboard/iei/kino-780am2-fam10/ramstage.c
new file mode 100644
index 0000000..44cbfcd
--- /dev/null
+++ b/src/mainboard/iei/kino-780am2-fam10/ramstage.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+/* TODO - Need to find GPIO for PCIE slot.
+ * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ /* PCIE slot not yet supported.*/
+}
+
+void set_pcie_reset()
+{
+ /* PCIE slot not yet supported.*/
+}
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in kino board.
+* This function called early than rs780_enable.
+*************************************************/
+static void kino_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IEI Kino-780AM2 Mainboard")
+ .enable_dev = kino_enable,
+};
diff --git a/src/mainboard/iei/nova4899r/mainboard.c b/src/mainboard/iei/nova4899r/mainboard.c
deleted file mode 100644
index 85c6521..0000000
--- a/src/mainboard/iei/nova4899r/mainboard.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Luis Correia <luis.f.correia at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IEI NOVA-4899R Mainboard")
-};
diff --git a/src/mainboard/iei/nova4899r/ramstage.c b/src/mainboard/iei/nova4899r/ramstage.c
new file mode 100644
index 0000000..85c6521
--- /dev/null
+++ b/src/mainboard/iei/nova4899r/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Luis Correia <luis.f.correia at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IEI NOVA-4899R Mainboard")
+};
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/mainboard.c b/src/mainboard/iei/pcisa-lx-800-r10/mainboard.c
deleted file mode 100644
index 163e360..0000000
--- a/src/mainboard/iei/pcisa-lx-800-r10/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IEI PCISA-LX-800-R10 Mainboard")
-};
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/ramstage.c b/src/mainboard/iei/pcisa-lx-800-r10/ramstage.c
new file mode 100644
index 0000000..163e360
--- /dev/null
+++ b/src/mainboard/iei/pcisa-lx-800-r10/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IEI PCISA-LX-800-R10 Mainboard")
+};
diff --git a/src/mainboard/iei/pm-lx-800-r11/mainboard.c b/src/mainboard/iei/pm-lx-800-r11/mainboard.c
deleted file mode 100644
index b598cac..0000000
--- a/src/mainboard/iei/pm-lx-800-r11/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Ricardo Martins <rasmartins at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IEI PM-LX-800-R11 Mainboard")
-};
diff --git a/src/mainboard/iei/pm-lx-800-r11/ramstage.c b/src/mainboard/iei/pm-lx-800-r11/ramstage.c
new file mode 100644
index 0000000..b598cac
--- /dev/null
+++ b/src/mainboard/iei/pm-lx-800-r11/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Ricardo Martins <rasmartins at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IEI PM-LX-800-R11 Mainboard")
+};
diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c
deleted file mode 100644
index 8455377..0000000
--- a/src/mainboard/intel/d810e2cb/mainboard.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel D810E2CB Mainboard")
-};
diff --git a/src/mainboard/intel/d810e2cb/ramstage.c b/src/mainboard/intel/d810e2cb/ramstage.c
new file mode 100644
index 0000000..8455377
--- /dev/null
+++ b/src/mainboard/intel/d810e2cb/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel D810E2CB Mainboard")
+};
diff --git a/src/mainboard/intel/d945gclf/mainboard.c b/src/mainboard/intel/d945gclf/mainboard.c
deleted file mode 100644
index ca920bc..0000000
--- a/src/mainboard/intel/d945gclf/mainboard.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <console/console.h>
-#include <boot/tables.h>
-#include <arch/coreboot_tables.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel D945GCLF Mainboard")
-};
-
diff --git a/src/mainboard/intel/d945gclf/ramstage.c b/src/mainboard/intel/d945gclf/ramstage.c
new file mode 100644
index 0000000..ca920bc
--- /dev/null
+++ b/src/mainboard/intel/d945gclf/ramstage.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <console/console.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel D945GCLF Mainboard")
+};
+
diff --git a/src/mainboard/intel/eagleheights/mainboard.c b/src/mainboard/intel/eagleheights/mainboard.c
deleted file mode 100644
index d6bc10f..0000000
--- a/src/mainboard/intel/eagleheights/mainboard.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-
-#include <device/device.h>
-#include <boot/tables.h>
-#include <arch/coreboot_tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel Eagle Heights Mainboard")
-};
-
diff --git a/src/mainboard/intel/eagleheights/ramstage.c b/src/mainboard/intel/eagleheights/ramstage.c
new file mode 100644
index 0000000..d6bc10f
--- /dev/null
+++ b/src/mainboard/intel/eagleheights/ramstage.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Eagle Heights Mainboard")
+};
+
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
deleted file mode 100644
index 796f71e..0000000
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <arch/coreboot_tables.h>
-#include "hda_verb.h"
-#include <southbridge/intel/bd82x6x/pch.h>
-
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
- int res=-1;
-
- printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
- __func__, regs->eax & 0xffff);
-
- switch(regs->eax & 0xffff) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffffff00;
- regs->ecx |= 0x01;
- res = 0;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV (eDP) *
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2 (eDP) *
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0003;
- res = 0;
- break;
- case 0x5f70:
- switch ((regs->ecx >> 8) & 0xff) {
- case 0:
- /* Get Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 1:
- /* Set Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 2:
- /* Get SG/Non-SG mode */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
- ((regs->ecx >> 8) & 0xff));
- return 0;
- }
- break;
-
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- break;
- }
- return res;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0001;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV (eDP) *
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2 (eDP) *
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 3;
- break;
- case 0x5f70:
- /* Unknown */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
- M.x86.R_AX);
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static void int15_install(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-#endif
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-}
-#endif
-
-/* Audio Setup */
-
-extern const u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Compal Link ChromeBox")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/intel/emeraldlake2/ramstage.c b/src/mainboard/intel/emeraldlake2/ramstage.c
new file mode 100644
index 0000000..796f71e
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/ramstage.c
@@ -0,0 +1,249 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x01;
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0003;
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0001;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 3;
+ break;
+ case 0x5f70:
+ /* Unknown */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Compal Link ChromeBox")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/intel/jarrell/mainboard.c b/src/mainboard/intel/jarrell/mainboard.c
deleted file mode 100644
index f66431d..0000000
--- a/src/mainboard/intel/jarrell/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel Jarell Mainboard")
-};
-
diff --git a/src/mainboard/intel/jarrell/ramstage.c b/src/mainboard/intel/jarrell/ramstage.c
new file mode 100644
index 0000000..f66431d
--- /dev/null
+++ b/src/mainboard/intel/jarrell/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Jarell Mainboard")
+};
+
diff --git a/src/mainboard/intel/mtarvon/mainboard.c b/src/mainboard/intel/mtarvon/mainboard.c
deleted file mode 100644
index b69df9b..0000000
--- a/src/mainboard/intel/mtarvon/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel Mt. Arvon Mainboard")
-};
-
diff --git a/src/mainboard/intel/mtarvon/ramstage.c b/src/mainboard/intel/mtarvon/ramstage.c
new file mode 100644
index 0000000..b69df9b
--- /dev/null
+++ b/src/mainboard/intel/mtarvon/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Mt. Arvon Mainboard")
+};
+
diff --git a/src/mainboard/intel/truxton/mainboard.c b/src/mainboard/intel/truxton/mainboard.c
deleted file mode 100644
index 754ba0d..0000000
--- a/src/mainboard/intel/truxton/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel Truxton Mainboard")
-};
-
diff --git a/src/mainboard/intel/truxton/ramstage.c b/src/mainboard/intel/truxton/ramstage.c
new file mode 100644
index 0000000..754ba0d
--- /dev/null
+++ b/src/mainboard/intel/truxton/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Truxton Mainboard")
+};
+
diff --git a/src/mainboard/intel/xe7501devkit/mainboard.c b/src/mainboard/intel/xe7501devkit/mainboard.c
deleted file mode 100644
index c605624..0000000
--- a/src/mainboard/intel/xe7501devkit/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
-};
-
diff --git a/src/mainboard/intel/xe7501devkit/ramstage.c b/src/mainboard/intel/xe7501devkit/ramstage.c
new file mode 100644
index 0000000..c605624
--- /dev/null
+++ b/src/mainboard/intel/xe7501devkit/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
+};
+
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c
deleted file mode 100644
index f3fc20f..0000000
--- a/src/mainboard/iwave/iWRainbowG6/mainboard.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009-2010 iWave Systems
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <console/console.h>
-#include <boot/tables.h>
-#include "hda_verb.h"
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("iW Rainbow G6 Mainboard")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/iwave/iWRainbowG6/ramstage.c b/src/mainboard/iwave/iWRainbowG6/ramstage.c
new file mode 100644
index 0000000..f3fc20f
--- /dev/null
+++ b/src/mainboard/iwave/iWRainbowG6/ramstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009-2010 iWave Systems
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <console/console.h>
+#include <boot/tables.h>
+#include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("iW Rainbow G6 Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c
deleted file mode 100644
index 251852f..0000000
--- a/src/mainboard/iwill/dk8_htx/mainboard.c
+++ /dev/null
@@ -1,5 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IWILL DK8-HTX Mainboard")
-};
diff --git a/src/mainboard/iwill/dk8_htx/ramstage.c b/src/mainboard/iwill/dk8_htx/ramstage.c
new file mode 100644
index 0000000..251852f
--- /dev/null
+++ b/src/mainboard/iwill/dk8_htx/ramstage.c
@@ -0,0 +1,5 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IWILL DK8-HTX Mainboard")
+};
diff --git a/src/mainboard/iwill/dk8s2/mainboard.c b/src/mainboard/iwill/dk8s2/mainboard.c
deleted file mode 100644
index 18ab152..0000000
--- a/src/mainboard/iwill/dk8s2/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IWILL DK8S2 Mainboard")
-};
-
diff --git a/src/mainboard/iwill/dk8s2/ramstage.c b/src/mainboard/iwill/dk8s2/ramstage.c
new file mode 100644
index 0000000..18ab152
--- /dev/null
+++ b/src/mainboard/iwill/dk8s2/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IWILL DK8S2 Mainboard")
+};
+
diff --git a/src/mainboard/iwill/dk8x/mainboard.c b/src/mainboard/iwill/dk8x/mainboard.c
deleted file mode 100644
index 3e062de..0000000
--- a/src/mainboard/iwill/dk8x/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("IWILL DK8X Mainboard")
-};
-
diff --git a/src/mainboard/iwill/dk8x/ramstage.c b/src/mainboard/iwill/dk8x/ramstage.c
new file mode 100644
index 0000000..3e062de
--- /dev/null
+++ b/src/mainboard/iwill/dk8x/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("IWILL DK8X Mainboard")
+};
+
diff --git a/src/mainboard/jetway/j7f24/mainboard.c b/src/mainboard/jetway/j7f24/mainboard.c
deleted file mode 100644
index 4b1ee39..0000000
--- a/src/mainboard/jetway/j7f24/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Jetway J7F[24]* Mainboard")
-};
diff --git a/src/mainboard/jetway/j7f24/ramstage.c b/src/mainboard/jetway/j7f24/ramstage.c
new file mode 100644
index 0000000..4b1ee39
--- /dev/null
+++ b/src/mainboard/jetway/j7f24/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Jetway J7F[24]* Mainboard")
+};
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
deleted file mode 100644
index 3c4d872..0000000
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-/*
- * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
- * pull it up before training the slot.
- ***/
-void set_pcie_dereset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-void set_pcie_reset()
-{
- u16 word;
- device_t sm_dev;
- /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- word = pci_read_config16(sm_dev, 0xA8);
- word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
- word &= ~((1 << 8) | (1 << 10));
- pci_write_config16(sm_dev, 0xA8, word);
-}
-
-#if 0 /* not tested yet. */
-/********************************************************
-* board uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif /* get_ide_dma66() */
-
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*************************************************
-* enable the dedicated function in this board.
-* This function called early than rs780_enable.
-*************************************************/
-static void pa78vm5_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD PA78VM5 Mainboard")
- .enable_dev = pa78vm5_enable,
-};
diff --git a/src/mainboard/jetway/pa78vm5/ramstage.c b/src/mainboard/jetway/pa78vm5/ramstage.c
new file mode 100644
index 0000000..3c4d872
--- /dev/null
+++ b/src/mainboard/jetway/pa78vm5/ramstage.c
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+u8 is_dev3_present(void);
+
+/*
+ * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
+ * pull it up before training the slot.
+ ***/
+void set_pcie_dereset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+void set_pcie_reset()
+{
+ u16 word;
+ device_t sm_dev;
+ /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ word = pci_read_config16(sm_dev, 0xA8);
+ word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */
+ word &= ~((1 << 8) | (1 << 10));
+ pci_write_config16(sm_dev, 0xA8, word);
+}
+
+#if 0 /* not tested yet. */
+/********************************************************
+* board uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ /*u32 sm_dev, ide_dev; */
+ device_t sm_dev, ide_dev;
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+#endif /* get_ide_dma66() */
+
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*************************************************
+* enable the dedicated function in this board.
+* This function called early than rs780_enable.
+*************************************************/
+static void pa78vm5_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD PA78VM5 Mainboard")
+ .enable_dev = pa78vm5_enable,
+};
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
deleted file mode 100644
index b9686bd..0000000
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <device/device.h>
-#include <console/console.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = BOOT_DISPLAY_CRT;
- break;
- case 0x5f40: /* Boot Panel Type */
- // M.x86.R_AX = 0x015f; // Supported but failed
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = 3; // Display ID
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-
-static void int15_install(void)
-{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
- int res = -1;
-
- /* This int15 handler is Intel IGD. specific. Other chipsets need other
- * handlers. The right way to do this is to move this handler code into
- * the mainboard or northbridge code.
- * TODO: completely move to mainboards / chipsets.
- */
- switch (regs->eax & 0xffff) {
- /* And now Intel IGD code */
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
- case 0x5f35:
- regs->eax = 0x5f;
- regs->ecx = BOOT_DISPLAY_DEFAULT;
- res = 0;
- break;
- case 0x5f40:
- regs->eax = 0x5f;
- regs->ecx = 3; // This is mainboard specific
- printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
- res = 0;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- }
-
- return res;
-}
-
-static void int15_install(void)
-{
- mainboard_interrupt_handlers(0x15, &int15_handler);
-}
-#endif
-
-
-/* Hardware Monitor */
-
-static u16 hwm_base = 0xa00;
-
-static void hwm_write(u8 reg, u8 value)
-{
- outb(reg, hwm_base + 0x05);
- outb(value, hwm_base + 0x06);
-}
-
-static void hwm_bank(u8 bank)
-{
- hwm_write(0x4e, bank);
-}
-
-#define FAN_CRUISE_CONTROL_DISABLED 0
-#define FAN_CRUISE_CONTROL_SPEED 1
-#define FAN_CRUISE_CONTROL_THERMAL 2
-
-#define FAN_SPEED_5625 0
-//#define FAN_TEMPERATURE_30DEGC 0
-
-struct fan_speed {
- u8 fan_in;
- u16 fan_speed;
-};
-
-// FANIN Target Speed Register
-// FANIN = 337500 / RPM
-struct fan_speed fan_speeds[] = {
- { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
- { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
- { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
- { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
-};
-
-struct temperature {
- u8 deg_celsius;
- u8 deg_fahrenheit;
-};
-
-struct temperature temperatures[] = {
- { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
- { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
- { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
- { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
-};
-
-static void hwm_setup(void)
-{
- int cpufan_control = 0, sysfan_control = 0;
- int cpufan_speed = 0, sysfan_speed = 0;
- int cpufan_temperature = 0, sysfan_temperature = 0;
-
- if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
- cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
- if (get_option(&cpufan_speed, "cpufan_speed") < 0)
- cpufan_speed = FAN_SPEED_5625;
- //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
- // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
-
- if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
- sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
- if (get_option(&sysfan_speed, "sysfan_speed") < 0)
- sysfan_speed = FAN_SPEED_5625;
- //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
- // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
-
- // hwm_write(0x31, 0x20); // AVCC high limit
- // hwm_write(0x34, 0x06); // VIN2 low limit
-
- hwm_bank(0);
- hwm_write(0x59, 0x20); // Diode Selection
- hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
-
- hwm_bank(4);
- hwm_write(0x54, 0xf1); // SYSTIN temperature offset
- hwm_write(0x55, 0x19); // CPUTIN temperature offset
- hwm_write(0x56, 0xfc); // AUXTIN temperature offset
-
- hwm_bank(0x80); // Default
-
- u8 fan_config = 0;
- // 00 FANOUT is Manual Mode
- // 01 FANOUT is Thermal Cruise Mode
- // 10 FANOUT is Fan Speed Cruise Mode
- switch (cpufan_control) {
- case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
- case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
- }
- switch (sysfan_control) {
- case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
- case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
- }
- // This register must be written first
- hwm_write(0x04, fan_config);
-
- switch (cpufan_control) {
- case FAN_CRUISE_CONTROL_SPEED:
- printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
- fan_speeds[cpufan_speed].fan_speed);
- hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
- break;
- case FAN_CRUISE_CONTROL_THERMAL:
- printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
- temperatures[cpufan_temperature].deg_celsius,
- temperatures[cpufan_temperature].deg_fahrenheit);
- hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
- break;
- }
-
- switch (sysfan_control) {
- case FAN_CRUISE_CONTROL_SPEED:
- printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
- fan_speeds[sysfan_speed].fan_speed);
- hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
- break;
- case FAN_CRUISE_CONTROL_THERMAL:
- printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
- temperatures[sysfan_temperature].deg_celsius,
- temperatures[sysfan_temperature].deg_fahrenheit);
- hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
- break;
- }
-
- hwm_write(0x0e, 0x02); // Fan Output Step Down Time
- hwm_write(0x0f, 0x02); // Fan Output Step Up Time
-
- hwm_write(0x47, 0xaf); // FAN divisor register
- hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
-
- hwm_write(0x40, 0x01); // Init, but no SMI#
-}
-
-/* Audio Setup */
-
-extern u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
- // Default VERB is fine on this mainboard.
- cim_verb_data = NULL;
- cim_verb_data_size = 0;
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
- verb_setup();
- hwm_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Kontron 986LCD-M Mainboard")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/kontron/986lcd-m/ramstage.c b/src/mainboard/kontron/986lcd-m/ramstage.c
new file mode 100644
index 0000000..b9686bd
--- /dev/null
+++ b/src/mainboard/kontron/986lcd-m/ramstage.c
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f35: /* Boot Display */
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = BOOT_DISPLAY_CRT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = 3; // Display ID
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+
+static void int15_install(void)
+{
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res = -1;
+
+ /* This int15 handler is Intel IGD. specific. Other chipsets need other
+ * handlers. The right way to do this is to move this handler code into
+ * the mainboard or northbridge code.
+ * TODO: completely move to mainboards / chipsets.
+ */
+ switch (regs->eax & 0xffff) {
+ /* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+ case 0x5f35:
+ regs->eax = 0x5f;
+ regs->ecx = BOOT_DISPLAY_DEFAULT;
+ res = 0;
+ break;
+ case 0x5f40:
+ regs->eax = 0x5f;
+ regs->ecx = 3; // This is mainboard specific
+ printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+ res = 0;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ }
+
+ return res;
+}
+
+static void int15_install(void)
+{
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
+
+/* Hardware Monitor */
+
+static u16 hwm_base = 0xa00;
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, hwm_base + 0x05);
+ outb(value, hwm_base + 0x06);
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x4e, bank);
+}
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+static void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") < 0)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") < 0)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
+
+/* Audio Setup */
+
+extern u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ // Default VERB is fine on this mainboard.
+ cim_verb_data = NULL;
+ cim_verb_data_size = 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+ hwm_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Kontron 986LCD-M Mainboard")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
deleted file mode 100644
index 4eb638f..0000000
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/********************************************************
-* dbm690t uses a BCM5789 as on-board NIC.
-* It has a pin named LOW_POWER to enable it into LOW POWER state.
-* In order to run NIC, we should let it out of Low power state. This pin is
-* controlled by sb600 GPM3.
-* RRG4.2.3 GPM as GPIO
-* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
-* I/O C50, C51, C52, PM I/O94, 95, 96.
-* RRG4.2.3.1 GPM pins as Input
-* RRG4.2.3.2 GPM pins as Output
-********************************************************/
-static void enable_onboard_nic(void)
-{
- u8 byte;
-
- printk(BIOS_INFO, "%s.\n", __func__);
-
- /* set index register 0C50h to 13h (miscellaneous control) */
- outb(0x13, 0xC50); /* CMIndex */
-
- /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x40;
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-
- /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
- byte = inb(0xC51);
- byte &= 0x3F;
- byte |= 0x80; /* 7:6=10 */
- outb(byte, 0xC51);
-
- /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
- byte = inb(0xC52);
- byte &= ~0x8;
- outb(byte, 0xC52);
-}
-
-/********************************************************
-* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- printk(BIOS_INFO, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in dbm690t board.
-* This function called early than rs690_enable.
-*************************************************/
-static void kt690_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- get_ide_dma66();
- set_thermal_config();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Kontron KT690/mITX Mainboard")
- .enable_dev = kt690_enable,
-};
diff --git a/src/mainboard/kontron/kt690/ramstage.c b/src/mainboard/kontron/kt690/ramstage.c
new file mode 100644
index 0000000..4eb638f
--- /dev/null
+++ b/src/mainboard/kontron/kt690/ramstage.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb600/sb600.h>
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+ u8 val);
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+
+/********************************************************
+* dbm690t uses a BCM5789 as on-board NIC.
+* It has a pin named LOW_POWER to enable it into LOW POWER state.
+* In order to run NIC, we should let it out of Low power state. This pin is
+* controlled by sb600 GPM3.
+* RRG4.2.3 GPM as GPIO
+* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
+* I/O C50, C51, C52, PM I/O94, 95, 96.
+* RRG4.2.3.1 GPM pins as Input
+* RRG4.2.3.2 GPM pins as Output
+********************************************************/
+static void enable_onboard_nic(void)
+{
+ u8 byte;
+
+ printk(BIOS_INFO, "%s.\n", __func__);
+
+ /* set index register 0C50h to 13h (miscellaneous control) */
+ outb(0x13, 0xC50); /* CMIndex */
+
+ /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x40;
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+
+ /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
+ byte = inb(0xC51);
+ byte &= 0x3F;
+ byte |= 0x80; /* 7:6=10 */
+ outb(byte, 0xC51);
+
+ /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
+ byte = inb(0xC52);
+ byte &= ~0x8;
+ outb(byte, 0xC52);
+}
+
+/********************************************************
+* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void get_ide_dma66(void)
+{
+ u8 byte;
+ struct device *sm_dev;
+ struct device *ide_dev;
+
+ printk(BIOS_INFO, "%s.\n", __func__);
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+
+/*
+ * set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb600 settings for thermal config */
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in dbm690t board.
+* This function called early than rs690_enable.
+*************************************************/
+static void kt690_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
+
+ enable_onboard_nic();
+ get_ide_dma66();
+ set_thermal_config();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Kontron KT690/mITX Mainboard")
+ .enable_dev = kt690_enable,
+};
diff --git a/src/mainboard/lanner/em8510/mainboard.c b/src/mainboard/lanner/em8510/mainboard.c
deleted file mode 100644
index 9317944..0000000
--- a/src/mainboard/lanner/em8510/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Travelping GmbH <info at travelping.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("LANNER EM-8510 Mainboard")
-};
-
diff --git a/src/mainboard/lanner/em8510/ramstage.c b/src/mainboard/lanner/em8510/ramstage.c
new file mode 100644
index 0000000..9317944
--- /dev/null
+++ b/src/mainboard/lanner/em8510/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Travelping GmbH <info at travelping.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("LANNER EM-8510 Mainboard")
+};
+
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
deleted file mode 100644
index bd4c4a7..0000000
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <delay.h>
-#include <arch/coreboot_tables.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <ec/lenovo/pmh7/pmh7.h>
-#include <ec/acpi/ec.h>
-#include <ec/lenovo/h8/h8.h>
-#include <northbridge/intel/i945/i945.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/x86/include/arch/acpigen.h>
-
-static acpi_cstate_t cst_entries[] = {
- { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
- { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
- { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
-};
-
-int get_cst_entries(acpi_cstate_t **entries)
-{
- *entries = cst_entries;
- return ARRAY_SIZE(cst_entries);
-}
-
-static void mainboard_enable(device_t dev)
-{
- struct southbridge_intel_i82801gx_config *config;
- device_t dev0, idedev;
- u8 defaults_loaded = 0;
-
- /* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
- ec_write(0x0c, 0xc7);
-
- idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
-
- if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
- /* legacy I/O connected */
- pmh7_ultrabay_power_enable(1);
- ec_write(0x0c, 0x84);
- } else if (idedev && idedev->chip_info &&
- h8_ultrabay_device_present()) {
- config = idedev->chip_info;
- config->ide_enable_primary = 1;
- pmh7_ultrabay_power_enable(1);
- ec_write(0x0c, 0x84);
- } else {
- pmh7_ultrabay_power_enable(0);
- ec_write(0x0c, 0x04);
- }
-
- /* set dock status led */
- ec_write(0x0c, 0x08);
- ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
-
- if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
- printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
- defaults_loaded = 0;
- }
-
- if (!defaults_loaded) {
- printk(BIOS_INFO, "Restoring CMOS defaults\n");
- set_option("tft_brightness", &(u8[]){ 0xff });
- set_option("volume", &(u8[]){ 0x03 });
- /* set baudrate to 115200 baud */
- set_option("baud_rate", &(u8[]){ 0x00 });
- /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
- set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
- set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
- }
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/lenovo/t60/ramstage.c b/src/mainboard/lenovo/t60/ramstage.c
new file mode 100644
index 0000000..bd4c4a7
--- /dev/null
+++ b/src/mainboard/lenovo/t60/ramstage.c
@@ -0,0 +1,104 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+static acpi_cstate_t cst_entries[] = {
+ { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
+ { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
+ { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ struct southbridge_intel_i82801gx_config *config;
+ device_t dev0, idedev;
+ u8 defaults_loaded = 0;
+
+ /* If we're resuming from suspend, blink suspend LED */
+ dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+ if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ ec_write(0x0c, 0xc7);
+
+ idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+
+ if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
+ /* legacy I/O connected */
+ pmh7_ultrabay_power_enable(1);
+ ec_write(0x0c, 0x84);
+ } else if (idedev && idedev->chip_info &&
+ h8_ultrabay_device_present()) {
+ config = idedev->chip_info;
+ config->ide_enable_primary = 1;
+ pmh7_ultrabay_power_enable(1);
+ ec_write(0x0c, 0x84);
+ } else {
+ pmh7_ultrabay_power_enable(0);
+ ec_write(0x0c, 0x04);
+ }
+
+ /* set dock status led */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
+
+ if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
+ printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
+ defaults_loaded = 0;
+ }
+
+ if (!defaults_loaded) {
+ printk(BIOS_INFO, "Restoring CMOS defaults\n");
+ set_option("tft_brightness", &(u8[]){ 0xff });
+ set_option("volume", &(u8[]){ 0x03 });
+ /* set baudrate to 115200 baud */
+ set_option("baud_rate", &(u8[]){ 0x00 });
+ /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
+ set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
+ set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
+ }
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
deleted file mode 100644
index 4ded239..0000000
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <delay.h>
-#include <arch/coreboot_tables.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <ec/lenovo/pmh7/pmh7.h>
-#include <ec/acpi/ec.h>
-#include <ec/lenovo/h8/h8.h>
-#include <northbridge/intel/i945/i945.h>
-#include <pc80/mc146818rtc.h>
-#include "dock.h"
-#include <arch/x86/include/arch/acpigen.h>
-
-static acpi_cstate_t cst_entries[] = {
- { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
- { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
- { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
-};
-
-int get_cst_entries(acpi_cstate_t **entries)
-{
- *entries = cst_entries;
- return ARRAY_SIZE(cst_entries);
-}
-
-static void mainboard_enable(device_t dev)
-{
- device_t dev0, idedev, sdhci_dev;
- u8 defaults_loaded = 0;
-
- ec_clr_bit(0x03, 2);
-
- if (inb(0x164c) & 0x08) {
- ec_set_bit(0x03, 2);
- ec_write(0x0c, 0x88);
- }
- /* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
- ec_write(0x0c, 0xc7);
-
- idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
- if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
- struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
- config->ide_enable_primary = 1;
- /* enable Ultrabay power */
- outb(inb(0x1628) | 0x01, 0x1628);
- ec_write(0x0c, 0x84);
- } else {
- /* disable Ultrabay power */
- outb(inb(0x1628) & ~0x01, 0x1628);
- ec_write(0x0c, 0x04);
- }
-
- /* Set SDHCI write protect polarity "SDWPPol" */
- sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0);
- if (sdhci_dev) {
- if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
- /* unlock */
- pci_write_config8(sdhci_dev, 0xf9, 0xfc);
- /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */
- pci_write_config8(sdhci_dev, 0xfa, 0x20);
- /* restore lock */
- pci_write_config8(sdhci_dev, 0xf9, 0x00);
- }
- }
-
- if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
- printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
- defaults_loaded = 0;
- }
-
- if (!defaults_loaded) {
- printk(BIOS_INFO, "Restoring CMOS defaults\n");
- set_option("tft_brightness", &(u8[]){ 0xff });
- set_option("volume", &(u8[]){ 0x03 });
- /* set baudrate to 115200 baud */
- set_option("baud_rate", &(u8[]){ 0x00 });
- /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
- set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
- set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
- }
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/lenovo/x60/ramstage.c b/src/mainboard/lenovo/x60/ramstage.c
new file mode 100644
index 0000000..4ded239
--- /dev/null
+++ b/src/mainboard/lenovo/x60/ramstage.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+#include "dock.h"
+#include <arch/x86/include/arch/acpigen.h>
+
+static acpi_cstate_t cst_entries[] = {
+ { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
+ { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
+ { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ device_t dev0, idedev, sdhci_dev;
+ u8 defaults_loaded = 0;
+
+ ec_clr_bit(0x03, 2);
+
+ if (inb(0x164c) & 0x08) {
+ ec_set_bit(0x03, 2);
+ ec_write(0x0c, 0x88);
+ }
+ /* If we're resuming from suspend, blink suspend LED */
+ dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+ if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ ec_write(0x0c, 0xc7);
+
+ idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+ if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
+ struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
+ config->ide_enable_primary = 1;
+ /* enable Ultrabay power */
+ outb(inb(0x1628) | 0x01, 0x1628);
+ ec_write(0x0c, 0x84);
+ } else {
+ /* disable Ultrabay power */
+ outb(inb(0x1628) & ~0x01, 0x1628);
+ ec_write(0x0c, 0x04);
+ }
+
+ /* Set SDHCI write protect polarity "SDWPPol" */
+ sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0);
+ if (sdhci_dev) {
+ if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
+ /* unlock */
+ pci_write_config8(sdhci_dev, 0xf9, 0xfc);
+ /* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */
+ pci_write_config8(sdhci_dev, 0xfa, 0x20);
+ /* restore lock */
+ pci_write_config8(sdhci_dev, 0xf9, 0x00);
+ }
+ }
+
+ if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
+ printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
+ defaults_loaded = 0;
+ }
+
+ if (!defaults_loaded) {
+ printk(BIOS_INFO, "Restoring CMOS defaults\n");
+ set_option("tft_brightness", &(u8[]){ 0xff });
+ set_option("volume", &(u8[]){ 0x03 });
+ /* set baudrate to 115200 baud */
+ set_option("baud_rate", &(u8[]){ 0x00 });
+ /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
+ set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
+ set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
+ }
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/lippert/frontrunner/mainboard.c b/src/mainboard/lippert/frontrunner/mainboard.c
deleted file mode 100644
index ec1503e..0000000
--- a/src/mainboard/lippert/frontrunner/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Lippert Cool Frontrunner Mainboard")
-};
-
diff --git a/src/mainboard/lippert/frontrunner/ramstage.c b/src/mainboard/lippert/frontrunner/ramstage.c
new file mode 100644
index 0000000..ec1503e
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Lippert Cool Frontrunner Mainboard")
+};
+
diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c
deleted file mode 100644
index 9b7ad98..0000000
--- a/src/mainboard/lippert/hurricane-lx/mainboard.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
-#if CONFIG_ONBOARD_UARTS_RS485
- #define SIO_GP1X_CONFIG 0x06
-#else
- #define SIO_GP1X_CONFIG 0x00
-#endif
-
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
- 0x1900, /* Enable monitoring */
- 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
- 0x805C, /* Unlock zero adjust */
- 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
- 0x005C, /* Lock zero adjust */
- 0xD014 /* Also set FAN_CTL polarity to Active High */
-};
-
-static void init(struct device *dev)
-{
- unsigned int gpio_base, i;
- printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__);
-
- /* Init CS5536 GPIOs */
- gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
-
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
- outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default)
- outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
- outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
-#if !CONFIG_BOARD_OLD_REVISION
- outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
- outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
-#endif
- outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old)
-
- /* Init Environment Controller. */
- for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
- u16 val = ec_init_table[i];
- outb((u8)val, 0x0295);
- outb(val >> 8, 0x0296);
- }
-
- /* bit2 = RS485_EN2, bit1 = RS485_EN1 */
- outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
-
- printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("LiPPERT Hurricane-LX Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/lippert/hurricane-lx/ramstage.c b/src/mainboard/lippert/hurricane-lx/ramstage.c
new file mode 100644
index 0000000..cf12bd5
--- /dev/null
+++ b/src/mainboard/lippert/hurricane-lx/ramstage.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on ramstage.c from the SpaceRunner-LX mainboard. */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
+#if CONFIG_ONBOARD_UARTS_RS485
+ #define SIO_GP1X_CONFIG 0x06
+#else
+ #define SIO_GP1X_CONFIG 0x00
+#endif
+
+static const u16 ec_init_table[] = { /* hi=data, lo=index */
+ 0x1900, /* Enable monitoring */
+ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
+ 0x805C, /* Unlock zero adjust */
+ 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
+ 0x005C, /* Lock zero adjust */
+ 0xD014 /* Also set FAN_CTL polarity to Active High */
+};
+
+static void init(struct device *dev)
+{
+ unsigned int gpio_base, i;
+ printk(BIOS_DEBUG, "LiPPERT Hurricane-LX ENTER %s\n", __func__);
+
+ /* Init CS5536 GPIOs */
+ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
+
+ outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
+ outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default)
+ outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
+ outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
+#if !CONFIG_BOARD_OLD_REVISION
+ outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
+ outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
+#endif
+ outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old)
+
+ /* Init Environment Controller. */
+ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
+ u16 val = ec_init_table[i];
+ outb((u8)val, 0x0295);
+ outb(val >> 8, 0x0296);
+ }
+
+ /* bit2 = RS485_EN2, bit1 = RS485_EN1 */
+ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
+
+ printk(BIOS_DEBUG, "LiPPERT Hurricane-LX EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("LiPPERT Hurricane-LX Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c
deleted file mode 100644
index cfec2a8..0000000
--- a/src/mainboard/lippert/literunner-lx/mainboard.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Based on mainboard.c from the SpaceRunner-LX mainboard. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
-#if CONFIG_ONBOARD_UARTS_RS485
- #define SIO_GP1X_CONFIG 0x07
-#else
- #define SIO_GP1X_CONFIG 0x01
-#endif
-
-/* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */
-#define SIO_GP2X_CONFIG 0x00
-
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
- 0x1900, /* Enable monitoring */
- 0x3050, /* VIN4,5 enabled */
- 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
- 0x805C, /* Unlock zero adjust */
- 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
- 0x005C, /* Lock zero adjust */
- 0xD014 /* Also set FAN_CTL polarity to Active High */
-};
-
-static void init(struct device *dev)
-{
- unsigned int gpio_base, i;
- printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__);
-
- /* Init CS5536 GPIOs */
- gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
-
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
- outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
- outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
- outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
- outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
- outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
-
- /* Init Environment Controller. */
- for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
- u16 val = ec_init_table[i];
- outb((u8)val, 0x0295);
- outb(val >> 8, 0x0296);
- }
-
- /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
- outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
- /* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */
- outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */
-
- printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("LiPPERT LiteRunner-LX Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/lippert/literunner-lx/ramstage.c b/src/mainboard/lippert/literunner-lx/ramstage.c
new file mode 100644
index 0000000..56a6e5a
--- /dev/null
+++ b/src/mainboard/lippert/literunner-lx/ramstage.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on ramstage.c from the SpaceRunner-LX mainboard. */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
+#if CONFIG_ONBOARD_UARTS_RS485
+ #define SIO_GP1X_CONFIG 0x07
+#else
+ #define SIO_GP1X_CONFIG 0x01
+#endif
+
+/* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */
+#define SIO_GP2X_CONFIG 0x00
+
+static const u16 ec_init_table[] = { /* hi=data, lo=index */
+ 0x1900, /* Enable monitoring */
+ 0x3050, /* VIN4,5 enabled */
+ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
+ 0x805C, /* Unlock zero adjust */
+ 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
+ 0x005C, /* Lock zero adjust */
+ 0xD014 /* Also set FAN_CTL polarity to Active High */
+};
+
+static void init(struct device *dev)
+{
+ unsigned int gpio_base, i;
+ printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__);
+
+ /* Init CS5536 GPIOs */
+ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
+
+ outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
+ outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
+ outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
+ outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
+ outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
+ outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
+
+ /* Init Environment Controller. */
+ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
+ u16 val = ec_init_table[i];
+ outb((u8)val, 0x0295);
+ outb(val >> 8, 0x0296);
+ }
+
+ /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
+ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
+ /* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */
+ outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */
+
+ printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("LiPPERT LiteRunner-LX Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c
deleted file mode 100644
index 26adb2f..0000000
--- a/src/mainboard/lippert/roadrunner-lx/mainboard.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Based on mainboard.c from AMD's DB800 mainboard. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */
-#if CONFIG_ONBOARD_UARTS_RS485
- #define SIO_GP1X_CONFIG 0x26
-#else
- #define SIO_GP1X_CONFIG 0x20
-#endif
-
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
- 0x1900, /* Enable monitoring */
- 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
- 0x805C, /* Unlock zero adjust */
- 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
- 0x005C, /* Lock zero adjust */
- 0xD014 /* Also set FAN_CTL polarity to Active High */
-};
-
-static void init(struct device *dev)
-{
- unsigned int gpio_base, i;
- printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__);
-
- /* Init CS5536 GPIOs. */
- gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
-
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
- outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
- outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
- outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED
-
- /* Init Environment Controller. */
- for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
- u16 val = ec_init_table[i];
- outb((u8)val, 0x0295);
- outb(val >> 8, 0x0296);
- }
-
- /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */
- outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
- printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("LiPPERT RoadRunner-LX Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/lippert/roadrunner-lx/ramstage.c b/src/mainboard/lippert/roadrunner-lx/ramstage.c
new file mode 100644
index 0000000..63ce4c8
--- /dev/null
+++ b/src/mainboard/lippert/roadrunner-lx/ramstage.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on ramstage.c from AMD's DB800 mainboard. */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */
+#if CONFIG_ONBOARD_UARTS_RS485
+ #define SIO_GP1X_CONFIG 0x26
+#else
+ #define SIO_GP1X_CONFIG 0x20
+#endif
+
+static const u16 ec_init_table[] = { /* hi=data, lo=index */
+ 0x1900, /* Enable monitoring */
+ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
+ 0x805C, /* Unlock zero adjust */
+ 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
+ 0x005C, /* Lock zero adjust */
+ 0xD014 /* Also set FAN_CTL polarity to Active High */
+};
+
+static void init(struct device *dev)
+{
+ unsigned int gpio_base, i;
+ printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX ENTER %s\n", __func__);
+
+ /* Init CS5536 GPIOs. */
+ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
+
+ outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
+ outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
+ outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
+ outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED
+
+ /* Init Environment Controller. */
+ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
+ u16 val = ec_init_table[i];
+ outb((u8)val, 0x0295);
+ outb(val >> 8, 0x0296);
+ }
+
+ /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */
+ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
+ printk(BIOS_DEBUG, "LiPPERT RoadRunner-LX EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("LiPPERT RoadRunner-LX Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c
deleted file mode 100644
index f2aeb10..0000000
--- a/src/mainboard/lippert/spacerunner-lx/mainboard.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Based on mainboard.c from AMD's DB800 mainboard. */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
-#if CONFIG_ONBOARD_UARTS_RS485
- #define SIO_GP1X_CONFIG 0x07
-#else
- #define SIO_GP1X_CONFIG 0x01
-#endif
-
-static const u16 ec_init_table[] = { /* hi=data, lo=index */
- 0x1900, /* Enable monitoring */
- 0x3050, /* VIN4,5 enabled */
- 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
- 0x805C, /* Unlock zero adjust */
- 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
- 0x005C, /* Lock zero adjust */
- 0xD014 /* Also set FAN_CTL polarity to Active High */
-};
-
-static void init(struct device *dev)
-{
- unsigned int gpio_base, i;
- printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
-
- /* Init CS5536 GPIOs */
- gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
-
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
- outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
- outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
- outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
- outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
- outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
- outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
-
- /* Init Environment Controller. */
- for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
- u16 val = ec_init_table[i];
- outb((u8)val, 0x0295);
- outb(val >> 8, 0x0296);
- }
-
- /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
- outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
-
- printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/lippert/spacerunner-lx/ramstage.c b/src/mainboard/lippert/spacerunner-lx/ramstage.c
new file mode 100644
index 0000000..c71ed76
--- /dev/null
+++ b/src/mainboard/lippert/spacerunner-lx/ramstage.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on ramstage.c from AMD's DB800 mainboard. */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
+#if CONFIG_ONBOARD_UARTS_RS485
+ #define SIO_GP1X_CONFIG 0x07
+#else
+ #define SIO_GP1X_CONFIG 0x01
+#endif
+
+static const u16 ec_init_table[] = { /* hi=data, lo=index */
+ 0x1900, /* Enable monitoring */
+ 0x3050, /* VIN4,5 enabled */
+ 0x0351, /* TMPIN1,2 diode mode, TMPIN3 off */
+ 0x805C, /* Unlock zero adjust */
+ 0x7056, 0x3C57, /* Zero adjust TMPIN1,2 */
+ 0x005C, /* Lock zero adjust */
+ 0xD014 /* Also set FAN_CTL polarity to Active High */
+};
+
+static void init(struct device *dev)
+{
+ unsigned int gpio_base, i;
+ printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__);
+
+ /* Init CS5536 GPIOs */
+ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
+ PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
+
+ outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD#
+ outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
+ outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
+ outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
+ outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
+ outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
+ outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
+
+ /* Init Environment Controller. */
+ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
+ u16 val = ec_init_table[i];
+ outb((u8)val, 0x0295);
+ outb(val >> 8, 0x0296);
+ }
+
+ /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */
+ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */
+
+ printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c
deleted file mode 100644
index 04af449..0000000
--- a/src/mainboard/mitac/6513wu/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Mitac 6513WU Mainboard")
-};
diff --git a/src/mainboard/mitac/6513wu/ramstage.c b/src/mainboard/mitac/6513wu/ramstage.c
new file mode 100644
index 0000000..04af449
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold at ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Mitac 6513WU Mainboard")
+};
diff --git a/src/mainboard/msi/ms6119/mainboard.c b/src/mainboard/msi/ms6119/mainboard.c
deleted file mode 100644
index 7ef3d4b..0000000
--- a/src/mainboard/msi/ms6119/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-6119 Mainboard")
-};
diff --git a/src/mainboard/msi/ms6119/ramstage.c b/src/mainboard/msi/ms6119/ramstage.c
new file mode 100644
index 0000000..7ef3d4b
--- /dev/null
+++ b/src/mainboard/msi/ms6119/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-6119 Mainboard")
+};
diff --git a/src/mainboard/msi/ms6147/mainboard.c b/src/mainboard/msi/ms6147/mainboard.c
deleted file mode 100644
index 091de54..0000000
--- a/src/mainboard/msi/ms6147/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Mats Erik Andersson <mats.andersson at gisladisker.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-6147 Mainboard")
-};
diff --git a/src/mainboard/msi/ms6147/ramstage.c b/src/mainboard/msi/ms6147/ramstage.c
new file mode 100644
index 0000000..091de54
--- /dev/null
+++ b/src/mainboard/msi/ms6147/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Mats Erik Andersson <mats.andersson at gisladisker.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-6147 Mainboard")
+};
diff --git a/src/mainboard/msi/ms6156/mainboard.c b/src/mainboard/msi/ms6156/mainboard.c
deleted file mode 100644
index 28b5e81..0000000
--- a/src/mainboard/msi/ms6156/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-6156 Mainboard")
-};
diff --git a/src/mainboard/msi/ms6156/ramstage.c b/src/mainboard/msi/ms6156/ramstage.c
new file mode 100644
index 0000000..28b5e81
--- /dev/null
+++ b/src/mainboard/msi/ms6156/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-6156 Mainboard")
+};
diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c
deleted file mode 100644
index 76c8c04..0000000
--- a/src/mainboard/msi/ms6178/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-6178 Mainboard")
-};
diff --git a/src/mainboard/msi/ms6178/ramstage.c b/src/mainboard/msi/ms6178/ramstage.c
new file mode 100644
index 0000000..76c8c04
--- /dev/null
+++ b/src/mainboard/msi/ms6178/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-6178 Mainboard")
+};
diff --git a/src/mainboard/msi/ms7135/mainboard.c b/src/mainboard/msi/ms7135/mainboard.c
deleted file mode 100644
index 3ed0c6b..0000000
--- a/src/mainboard/msi/ms7135/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch at kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS7135 Mainboard")
-};
diff --git a/src/mainboard/msi/ms7135/ramstage.c b/src/mainboard/msi/ms7135/ramstage.c
new file mode 100644
index 0000000..3ed0c6b
--- /dev/null
+++ b/src/mainboard/msi/ms7135/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch at kollasch.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS7135 Mainboard")
+};
diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c
deleted file mode 100644
index 06d606f..0000000
--- a/src/mainboard/msi/ms7260/mainboard.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-#if 0
-#include "hda_verb.h"
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-#endif
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
- // .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/msi/ms7260/ramstage.c b/src/mainboard/msi/ms7260/ramstage.c
new file mode 100644
index 0000000..06d606f
--- /dev/null
+++ b/src/mainboard/msi/ms7260/ramstage.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+#if 0
+#include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+#endif
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
+ // .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/msi/ms9185/mainboard.c b/src/mainboard/msi/ms9185/mainboard.c
deleted file mode 100644
index f3e28d4..0000000
--- a/src/mainboard/msi/ms9185/mainboard.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi at gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-9185 Mainboard")
-};
diff --git a/src/mainboard/msi/ms9185/ramstage.c b/src/mainboard/msi/ms9185/ramstage.c
new file mode 100644
index 0000000..f3e28d4
--- /dev/null
+++ b/src/mainboard/msi/ms9185/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by bxshi <bingxunshi at gmail.com> for MSI.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-9185 Mainboard")
+};
diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c
deleted file mode 100644
index 800fd25..0000000
--- a/src/mainboard/msi/ms9282/mainboard.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-// #include "hda_verb.h"
-
-static void verb_setup(void)
-{
- /* TODO: Add a correct hda_verb.h file for this board. */
- // cim_verb_data = mainboard_cim_verb_data;
- // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-9282 Mainboard")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/msi/ms9282/ramstage.c b/src/mainboard/msi/ms9282/ramstage.c
new file mode 100644
index 0000000..800fd25
--- /dev/null
+++ b/src/mainboard/msi/ms9282/ramstage.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 MSI
+ * Written by Bingxun Shi <bingxunshi at gmail.com> for MSI.
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+// #include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ /* TODO: Add a correct hda_verb.h file for this board. */
+ // cim_verb_data = mainboard_cim_verb_data;
+ // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-9282 Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
deleted file mode 100644
index e570607..0000000
--- a/src/mainboard/msi/ms9652_fam10/mainboard.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-// #include "hda_verb.h"
-
-static void verb_setup(void)
-{
- /* TODO: Add a correct hda_verb.h file for this board. */
- // cim_verb_data = mainboard_cim_verb_data;
- // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("MSI MS-9652 Mainboard (Family 10)")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/msi/ms9652_fam10/ramstage.c b/src/mainboard/msi/ms9652_fam10/ramstage.c
new file mode 100644
index 0000000..e570607
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/ramstage.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+// #include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ /* TODO: Add a correct hda_verb.h file for this board. */
+ // cim_verb_data = mainboard_cim_verb_data;
+ // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("MSI MS-9652 Mainboard (Family 10)")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c
deleted file mode 100644
index 3bbaa11..0000000
--- a/src/mainboard/nec/powermate2000/mainboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("NEC PowerMate 2000 Mainboard")
-};
diff --git a/src/mainboard/nec/powermate2000/ramstage.c b/src/mainboard/nec/powermate2000/ramstage.c
new file mode 100644
index 0000000..3bbaa11
--- /dev/null
+++ b/src/mainboard/nec/powermate2000/ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("NEC PowerMate 2000 Mainboard")
+};
diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c
deleted file mode 100644
index 11e7032..0000000
--- a/src/mainboard/newisys/khepri/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Newisys 2100 Mainboard")
-};
-
diff --git a/src/mainboard/newisys/khepri/ramstage.c b/src/mainboard/newisys/khepri/ramstage.c
new file mode 100644
index 0000000..11e7032
--- /dev/null
+++ b/src/mainboard/newisys/khepri/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Newisys 2100 Mainboard")
+};
+
diff --git a/src/mainboard/nokia/ip530/mainboard.c b/src/mainboard/nokia/ip530/mainboard.c
deleted file mode 100644
index 8b934ff..0000000
--- a/src/mainboard/nokia/ip530/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Bertens <mbertens at xs4all.nl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Nokia IP530 Mainboard")
-};
diff --git a/src/mainboard/nokia/ip530/ramstage.c b/src/mainboard/nokia/ip530/ramstage.c
new file mode 100644
index 0000000..8b934ff
--- /dev/null
+++ b/src/mainboard/nokia/ip530/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens at xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Nokia IP530 Mainboard")
+};
diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c
deleted file mode 100644
index 5836571..0000000
--- a/src/mainboard/nvidia/l1_2pvv/mainboard.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "hda_verb.h"
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_enable(device_t dev)
-{
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("NVIDIA l1_2pvv Mainboard")
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/nvidia/l1_2pvv/ramstage.c b/src/mainboard/nvidia/l1_2pvv/ramstage.c
new file mode 100644
index 0000000..5836571
--- /dev/null
+++ b/src/mainboard/nvidia/l1_2pvv/ramstage.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "hda_verb.h"
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("NVIDIA l1_2pvv Mainboard")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c
deleted file mode 100644
index 74c1cc4..0000000
--- a/src/mainboard/pcengines/alix1c/mainboard.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("PC Engines ALIX1.C Mainboard")
- .enable_dev = enable_dev,
-};
-
diff --git a/src/mainboard/pcengines/alix1c/ramstage.c b/src/mainboard/pcengines/alix1c/ramstage.c
new file mode 100644
index 0000000..74c1cc4
--- /dev/null
+++ b/src/mainboard/pcengines/alix1c/ramstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "ALIX1.C ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "ALIX1.C EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("PC Engines ALIX1.C Mainboard")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/mainboard/pcengines/alix2d/mainboard.c b/src/mainboard/pcengines/alix2d/mainboard.c
deleted file mode 100644
index 1b526c9..0000000
--- a/src/mainboard/pcengines/alix2d/mainboard.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("PC Engines ALIX.2D Mainboard")
- .enable_dev = enable_dev,
-};
-
diff --git a/src/mainboard/pcengines/alix2d/ramstage.c b/src/mainboard/pcengines/alix2d/ramstage.c
new file mode 100644
index 0000000..1b526c9
--- /dev/null
+++ b/src/mainboard/pcengines/alix2d/ramstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "ALIX.2D ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "ALIX.2D EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("PC Engines ALIX.2D Mainboard")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c
deleted file mode 100644
index ff98977..0000000
--- a/src/mainboard/rca/rm4100/mainboard.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <boot/tables.h>
-#include <arch/coreboot_tables.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-static void mainboard_init(device_t dev)
-{
- // TODO Switch parport LEDs again
-}
-
-static void mainboard_enable(device_t dev)
-{
- // TODO Switch parport LEDs
- dev->ops->init = mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
- CHIP_NAME("RCA RM4100 Mainboard")
-};
diff --git a/src/mainboard/rca/rm4100/ramstage.c b/src/mainboard/rca/rm4100/ramstage.c
new file mode 100644
index 0000000..ff98977
--- /dev/null
+++ b/src/mainboard/rca/rm4100/ramstage.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+static void mainboard_init(device_t dev)
+{
+ // TODO Switch parport LEDs again
+}
+
+static void mainboard_enable(device_t dev)
+{
+ // TODO Switch parport LEDs
+ dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+ CHIP_NAME("RCA RM4100 Mainboard")
+};
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
deleted file mode 100644
index 1f4ebc7..0000000
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/tables.h>
-#include <delay.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <arch/coreboot_tables.h>
-
-#include <ec/acpi/ec.h>
-#include "m3885.h"
-
-#define DUMP_RUNTIME_REGISTERS 0
-
-static void backlight_enable(void)
-{
-#if 0
-// Disabled, don't let the X9511 burn out
- int i;
-
- /* P56 is Brightness Up, and it needs a Pulse instead of a
- * Level
- */
- for (i=0; i < 28; i++) {
- //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
- m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
- }
-#endif
- printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f));
-}
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
- u8 display_id;
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f40: /* Boot Panel Type */
- /* LCD panel type is SIO GPIO40-43 */
- // display_id = inb(0x60f) & 0x0f;
- display_id = 3;
- // M.x86.R_AX = 0x015f; // Supported but failed
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = display_id;
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-
-static void int15_install(void)
-{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
- int res = -1;
-
- /* This int15 handler is Intel IGD. specific. Other chipsets need other
- * handlers. The right way to do this is to move this handler code into
- * the mainboard or northbridge code.
- * TODO: completely move to mainboards / chipsets.
- */
- switch (regs->eax & 0xffff) {
- /* And now Intel IGD code */
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
- case 0x5f35:
- regs->eax = 0x5f;
- regs->ecx = BOOT_DISPLAY_DEFAULT;
- res = 0;
- break;
- case 0x5f40:
- regs->eax = 0x5f;
- regs->ecx = 3; // This is mainboard specific
- printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
- res = 0;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- }
-
- return res;
-}
-
-static void int15_install(void)
-{
- mainboard_interrupt_handlers(0x15, &int15_handler);
-}
-#endif
-
-#if DUMP_RUNTIME_REGISTERS
-static void dump_runtime_registers(void)
-{
- int i;
-
- printk(BIOS_DEBUG, "SuperIO runtime register block:\n");
- for (i=0; i<0x10; i++)
- printk(BIOS_DEBUG, "%02x ", i);
- printk(BIOS_DEBUG, "\n");
- for (i=0; i<0x10; i++)
- printk(BIOS_DEBUG, "%02x ", inb(0x600 +i));
- printk(BIOS_DEBUG, "\n");
-}
-#endif
-
-static void mainboard_enable(device_t dev)
-{
- /* Configure the MultiKey controller */
- // m3885_configure_multikey();
-
- /* Enable LCD Backlight */
- backlight_enable();
-
- /* Disable Dummy DCC -> GP45 = 1 */
- outb(inb(0x60f) | (1 << 5), 0x60f);
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
-#if DUMP_RUNTIME_REGISTERS
- dump_runtime_registers();
-#endif
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Roda Computer GmbH RK886EX Rugged Notebook (ROCKY3+)")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/roda/rk886ex/ramstage.c b/src/mainboard/roda/rk886ex/ramstage.c
new file mode 100644
index 0000000..1f4ebc7
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/ramstage.c
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/tables.h>
+#include <delay.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <arch/coreboot_tables.h>
+
+#include <ec/acpi/ec.h>
+#include "m3885.h"
+
+#define DUMP_RUNTIME_REGISTERS 0
+
+static void backlight_enable(void)
+{
+#if 0
+// Disabled, don't let the X9511 burn out
+ int i;
+
+ /* P56 is Brightness Up, and it needs a Pulse instead of a
+ * Level
+ */
+ for (i=0; i < 28; i++) {
+ //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56);
+ m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56);
+ }
+#endif
+ printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f));
+}
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ u8 display_id;
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f35: /* Boot Display */
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ /* LCD panel type is SIO GPIO40-43 */
+ // display_id = inb(0x60f) & 0x0f;
+ display_id = 3;
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = display_id;
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+
+static void int15_install(void)
+{
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res = -1;
+
+ /* This int15 handler is Intel IGD. specific. Other chipsets need other
+ * handlers. The right way to do this is to move this handler code into
+ * the mainboard or northbridge code.
+ * TODO: completely move to mainboards / chipsets.
+ */
+ switch (regs->eax & 0xffff) {
+ /* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+ case 0x5f35:
+ regs->eax = 0x5f;
+ regs->ecx = BOOT_DISPLAY_DEFAULT;
+ res = 0;
+ break;
+ case 0x5f40:
+ regs->eax = 0x5f;
+ regs->ecx = 3; // This is mainboard specific
+ printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+ res = 0;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ }
+
+ return res;
+}
+
+static void int15_install(void)
+{
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
+#if DUMP_RUNTIME_REGISTERS
+static void dump_runtime_registers(void)
+{
+ int i;
+
+ printk(BIOS_DEBUG, "SuperIO runtime register block:\n");
+ for (i=0; i<0x10; i++)
+ printk(BIOS_DEBUG, "%02x ", i);
+ printk(BIOS_DEBUG, "\n");
+ for (i=0; i<0x10; i++)
+ printk(BIOS_DEBUG, "%02x ", inb(0x600 +i));
+ printk(BIOS_DEBUG, "\n");
+}
+#endif
+
+static void mainboard_enable(device_t dev)
+{
+ /* Configure the MultiKey controller */
+ // m3885_configure_multikey();
+
+ /* Enable LCD Backlight */
+ backlight_enable();
+
+ /* Disable Dummy DCC -> GP45 = 1 */
+ outb(inb(0x60f) | (1 << 5), 0x60f);
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+#if DUMP_RUNTIME_REGISTERS
+ dump_runtime_registers();
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Roda Computer GmbH RK886EX Rugged Notebook (ROCKY3+)")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
deleted file mode 100644
index e83516a..0000000
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <arch/coreboot_tables.h>
-#include <ec/smsc/mec1308/ec.h>
-#include "hda_verb.h"
-#include "ec.h"
-#include "onboard.h"
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <smbios.h>
-
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-
- /* Enable EC ACPI mode for the OS before resume */
- send_ec_command(EC_SMI_DISABLE);
- send_ec_command(EC_ACPI_ENABLE);
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
- int res=-1;
-
- printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
- __func__, regs->eax & 0xffff);
-
- switch(regs->eax & 0xffff) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffffff00;
- regs->ecx |= 0x00;
- res = 0;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0001;
- res = 0;
- break;
- case 0x5f70:
- switch ((regs->ecx >> 8) & 0xff) {
- case 0:
- /* Get Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 1:
- /* Set Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 2:
- /* Get SG/Non-SG mode */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
- ((regs->ecx >> 8) & 0xff));
- return 0;
- }
- break;
-
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- break;
- }
- return res;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CL = 0x00;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 1;
- break;
- case 0x5f70:
- switch (M.x86.R_CH) {
- case 0:
- /* Get Mux */
- printk(BIOS_DEBUG, "Get Mux\n");
- M.x86.R_AX = 0x005f;
- M.x86.R_CL = 0;
- break;
- case 1:
- printk(BIOS_DEBUG, "Set Mux\n");
- /* Set Mux */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0;
- break;
- case 2:
- printk(BIOS_DEBUG, "Get SG Mode\n");
- /* Get SG/Non-SG mode */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
- M.x86.R_CH);
- return 0;
- }
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
- M.x86.R_AX);
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static void int15_install(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-#endif
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-}
-#endif
-
-/* Audio Setup */
-
-extern const u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-static void mainboard_init(device_t dev)
-{
- /* Initialize the Embedded Controller */
- lumpy_ec_init();
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
- verb_setup();
-}
-
-static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
- const char *name, u8 irq, u8 addr)
-{
- struct smbios_type41 *t = (struct smbios_type41 *)*current;
- int len = sizeof(struct smbios_type41);
-
- memset(t, 0, sizeof(struct smbios_type41));
- t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
- t->handle = *handle;
- t->length = len - 2;
- t->reference_designation = smbios_add_string(t->eos, name);
- t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
- t->device_status = 1;
- t->device_type_instance = irq;
- t->segment_group_number = 0;
- t->bus_number = addr;
- t->function_number = 0;
- t->device_number = 0;
-
- len = t->length + smbios_string_table_len(t->eos);
- *current += len;
- *handle += 1;
- return len;
-}
-
-
-static int lumpy_onboard_smbios_data(device_t dev, int *handle,
- unsigned long *current)
-{
- int len = 0;
-
- len += lumpy_smbios_type41_irq(handle, current,
- LUMPY_LIGHTSENSOR_NAME,
- LUMPY_LIGHTSENSOR_IRQ,
- LUMPY_LIGHTSENSOR_I2C_ADDR);
-
- len += lumpy_smbios_type41_irq(handle, current,
- LUMPY_TRACKPAD_NAME,
- LUMPY_TRACKPAD_IRQ,
- LUMPY_TRACKPAD_I2C_ADDR);
-
- return len;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Samsung Lumpy ChromeBook")
- .enable_dev = mainboard_enable,
- .get_smbios_data = lumpy_onboard_smbios_data,
-};
-
diff --git a/src/mainboard/samsung/lumpy/ramstage.c b/src/mainboard/samsung/lumpy/ramstage.c
new file mode 100644
index 0000000..e83516a
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/ramstage.c
@@ -0,0 +1,331 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "hda_verb.h"
+#include "ec.h"
+#include "onboard.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+
+ /* Enable EC ACPI mode for the OS before resume */
+ send_ec_command(EC_SMI_DISABLE);
+ send_ec_command(EC_ACPI_ENABLE);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x00;
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0001;
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ printk(BIOS_DEBUG, "Get Mux\n");
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0;
+ break;
+ case 1:
+ printk(BIOS_DEBUG, "Set Mux\n");
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ case 2:
+ printk(BIOS_DEBUG, "Get SG Mode\n");
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ return 0;
+ }
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_init(device_t dev)
+{
+ /* Initialize the Embedded Controller */
+ lumpy_ec_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
+ const char *name, u8 irq, u8 addr)
+{
+ struct smbios_type41 *t = (struct smbios_type41 *)*current;
+ int len = sizeof(struct smbios_type41);
+
+ memset(t, 0, sizeof(struct smbios_type41));
+ t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+ t->handle = *handle;
+ t->length = len - 2;
+ t->reference_designation = smbios_add_string(t->eos, name);
+ t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+ t->device_status = 1;
+ t->device_type_instance = irq;
+ t->segment_group_number = 0;
+ t->bus_number = addr;
+ t->function_number = 0;
+ t->device_number = 0;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+ *handle += 1;
+ return len;
+}
+
+
+static int lumpy_onboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += lumpy_smbios_type41_irq(handle, current,
+ LUMPY_LIGHTSENSOR_NAME,
+ LUMPY_LIGHTSENSOR_IRQ,
+ LUMPY_LIGHTSENSOR_I2C_ADDR);
+
+ len += lumpy_smbios_type41_irq(handle, current,
+ LUMPY_TRACKPAD_NAME,
+ LUMPY_TRACKPAD_IRQ,
+ LUMPY_TRACKPAD_I2C_ADDR);
+
+ return len;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Samsung Lumpy ChromeBook")
+ .enable_dev = mainboard_enable,
+ .get_smbios_data = lumpy_onboard_smbios_data,
+};
+
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
deleted file mode 100644
index 246b261..0000000
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <arch/coreboot_tables.h>
-#include "hda_verb.h"
-#include <southbridge/intel/bd82x6x/pch.h>
-
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
- int res=-1;
-
- printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
- __func__, regs->eax & 0xffff);
-
- switch(regs->eax & 0xffff) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffffff00;
- regs->ecx |= 0x01;
- res = 0;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV (eDP) *
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2 (eDP) *
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0003;
- res = 0;
- break;
- case 0x5f70:
- switch ((regs->ecx >> 8) & 0xff) {
- case 0:
- /* Get Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 1:
- /* Set Mux */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- case 2:
- /* Get SG/Non-SG mode */
- regs->eax &= 0xffff0000;
- regs->eax |= 0x005f;
- regs->ecx &= 0xffff0000;
- regs->ecx |= 0x0000;
- res = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
- ((regs->ecx >> 8) & 0xff));
- return 0;
- }
- break;
-
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- regs->eax & 0xffff);
- break;
- }
- return res;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f34:
- /*
- * Set Panel Fitting Hook:
- * bit 2 = Graphics Stretching
- * bit 1 = Text Stretching
- * bit 0 = Centering (do not set with bit1 or bit2)
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0001;
- break;
- case 0x5f35:
- /*
- * Boot Display Device Hook:
- * bit 0 = CRT
- * bit 1 = TV (eDP) *
- * bit 2 = EFP *
- * bit 3 = LFP
- * bit 4 = CRT2
- * bit 5 = TV2 (eDP) *
- * bit 6 = EFP2 *
- * bit 7 = LFP2
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0x0000;
- break;
- case 0x5f51:
- /*
- * Hook to select active LFP configuration:
- * 00h = No LVDS, VBIOS does not enable LVDS
- * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
- * 02h = SVDO-LVDS, LFP driven by SVDO decoder
- * 03h = eDP, LFP Driven by Int-DisplayPort encoder
- */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 3;
- break;
- case 0x5f70:
- /* Unknown */
- M.x86.R_AX = 0x005f;
- M.x86.R_CX = 0;
- break;
- default:
- /* Interrupt was not handled */
- printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
- M.x86.R_AX);
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static void int15_install(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-#endif
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-}
-#endif
-
-/* Audio Setup */
-
-extern const u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
- cim_verb_data = mainboard_cim_verb_data;
- cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
- verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Samsung Stumpy ChromeBox")
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/samsung/stumpy/ramstage.c b/src/mainboard/samsung/stumpy/ramstage.c
new file mode 100644
index 0000000..246b261
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/ramstage.c
@@ -0,0 +1,249 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x01;
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0003;
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0001;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP) *
+ * bit 2 = EFP *
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP) *
+ * bit 6 = EFP2 *
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 3;
+ break;
+ case 0x5f70:
+ /* Unknown */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Samsung Stumpy ChromeBox")
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
deleted file mode 100644
index e4d88db..0000000
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ /dev/null
@@ -1,881 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <delay.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/sb600/sb600.h>
-#include <southbridge/amd/rs690/chip.h>
-#include <southbridge/amd/rs690/rs690.h>
-#include <superio/ite/it8712f/it8712f.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include "int15_func.h"
-
-// ****LCD panel ID support: *****
-// Callback Sub-Function 00h - Get LCD Panel ID
-#define PANEL_TABLE_ID_NO 0 // no LCD
-#define PANEL_TABLE_ID1 1 // 1024x768_65MHz_Dual
-#define PANEL_TABLE_ID2 2 // 920x1200_162MHz
-#define PANEL_TABLE_ID3 3 // 600x1200_162MHz
-#define PANEL_TABLE_ID4 4 // 1024x768_65MHz
-#define PANEL_TABLE_ID5 5 // 1400x1050_108MHz
-#define PANEL_TABLE_ID6 6 // 1680x1050_119MHz
-#define PANEL_TABLE_ID7 7 // 2048x1536_164MHz
-#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz
-#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01
-
-// Callback Sub-Function 05h – Select Boot-up TV Standard
-#define TV_MODE_00 0x00 /* NTSC */
-#define TV_MODE_01 0x01 /* PAL */
-#define TV_MODE_02 0x02 /* PALM */
-#define TV_MODE_03 0x03 /* PAL60 */
-#define TV_MODE_04 0x04 /* NTSCJ */
-#define TV_MODE_05 0x05 /* PALCN */
-#define TV_MODE_06 0x06 /* PALN */
-#define TV_MODE_09 0x09 /* SCART-RGB */
-#define TV_MODE_NO 0xff /* No TV Support */
-
-#define PLX_VIDDID 0x861610b5
-
-/* 7475 Common Registers */
-#define REG_DEVREV2 0x12 /* ADT7490 only */
-#define REG_VTT 0x1E /* ADT7490 only */
-#define REG_EXTEND3 0x1F /* ADT7490 only */
-#define REG_VOLTAGE_BASE 0x20
-#define REG_TEMP_BASE 0x25
-#define REG_TACH_BASE 0x28
-#define REG_PWM_BASE 0x30
-#define REG_PWM_MAX_BASE 0x38
-#define REG_DEVID 0x3D
-#define REG_VENDID 0x3E
-#define REG_DEVID2 0x3F
-#define REG_STATUS1 0x41
-#define REG_STATUS2 0x42
-#define REG_VID 0x43 /* ADT7476 only */
-#define REG_VOLTAGE_MIN_BASE 0x44
-#define REG_VOLTAGE_MAX_BASE 0x45
-#define REG_TEMP_MIN_BASE 0x4E
-#define REG_TEMP_MAX_BASE 0x4F
-#define REG_TACH_MIN_BASE 0x54
-#define REG_PWM_CONFIG_BASE 0x5C
-#define REG_TEMP_TRANGE_BASE 0x5F
-#define REG_PWM_MIN_BASE 0x64
-#define REG_TEMP_TMIN_BASE 0x67
-#define REG_TEMP_THERM_BASE 0x6A
-#define REG_REMOTE1_HYSTERSIS 0x6D
-#define REG_REMOTE2_HYSTERSIS 0x6E
-#define REG_TEMP_OFFSET_BASE 0x70
-#define REG_CONFIG2 0x73
-#define REG_EXTEND1 0x76
-#define REG_EXTEND2 0x77
-#define REG_CONFIG1 0x40 // ADT7475
-#define REG_CONFIG3 0x78
-#define REG_CONFIG5 0x7C
-#define REG_CONFIG6 0x10 // ADT7475
-#define REG_CONFIG7 0x11 // ADT7475
-#define REG_CONFIG4 0x7D
-#define REG_STATUS4 0x81 /* ADT7490 only */
-#define REG_VTT_MIN 0x84 /* ADT7490 only */
-#define REG_VTT_MAX 0x86 /* ADT7490 only */
-
-#define VID_VIDSEL 0x80 /* ADT7476 only */
-
-#define CONFIG2_ATTN 0x20
-#define CONFIG3_SMBALERT 0x01
-#define CONFIG3_THERM 0x02
-#define CONFIG4_PINFUNC 0x03
-#define CONFIG4_MAXDUTY 0x08
-#define CONFIG4_ATTN_IN10 0x30
-#define CONFIG4_ATTN_IN43 0xC0
-#define CONFIG5_TWOSCOMP 0x01
-#define CONFIG5_TEMPOFFSET 0x02
-#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */
-#define REMOTE1 0
-#define LOCAL 1
-#define REMOTE2 2
-
-/* ADT7475 Settings */
-#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */
-#define ADT7475_TEMP_COUNT 3
-#define ADT7475_TACH_COUNT 4
-#define ADT7475_PWM_COUNT 3
-
-/* Macros to easily index the registers */
-#define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
-#define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
-
-#define PWM_REG(idx) (REG_PWM_BASE + (idx))
-#define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
-#define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
-#define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
-
-#define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
-#define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
-#define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
-
-#define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
-#define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
-#define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
-#define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
-#define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
-#define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
-#define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
-
-#define SMBUS_IO_BASE 0x1000
-#define ADT7475_ADDRESS 0x2E
-
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-
-static u32 smbus_io_base = SMBUS_IO_BASE;
-static u32 adt7475_address = ADT7475_ADDRESS;
-
-/* Macro to read the registers */
-#define adt7475_read_byte(reg) \
- do_smbus_read_byte(smbus_io_base, adt7475_address, reg)
-
-#define adt7475_write_byte(reg, val) \
- do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
-
-#define TWOS_COMPL 1
-
-struct __table__{
- const char *info;
- u8 val;
-};
-
-struct __table__ dutycycles[] = {
- {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73},
- {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4},
- {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5},
- {"100%", 0xff}
-};
-#define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__)
-#define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix
-#define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range"
-#if TWOS_COMPL == 0
-struct __table__ temperatures[] = {
- {"30°C", 0x5e},{"35°C", 0x63},{"40°C", 0x68},{"45°C", 0x6d},{"50°C", 0x72},
- {"55°C", 0x77},{"60°C", 0x7c},{"65°C", 0x81},{"70°C", 0x86},{"75°C", 0x8b},
- {"80°C", 0x90}
-};
-#else
-struct __table__ temperatures[] = {
- {"30°C", 30},{"35°C", 35},{"40°C", 40},{"45°C", 45},{"50°C", 50},
- {"55°C", 55},{"60°C", 60},{"65°C", 65},{"70°C", 70},{"75°C", 75},
- {"80°C", 80}
-};
-#endif
-int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0};
-
-#define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__)
-#define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix
-#define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range"
-
-struct fan_control {
- unsigned int enable : 1;
- u8 polarity;
- u8 t_min;
- u8 t_max;
- u8 pwm_min;
- u8 pwm_max;
- u8 t_range;
-};
-/* ############################################################################################# */
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x4e08: /* Boot Display */
- switch (M.x86.R_BX) {
- case 0x80:
- M.x86.R_AX &= ~(0xff); // Success
- M.x86.R_BX &= ~(0xff);
- printk(BIOS_DEBUG, "Integrated System Information\n");
- break;
- case 0x00:
- M.x86.R_AX &= ~(0xff);
- M.x86.R_BX = 0x00;
- printk(BIOS_DEBUG, "Panel ID = 0\n");
- break;
- case 0x05:
- M.x86.R_AX &= ~(0xff);
- M.x86.R_BX = 0xff;
- printk(BIOS_DEBUG, "TV = off\n");
- break;
- default:
- return 0;
- }
- break;
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f40: /* Boot Panel Type */
- // M.x86.R_AX = 0x015f; // Supported but failed
- M.x86.R_AX = 0x005f; // Success
- M.x86.R_CL = 3; // Display ID
- break;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-
-static void int15_install(void)
-{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-}
-#endif
-/* ############################################################################################# */
-
- /**
- * @brief
- *
- * @param
- */
-
-static u8 calc_trange(u8 t_min, u8 t_max) {
-
- u8 prev;
- int i;
- int diff = t_max - t_min;
-
- // walk through the trange table
- for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
- if( trange[i] < diff ) {
- prev = i; // save last val
- continue;
- }
- if( diff == trange[i] ) return i;
- if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
- return i;
- }
- return prev;
-}
-
-/********************************************************
-* sina uses SB600 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void cable_detect(void)
-{
-
- u8 byte;
- struct device *sm_dev;
- struct device *ide_dev;
-
- /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
- printk(BIOS_DEBUG, "%s.\n", __func__);
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0xA9);
- byte |= (1 << 5); /* Set Gpio9 as input */
- pci_write_config8(sm_dev, 0xA9, byte);
-
- /* IDE Controller (Device 20, Function 1) on SB600 */
- ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
-
- byte = pci_read_config8(ide_dev, 9);
- printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility");
-
- byte = pci_read_config8(ide_dev, 0x56);
- byte &= ~(7 << 0);
- if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) )
- byte |= 2 << 0; /* mode 2 */
- else
- byte |= 5 << 0; /* mode 5 */
- printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0));
- pci_write_config8(ide_dev, 0x56, byte);
-}
-
-/**
- * @brief Detect the ADT7475 device
- *
- * @param
- */
-
-static const char * adt7475_detect( void ) {
-
- int vendid, devid, devid2;
- const char *name = NULL;
-
- vendid = adt7475_read_byte(REG_VENDID);
- devid2 = adt7475_read_byte(REG_DEVID2);
- if (vendid != 0x41 || /* Analog Devices */
- (devid2 & 0xf8) != 0x68) {
- return name;
- }
-
- devid = adt7475_read_byte(REG_DEVID);
- if (devid == 0x73)
- name = "adt7473";
- else if (devid == 0x75 && adt7475_address == 0x2e)
- name = "adt7475";
- else if (devid == 0x76)
- name = "adt7476";
- else if ((devid2 & 0xfc) == 0x6c)
- name = "adt7490";
-
- return name;
-}
-
-// thermal control defaults
-const struct fan_control cpu_fan_control_defaults = {
- .enable = 0, // disable by default
- .polarity = 0, // high by default
- .t_min = 3, // default = 45°C
- .t_max = 7, // 65°C
- .pwm_min = 1, // default dutycycle = 30%
- .pwm_max = 13, // 90%
-};
-const struct fan_control case_fan_control_defaults = {
- .enable = 0, // disable by default
- .polarity = 0, // high by default
- .t_min = 2, // default = 40°C
- .t_max = 8, // 70°C
- .pwm_min = 0, // default dutycycle = 25%
- .pwm_max = 13, // 90%
-};
-
-static void pm_init( void )
-{
- u16 word;
- u8 byte;
- device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to tristate */
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* set GPM5 to not wake from s5 */
- byte = pm_ioread(0x77);
- byte &= ~(1 << 5);
- pm_iowrite(0x77, byte);
-}
-
- /**
- * @brief Setup thermal config on SINA Mainboard
- *
- * @param
- */
-
-static void set_thermal_config(void)
-{
- u8 byte, byte2;
- u8 cpu_pwm_conf, case_pwm_conf;
- device_t sm_dev;
- struct fan_control cpu_fan_control, case_fan_control;
- const char *name = NULL;
-
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
-
- if( (name = adt7475_detect()) == NULL ) {
- printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
- return;
- }
- printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
-
- cpu_fan_control = cpu_fan_control_defaults;
- case_fan_control = case_fan_control_defaults;
-
- if( get_option(&byte, "cpu_fan_control") == -4 ) {
- printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__);
- } else {
- // get all the options needed
- if( get_option(&byte, "cpu_fan_control") == 0 )
- cpu_fan_control.enable = byte ? 1 : 0;
-
- get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
- get_option(&cpu_fan_control.t_min, "cpu_t_min");
- get_option(&cpu_fan_control.t_max, "cpu_t_max");
- get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min");
- get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
-
- if( get_option(&byte, "chassis_fan_control") == 0)
- case_fan_control.enable = byte ? 1 : 0;
- get_option(&case_fan_control.polarity, "chassis_fan_polarity");
- get_option(&case_fan_control.t_min, "chassis_t_min");
- get_option(&case_fan_control.t_max, "chassis_t_max");
- get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
- get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
-
- }
-
- printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
- printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high");
-
- printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
- cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
-
- printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
- cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
-
- printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
- cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
-
- printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
- cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
-
- cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
- printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
- cpu_fan_control.t_range <<= 4;
- cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
-
- printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
- printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
-
- printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
- case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
-
- printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
- case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
-
- printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
- case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
-
- printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
- case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
-
- case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
- printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
- case_fan_control.t_range <<= 4;
- case_fan_control.t_range |= (4 << 0); // 35.3Hz
-
- cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
- case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
- cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5); // manual control
- case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
-
- /* set adt7475 */
-
- adt7475_write_byte(REG_CONFIG1, 0x04); // clear register, bit 2 is read only
-
- /* Config Register 6: */
- adt7475_write_byte(REG_CONFIG6, 0x00);
- /* Config Register 7 */
- adt7475_write_byte(REG_CONFIG7, 0x00);
-
- /* Config Register 5: */
- /* set Offset 64 format, enable THERM on Remote 1& Local */
- adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);
- /* No offset for remote 1 */
- adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
- /* No offset for local */
- adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
- /* No offset for remote 2 */
- adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
-
- /* remote 1 low temp limit */
- adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
- /* remote 1 High temp limit (90C) */
- adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
-
- /* local Low Temp Limit */
- adt7475_write_byte(TEMP_MIN_REG(1), 0x00);
- /* local High Limit (90C) */
- adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
-
- /* remote 1 therm temp limit (95C) */
- adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
- /* local therm temp limit (95C) */
- adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
-
- /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
- adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
- /* PWM 3 configuration register Case fan controlled by ADTxxxx temp */
- adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
-
- if( cpu_fan_control.enable ) {
- /* PWM 1 minimum duty cycle (37%) */
- adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min);
- /* PWM 1 Maximum duty cycle (100%) */
- adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max);
- /* Remote 1 temperature Tmin (32C) */
- adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min);
- /* remote 1 Trange (53C ramp range) */
- adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range);
- } else {
- adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
- }
-
- if( case_fan_control.enable ) {
- /* PWM 2 minimum duty cycle (37%) */
- adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
- /* PWM 2 Maximum Duty Cycle (100%) */
- adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max);
- /* local temperature Tmin (32C) */
- adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min);
- /* local Trange (53C ramp range) */
- adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange
- adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq
- } else {
- adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max);
- }
-
- /* Config Register 3 - enable smbalert & therm */
- adt7475_write_byte(0x78, 0x03);
- /* Config Register 4 - enable therm output */
- adt7475_write_byte(0x7d, 0x09);
- /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
- adt7475_write_byte(0x75, 0x2e);
-
- /* Config Register 1 Set Start bit */
- adt7475_write_byte(0x40, 0x05);
-
- /* Read status register to clear any old errors */
- byte2 = adt7475_read_byte(0x42);
- byte = adt7475_read_byte(0x41);
-
- printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n",
- byte2, byte);
-
-}
-
- /**
- * @brief
- *
- * @param
- */
-
-static void patch_mmio_nonposted( void )
-{
- unsigned reg, index;
- resource_t rbase, rend;
- u32 base, limit;
- struct resource *resource;
- device_t dev;
- device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
-
- printk(BIOS_DEBUG,"%s ...\n", __func__);
-
- dev = dev_find_slot(1, PCI_DEVFN(5,0));
- // the uma frame buffer
- index = 0x10;
- resource = probe_resource(dev, index);
- if( resource ) {
- // fixup resource nonposted in k8 mmio
- /* Get the base address */
- rbase = (resource->base >> 8) & ~(0xff);
- /* Get the limit (rounded up) */
- rend = (resource_end(resource) >> 8) & ~(0xff);
-
- printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
-
- for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
- base = pci_read_config32(k8_f1,reg);
- limit = pci_read_config32(k8_f1,reg+4);
- printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
- if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
- limit |= (1 << 7);
- printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
- pci_write_config32(k8_f1, reg+4, limit);
- break;
- }
- }
- printk(BIOS_DEBUG, "\n");
- }
-}
-
- /**
- * @brief
- *
- * @param
- */
-
-struct {
- unsigned int bus;
- unsigned int devfn;
-} slot[] = {
- {0, PCI_DEVFN(0,0)},
- {0, PCI_DEVFN(18,0)},
- {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)},
- {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)},
- {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
- {255,0},
-};
-
-
-unsigned int plx_present = 0;
-
-static void update_subsystemid( device_t dev )
-{
- int i;
-
- dev->subsystem_vendor = 0x110a;
- if( plx_present ){
- dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
- } else {
- dev->subsystem_device = 0x4077; // U1P0 = 0x4077
- }
- printk(BIOS_INFO, "%s [%x/%x]\n", dev->chip_ops->name, dev->subsystem_vendor, dev->subsystem_device );
- for( i=0; slot[i].bus < 255; i++) {
- device_t d;
- d = dev_find_slot(slot[i].bus,slot[i].devfn);
- if( d ) {
- printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
- d->subsystem_device = dev->subsystem_device;
- }
- }
-}
-
- /**
- * @brief
- *
- * @param
- */
-
-static void detect_hw_variant( device_t dev )
-{
-
- device_t nb_dev =0, dev2 = 0;
- struct southbridge_amd_rs690_config *cfg;
- u32 lc_state, id = 0;
-
- printk(BIOS_INFO, "Scan for PLX device ...\n");
- nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- if (!nb_dev) {
- die("CAN NOT FIND RS690 DEVICE, HALT!\n");
- /* NOT REACHED */
- }
-
- dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
- if (!dev2) {
- die("CAN NOT FIND GFX DEVICE 2, HALT!\n");
- /* NOT REACHED */
- }
- PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2
-
- mdelay(40);
- lc_state = nbpcie_p_read_index(dev2, 0xa5); /* lc_state */
- printk(BIOS_DEBUG, "lc current state=%x\n", lc_state);
- /* LC_CURRENT_STATE = bit0-5 */
- switch( lc_state & 0x3f ){
- case 0x00:
- case 0x01:
- case 0x02:
- case 0x03:
- case 0x04:
- printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n");
- break;
- case 0x07:
- case 0x10:
- {
- struct device dummy;
- u32 pci_primary_bus, buses;
- u16 secondary, subordinate;
-
- printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));
- // save the existing primary/secondary/subordinate bus number configuration.
- secondary = dev2->bus->secondary;
- subordinate = dev2->bus->subordinate;
- buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
-
- // Configure the bus numbers for this bridge
- // bus number 1 is for internal gfx device, so we start with busnumber 2
-
- buses &= 0xff000000;
- buses |= ((2 << 8) | (0xff << 16));
- // setup the buses in device 2
- pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
-
- // fake a device descriptor for a device behind device 2
- dummy.bus = dev2->bus;
- dummy.bus->secondary = (buses >> 8) & 0xff;
- dummy.bus->subordinate = (buses >> 16) & 0xff;
- dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0
-
- id = pci_read_config32(&dummy, PCI_VENDOR_ID);
- /* Have we found something?
- * Some broken boards return 0 if a slot is empty, but
- * the expected answer is 0xffffffff
- */
- if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
- printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
- } else {
- printk(BIOS_DEBUG, "found device [%x]\n", id);
- }
- // restore changes made for device 2
- dev2->bus->secondary = secondary;
- dev2->bus->secondary = subordinate;
- pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus);
- }
- break;
- default:
- break;
- }
-
- plx_present = 0;
- if( id == PLX_VIDDID ){
- printk(BIOS_INFO, "found PLX device\n");
- plx_present = 1;
- cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
- if( cfg->gfx_tmds ) {
- printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
- cfg->gfx_tmds = 0;
- cfg->gfx_link_width = 4;
- }
- return;
- }
-}
-
-static void smm_lock( void )
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69,
- D_LCK | G_SMRAME | A_BASE_SEG);
-}
-
- /**
- * @brief Init
- *
- * @param the root device
- */
-
-static void init(device_t dev)
-{
-#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
- INT15_function_extensions int15_func;
-#endif
-
- printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
- dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-
-#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
- if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
- int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
- int15_func.regs.func05_TV_standard = TV_MODE_NO;
- install_INT15_function_extensions(&int15_func);
-#endif
- set_thermal_config();
- pm_init();
- cable_detect();
- patch_mmio_nonposted();
- smm_lock();
-}
-
-/*************************************************
-* enable the dedicated function in sina board.
-* This function called early than rs690_enable.
-*************************************************/
-static void enable_dev(device_t dev)
-{
-
- printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
- dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
-
- detect_hw_variant(dev);
- update_subsystemid(dev);
-
- dev->ops->init = init; // rest of mainboard init later
-}
-
- /**
- * @brief
- *
- * @param
- */
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- device_t dev;
- struct resource *res;
-
- dev = dev_find_slot(0, PCI_DEVFN(0,0));
- res = probe_resource(dev, 0x1C);
- if( res ) {
- printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size);
- lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
- }
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER)
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/siemens/sitemp_g1p1/ramstage.c b/src/mainboard/siemens/sitemp_g1p1/ramstage.c
new file mode 100644
index 0000000..e4d88db
--- /dev/null
+++ b/src/mainboard/siemens/sitemp_g1p1/ramstage.c
@@ -0,0 +1,881 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Siemens AG, Inc.
+ * (Written by Josef Kellermann <joseph.kellermann at heitec.de> for Siemens AG, Inc.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/rs690/chip.h>
+#include <southbridge/amd/rs690/rs690.h>
+#include <superio/ite/it8712f/it8712f.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include "int15_func.h"
+
+// ****LCD panel ID support: *****
+// Callback Sub-Function 00h - Get LCD Panel ID
+#define PANEL_TABLE_ID_NO 0 // no LCD
+#define PANEL_TABLE_ID1 1 // 1024x768_65MHz_Dual
+#define PANEL_TABLE_ID2 2 // 920x1200_162MHz
+#define PANEL_TABLE_ID3 3 // 600x1200_162MHz
+#define PANEL_TABLE_ID4 4 // 1024x768_65MHz
+#define PANEL_TABLE_ID5 5 // 1400x1050_108MHz
+#define PANEL_TABLE_ID6 6 // 1680x1050_119MHz
+#define PANEL_TABLE_ID7 7 // 2048x1536_164MHz
+#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz
+#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01
+
+// Callback Sub-Function 05h – Select Boot-up TV Standard
+#define TV_MODE_00 0x00 /* NTSC */
+#define TV_MODE_01 0x01 /* PAL */
+#define TV_MODE_02 0x02 /* PALM */
+#define TV_MODE_03 0x03 /* PAL60 */
+#define TV_MODE_04 0x04 /* NTSCJ */
+#define TV_MODE_05 0x05 /* PALCN */
+#define TV_MODE_06 0x06 /* PALN */
+#define TV_MODE_09 0x09 /* SCART-RGB */
+#define TV_MODE_NO 0xff /* No TV Support */
+
+#define PLX_VIDDID 0x861610b5
+
+/* 7475 Common Registers */
+#define REG_DEVREV2 0x12 /* ADT7490 only */
+#define REG_VTT 0x1E /* ADT7490 only */
+#define REG_EXTEND3 0x1F /* ADT7490 only */
+#define REG_VOLTAGE_BASE 0x20
+#define REG_TEMP_BASE 0x25
+#define REG_TACH_BASE 0x28
+#define REG_PWM_BASE 0x30
+#define REG_PWM_MAX_BASE 0x38
+#define REG_DEVID 0x3D
+#define REG_VENDID 0x3E
+#define REG_DEVID2 0x3F
+#define REG_STATUS1 0x41
+#define REG_STATUS2 0x42
+#define REG_VID 0x43 /* ADT7476 only */
+#define REG_VOLTAGE_MIN_BASE 0x44
+#define REG_VOLTAGE_MAX_BASE 0x45
+#define REG_TEMP_MIN_BASE 0x4E
+#define REG_TEMP_MAX_BASE 0x4F
+#define REG_TACH_MIN_BASE 0x54
+#define REG_PWM_CONFIG_BASE 0x5C
+#define REG_TEMP_TRANGE_BASE 0x5F
+#define REG_PWM_MIN_BASE 0x64
+#define REG_TEMP_TMIN_BASE 0x67
+#define REG_TEMP_THERM_BASE 0x6A
+#define REG_REMOTE1_HYSTERSIS 0x6D
+#define REG_REMOTE2_HYSTERSIS 0x6E
+#define REG_TEMP_OFFSET_BASE 0x70
+#define REG_CONFIG2 0x73
+#define REG_EXTEND1 0x76
+#define REG_EXTEND2 0x77
+#define REG_CONFIG1 0x40 // ADT7475
+#define REG_CONFIG3 0x78
+#define REG_CONFIG5 0x7C
+#define REG_CONFIG6 0x10 // ADT7475
+#define REG_CONFIG7 0x11 // ADT7475
+#define REG_CONFIG4 0x7D
+#define REG_STATUS4 0x81 /* ADT7490 only */
+#define REG_VTT_MIN 0x84 /* ADT7490 only */
+#define REG_VTT_MAX 0x86 /* ADT7490 only */
+
+#define VID_VIDSEL 0x80 /* ADT7476 only */
+
+#define CONFIG2_ATTN 0x20
+#define CONFIG3_SMBALERT 0x01
+#define CONFIG3_THERM 0x02
+#define CONFIG4_PINFUNC 0x03
+#define CONFIG4_MAXDUTY 0x08
+#define CONFIG4_ATTN_IN10 0x30
+#define CONFIG4_ATTN_IN43 0xC0
+#define CONFIG5_TWOSCOMP 0x01
+#define CONFIG5_TEMPOFFSET 0x02
+#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */
+#define REMOTE1 0
+#define LOCAL 1
+#define REMOTE2 2
+
+/* ADT7475 Settings */
+#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */
+#define ADT7475_TEMP_COUNT 3
+#define ADT7475_TACH_COUNT 4
+#define ADT7475_PWM_COUNT 3
+
+/* Macros to easily index the registers */
+#define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
+#define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
+
+#define PWM_REG(idx) (REG_PWM_BASE + (idx))
+#define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
+#define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
+#define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
+
+#define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
+#define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
+#define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
+
+#define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
+#define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
+#define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
+#define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
+#define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
+#define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
+#define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
+
+#define SMBUS_IO_BASE 0x1000
+#define ADT7475_ADDRESS 0x2E
+
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+
+static u32 smbus_io_base = SMBUS_IO_BASE;
+static u32 adt7475_address = ADT7475_ADDRESS;
+
+/* Macro to read the registers */
+#define adt7475_read_byte(reg) \
+ do_smbus_read_byte(smbus_io_base, adt7475_address, reg)
+
+#define adt7475_write_byte(reg, val) \
+ do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
+
+#define TWOS_COMPL 1
+
+struct __table__{
+ const char *info;
+ u8 val;
+};
+
+struct __table__ dutycycles[] = {
+ {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73},
+ {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4},
+ {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5},
+ {"100%", 0xff}
+};
+#define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__)
+#define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix
+#define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range"
+#if TWOS_COMPL == 0
+struct __table__ temperatures[] = {
+ {"30°C", 0x5e},{"35°C", 0x63},{"40°C", 0x68},{"45°C", 0x6d},{"50°C", 0x72},
+ {"55°C", 0x77},{"60°C", 0x7c},{"65°C", 0x81},{"70°C", 0x86},{"75°C", 0x8b},
+ {"80°C", 0x90}
+};
+#else
+struct __table__ temperatures[] = {
+ {"30°C", 30},{"35°C", 35},{"40°C", 40},{"45°C", 45},{"50°C", 50},
+ {"55°C", 55},{"60°C", 60},{"65°C", 65},{"70°C", 70},{"75°C", 75},
+ {"80°C", 80}
+};
+#endif
+int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0};
+
+#define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__)
+#define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix
+#define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range"
+
+struct fan_control {
+ unsigned int enable : 1;
+ u8 polarity;
+ u8 t_min;
+ u8 t_max;
+ u8 pwm_min;
+ u8 pwm_max;
+ u8 t_range;
+};
+/* ############################################################################################# */
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x4e08: /* Boot Display */
+ switch (M.x86.R_BX) {
+ case 0x80:
+ M.x86.R_AX &= ~(0xff); // Success
+ M.x86.R_BX &= ~(0xff);
+ printk(BIOS_DEBUG, "Integrated System Information\n");
+ break;
+ case 0x00:
+ M.x86.R_AX &= ~(0xff);
+ M.x86.R_BX = 0x00;
+ printk(BIOS_DEBUG, "Panel ID = 0\n");
+ break;
+ case 0x05:
+ M.x86.R_AX &= ~(0xff);
+ M.x86.R_BX = 0xff;
+ printk(BIOS_DEBUG, "TV = off\n");
+ break;
+ default:
+ return 0;
+ }
+ break;
+ case 0x5f35: /* Boot Display */
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f40: /* Boot Panel Type */
+ // M.x86.R_AX = 0x015f; // Supported but failed
+ M.x86.R_AX = 0x005f; // Success
+ M.x86.R_CL = 3; // Display ID
+ break;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+
+static void int15_install(void)
+{
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+/* ############################################################################################# */
+
+ /**
+ * @brief
+ *
+ * @param
+ */
+
+static u8 calc_trange(u8 t_min, u8 t_max) {
+
+ u8 prev;
+ int i;
+ int diff = t_max - t_min;
+
+ // walk through the trange table
+ for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
+ if( trange[i] < diff ) {
+ prev = i; // save last val
+ continue;
+ }
+ if( diff == trange[i] ) return i;
+ if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
+ return i;
+ }
+ return prev;
+}
+
+/********************************************************
+* sina uses SB600 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
+* get the cable type, 40 pin or 80 pin?
+********************************************************/
+static void cable_detect(void)
+{
+
+ u8 byte;
+ struct device *sm_dev;
+ struct device *ide_dev;
+
+ /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
+ printk(BIOS_DEBUG, "%s.\n", __func__);
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0xA9);
+ byte |= (1 << 5); /* Set Gpio9 as input */
+ pci_write_config8(sm_dev, 0xA9, byte);
+
+ /* IDE Controller (Device 20, Function 1) on SB600 */
+ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
+
+ byte = pci_read_config8(ide_dev, 9);
+ printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility");
+
+ byte = pci_read_config8(ide_dev, 0x56);
+ byte &= ~(7 << 0);
+ if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) )
+ byte |= 2 << 0; /* mode 2 */
+ else
+ byte |= 5 << 0; /* mode 5 */
+ printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0));
+ pci_write_config8(ide_dev, 0x56, byte);
+}
+
+/**
+ * @brief Detect the ADT7475 device
+ *
+ * @param
+ */
+
+static const char * adt7475_detect( void ) {
+
+ int vendid, devid, devid2;
+ const char *name = NULL;
+
+ vendid = adt7475_read_byte(REG_VENDID);
+ devid2 = adt7475_read_byte(REG_DEVID2);
+ if (vendid != 0x41 || /* Analog Devices */
+ (devid2 & 0xf8) != 0x68) {
+ return name;
+ }
+
+ devid = adt7475_read_byte(REG_DEVID);
+ if (devid == 0x73)
+ name = "adt7473";
+ else if (devid == 0x75 && adt7475_address == 0x2e)
+ name = "adt7475";
+ else if (devid == 0x76)
+ name = "adt7476";
+ else if ((devid2 & 0xfc) == 0x6c)
+ name = "adt7490";
+
+ return name;
+}
+
+// thermal control defaults
+const struct fan_control cpu_fan_control_defaults = {
+ .enable = 0, // disable by default
+ .polarity = 0, // high by default
+ .t_min = 3, // default = 45°C
+ .t_max = 7, // 65°C
+ .pwm_min = 1, // default dutycycle = 30%
+ .pwm_max = 13, // 90%
+};
+const struct fan_control case_fan_control_defaults = {
+ .enable = 0, // disable by default
+ .polarity = 0, // high by default
+ .t_min = 2, // default = 40°C
+ .t_max = 8, // 70°C
+ .pwm_min = 0, // default dutycycle = 25%
+ .pwm_max = 13, // 90%
+};
+
+static void pm_init( void )
+{
+ u16 word;
+ u8 byte;
+ device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to tristate */
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* set GPM5 to not wake from s5 */
+ byte = pm_ioread(0x77);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x77, byte);
+}
+
+ /**
+ * @brief Setup thermal config on SINA Mainboard
+ *
+ * @param
+ */
+
+static void set_thermal_config(void)
+{
+ u8 byte, byte2;
+ u8 cpu_pwm_conf, case_pwm_conf;
+ device_t sm_dev;
+ struct fan_control cpu_fan_control, case_fan_control;
+ const char *name = NULL;
+
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
+
+ if( (name = adt7475_detect()) == NULL ) {
+ printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
+ return;
+ }
+ printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
+
+ cpu_fan_control = cpu_fan_control_defaults;
+ case_fan_control = case_fan_control_defaults;
+
+ if( get_option(&byte, "cpu_fan_control") == -4 ) {
+ printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__);
+ } else {
+ // get all the options needed
+ if( get_option(&byte, "cpu_fan_control") == 0 )
+ cpu_fan_control.enable = byte ? 1 : 0;
+
+ get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
+ get_option(&cpu_fan_control.t_min, "cpu_t_min");
+ get_option(&cpu_fan_control.t_max, "cpu_t_max");
+ get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min");
+ get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
+
+ if( get_option(&byte, "chassis_fan_control") == 0)
+ case_fan_control.enable = byte ? 1 : 0;
+ get_option(&case_fan_control.polarity, "chassis_fan_polarity");
+ get_option(&case_fan_control.t_min, "chassis_t_min");
+ get_option(&case_fan_control.t_max, "chassis_t_max");
+ get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
+ get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
+
+ }
+
+ printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
+ printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high");
+
+ printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
+ cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
+
+ printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
+ cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
+
+ printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
+ cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
+
+ printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
+ cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
+
+ cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
+ printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
+ cpu_fan_control.t_range <<= 4;
+ cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
+
+ printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
+ printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
+
+ printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
+ case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
+
+ printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
+ case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
+
+ printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
+ case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
+
+ printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
+ case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
+
+ case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
+ printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
+ case_fan_control.t_range <<= 4;
+ case_fan_control.t_range |= (4 << 0); // 35.3Hz
+
+ cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
+ case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
+ cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5); // manual control
+ case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
+
+ /* set adt7475 */
+
+ adt7475_write_byte(REG_CONFIG1, 0x04); // clear register, bit 2 is read only
+
+ /* Config Register 6: */
+ adt7475_write_byte(REG_CONFIG6, 0x00);
+ /* Config Register 7 */
+ adt7475_write_byte(REG_CONFIG7, 0x00);
+
+ /* Config Register 5: */
+ /* set Offset 64 format, enable THERM on Remote 1& Local */
+ adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);
+ /* No offset for remote 1 */
+ adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
+ /* No offset for local */
+ adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
+ /* No offset for remote 2 */
+ adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
+
+ /* remote 1 low temp limit */
+ adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
+ /* remote 1 High temp limit (90C) */
+ adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
+
+ /* local Low Temp Limit */
+ adt7475_write_byte(TEMP_MIN_REG(1), 0x00);
+ /* local High Limit (90C) */
+ adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
+
+ /* remote 1 therm temp limit (95C) */
+ adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
+ /* local therm temp limit (95C) */
+ adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
+
+ /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */
+ adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
+ /* PWM 3 configuration register Case fan controlled by ADTxxxx temp */
+ adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
+
+ if( cpu_fan_control.enable ) {
+ /* PWM 1 minimum duty cycle (37%) */
+ adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min);
+ /* PWM 1 Maximum duty cycle (100%) */
+ adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max);
+ /* Remote 1 temperature Tmin (32C) */
+ adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min);
+ /* remote 1 Trange (53C ramp range) */
+ adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range);
+ } else {
+ adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
+ }
+
+ if( case_fan_control.enable ) {
+ /* PWM 2 minimum duty cycle (37%) */
+ adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
+ /* PWM 2 Maximum Duty Cycle (100%) */
+ adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max);
+ /* local temperature Tmin (32C) */
+ adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min);
+ /* local Trange (53C ramp range) */
+ adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange
+ adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq
+ } else {
+ adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max);
+ }
+
+ /* Config Register 3 - enable smbalert & therm */
+ adt7475_write_byte(0x78, 0x03);
+ /* Config Register 4 - enable therm output */
+ adt7475_write_byte(0x7d, 0x09);
+ /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
+ adt7475_write_byte(0x75, 0x2e);
+
+ /* Config Register 1 Set Start bit */
+ adt7475_write_byte(0x40, 0x05);
+
+ /* Read status register to clear any old errors */
+ byte2 = adt7475_read_byte(0x42);
+ byte = adt7475_read_byte(0x41);
+
+ printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n",
+ byte2, byte);
+
+}
+
+ /**
+ * @brief
+ *
+ * @param
+ */
+
+static void patch_mmio_nonposted( void )
+{
+ unsigned reg, index;
+ resource_t rbase, rend;
+ u32 base, limit;
+ struct resource *resource;
+ device_t dev;
+ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
+
+ printk(BIOS_DEBUG,"%s ...\n", __func__);
+
+ dev = dev_find_slot(1, PCI_DEVFN(5,0));
+ // the uma frame buffer
+ index = 0x10;
+ resource = probe_resource(dev, index);
+ if( resource ) {
+ // fixup resource nonposted in k8 mmio
+ /* Get the base address */
+ rbase = (resource->base >> 8) & ~(0xff);
+ /* Get the limit (rounded up) */
+ rend = (resource_end(resource) >> 8) & ~(0xff);
+
+ printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
+
+ for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+ base = pci_read_config32(k8_f1,reg);
+ limit = pci_read_config32(k8_f1,reg+4);
+ printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
+ if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
+ limit |= (1 << 7);
+ printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
+ pci_write_config32(k8_f1, reg+4, limit);
+ break;
+ }
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+}
+
+ /**
+ * @brief
+ *
+ * @param
+ */
+
+struct {
+ unsigned int bus;
+ unsigned int devfn;
+} slot[] = {
+ {0, PCI_DEVFN(0,0)},
+ {0, PCI_DEVFN(18,0)},
+ {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)},
+ {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)},
+ {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
+ {255,0},
+};
+
+
+unsigned int plx_present = 0;
+
+static void update_subsystemid( device_t dev )
+{
+ int i;
+
+ dev->subsystem_vendor = 0x110a;
+ if( plx_present ){
+ dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
+ } else {
+ dev->subsystem_device = 0x4077; // U1P0 = 0x4077
+ }
+ printk(BIOS_INFO, "%s [%x/%x]\n", dev->chip_ops->name, dev->subsystem_vendor, dev->subsystem_device );
+ for( i=0; slot[i].bus < 255; i++) {
+ device_t d;
+ d = dev_find_slot(slot[i].bus,slot[i].devfn);
+ if( d ) {
+ printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
+ d->subsystem_device = dev->subsystem_device;
+ }
+ }
+}
+
+ /**
+ * @brief
+ *
+ * @param
+ */
+
+static void detect_hw_variant( device_t dev )
+{
+
+ device_t nb_dev =0, dev2 = 0;
+ struct southbridge_amd_rs690_config *cfg;
+ u32 lc_state, id = 0;
+
+ printk(BIOS_INFO, "Scan for PLX device ...\n");
+ nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (!nb_dev) {
+ die("CAN NOT FIND RS690 DEVICE, HALT!\n");
+ /* NOT REACHED */
+ }
+
+ dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
+ if (!dev2) {
+ die("CAN NOT FIND GFX DEVICE 2, HALT!\n");
+ /* NOT REACHED */
+ }
+ PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2
+
+ mdelay(40);
+ lc_state = nbpcie_p_read_index(dev2, 0xa5); /* lc_state */
+ printk(BIOS_DEBUG, "lc current state=%x\n", lc_state);
+ /* LC_CURRENT_STATE = bit0-5 */
+ switch( lc_state & 0x3f ){
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n");
+ break;
+ case 0x07:
+ case 0x10:
+ {
+ struct device dummy;
+ u32 pci_primary_bus, buses;
+ u16 secondary, subordinate;
+
+ printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));
+ // save the existing primary/secondary/subordinate bus number configuration.
+ secondary = dev2->bus->secondary;
+ subordinate = dev2->bus->subordinate;
+ buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
+
+ // Configure the bus numbers for this bridge
+ // bus number 1 is for internal gfx device, so we start with busnumber 2
+
+ buses &= 0xff000000;
+ buses |= ((2 << 8) | (0xff << 16));
+ // setup the buses in device 2
+ pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
+
+ // fake a device descriptor for a device behind device 2
+ dummy.bus = dev2->bus;
+ dummy.bus->secondary = (buses >> 8) & 0xff;
+ dummy.bus->subordinate = (buses >> 16) & 0xff;
+ dummy.path.type = DEVICE_PATH_PCI;
+ dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0
+
+ id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+ /* Have we found something?
+ * Some broken boards return 0 if a slot is empty, but
+ * the expected answer is 0xffffffff
+ */
+ if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
+ printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
+ } else {
+ printk(BIOS_DEBUG, "found device [%x]\n", id);
+ }
+ // restore changes made for device 2
+ dev2->bus->secondary = secondary;
+ dev2->bus->secondary = subordinate;
+ pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus);
+ }
+ break;
+ default:
+ break;
+ }
+
+ plx_present = 0;
+ if( id == PLX_VIDDID ){
+ printk(BIOS_INFO, "found PLX device\n");
+ plx_present = 1;
+ cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
+ if( cfg->gfx_tmds ) {
+ printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
+ cfg->gfx_tmds = 0;
+ cfg->gfx_link_width = 4;
+ }
+ return;
+ }
+}
+
+static void smm_lock( void )
+{
+ /* LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69,
+ D_LCK | G_SMRAME | A_BASE_SEG);
+}
+
+ /**
+ * @brief Init
+ *
+ * @param the root device
+ */
+
+static void init(device_t dev)
+{
+#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ INT15_function_extensions int15_func;
+#endif
+
+ printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
+ dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
+
+#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
+ int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
+ int15_func.regs.func05_TV_standard = TV_MODE_NO;
+ install_INT15_function_extensions(&int15_func);
+#endif
+ set_thermal_config();
+ pm_init();
+ cable_detect();
+ patch_mmio_nonposted();
+ smm_lock();
+}
+
+/*************************************************
+* enable the dedicated function in sina board.
+* This function called early than rs690_enable.
+*************************************************/
+static void enable_dev(device_t dev)
+{
+
+ printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
+ dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+
+ detect_hw_variant(dev);
+ update_subsystemid(dev);
+
+ dev->ops->init = init; // rest of mainboard init later
+}
+
+ /**
+ * @brief
+ *
+ * @param
+ */
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ device_t dev;
+ struct resource *res;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ res = probe_resource(dev, 0x1C);
+ if( res ) {
+ printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+ }
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER)
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c b/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c
deleted file mode 100644
index 9e7b1f2..0000000
--- a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Soyo SY-6BA+ III Mainboard")
-};
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/ramstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/ramstage.c
new file mode 100644
index 0000000..9e7b1f2
--- /dev/null
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Soyo SY-6BA+ III Mainboard")
+};
diff --git a/src/mainboard/sunw/ultra40/mainboard.c b/src/mainboard/sunw/ultra40/mainboard.c
deleted file mode 100644
index d46ea38..0000000
--- a/src/mainboard/sunw/ultra40/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Sun Ultra 40 Mainboard")
-};
-
diff --git a/src/mainboard/sunw/ultra40/ramstage.c b/src/mainboard/sunw/ultra40/ramstage.c
new file mode 100644
index 0000000..d46ea38
--- /dev/null
+++ b/src/mainboard/sunw/ultra40/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Sun Ultra 40 Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/h8dme/mainboard.c b/src/mainboard/supermicro/h8dme/mainboard.c
deleted file mode 100644
index c092c71..0000000
--- a/src/mainboard/supermicro/h8dme/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 Advanced Micro Devices
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro H8DME Mainboard")
-};
diff --git a/src/mainboard/supermicro/h8dme/ramstage.c b/src/mainboard/supermicro/h8dme/ramstage.c
new file mode 100644
index 0000000..c092c71
--- /dev/null
+++ b/src/mainboard/supermicro/h8dme/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 Advanced Micro Devices
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro H8DME Mainboard")
+};
diff --git a/src/mainboard/supermicro/h8dmr/mainboard.c b/src/mainboard/supermicro/h8dmr/mainboard.c
deleted file mode 100644
index 45536af..0000000
--- a/src/mainboard/supermicro/h8dmr/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro H8DMR Mainboard")
-};
diff --git a/src/mainboard/supermicro/h8dmr/ramstage.c b/src/mainboard/supermicro/h8dmr/ramstage.c
new file mode 100644
index 0000000..45536af
--- /dev/null
+++ b/src/mainboard/supermicro/h8dmr/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro H8DMR Mainboard")
+};
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c b/src/mainboard/supermicro/h8dmr_fam10/mainboard.c
deleted file mode 100644
index 24736a9..0000000
--- a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)")
-};
diff --git a/src/mainboard/supermicro/h8dmr_fam10/ramstage.c b/src/mainboard/supermicro/h8dmr_fam10/ramstage.c
new file mode 100644
index 0000000..24736a9
--- /dev/null
+++ b/src/mainboard/supermicro/h8dmr_fam10/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)")
+};
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
deleted file mode 100644
index 1f02c73..0000000
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <NbPlatform.h>
-
-void set_pcie_dereset(void *nbconfig);
-void set_pcie_reset(void *nbconfig);
-
-/**
- *
- */
-void set_pcie_reset(void *nbconfig)
-{
-}
-
-/**
- * Mainboard specific RD890 CIMx callback
- * Release Resets to PCIe Links
- * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
- */
-void set_pcie_dereset(void *nbconfig)
-{
- //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
- u32 i;
- u32 val;
- u32 nb_addr;
-
- val = 0x00000007UL;
- AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
- for (i = 0; i < MAX_NB_COUNT; i ++) {
- nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
- LibNbPciIndexRMW(nb_addr,
- NB_HTIU_REGA8,
- AccessS3SaveWidth32,
- ~val,
- val,
- &(pConfig->Northbridges[i]));
- }
-}
-
-
-/*************************************************
- * enable the dedicated function in h8qgi board.
- *************************************************/
-static void h8qgi_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-}
-
-#if CONFIG_HAVE_MAINBOARD_RESOURCES
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-#endif
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
- .enable_dev = h8qgi_enable,
-};
diff --git a/src/mainboard/supermicro/h8qgi/ramstage.c b/src/mainboard/supermicro/h8qgi/ramstage.c
new file mode 100644
index 0000000..1f02c73
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/ramstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <NbPlatform.h>
+
+void set_pcie_dereset(void *nbconfig);
+void set_pcie_reset(void *nbconfig);
+
+/**
+ *
+ */
+void set_pcie_reset(void *nbconfig)
+{
+}
+
+/**
+ * Mainboard specific RD890 CIMx callback
+ * Release Resets to PCIe Links
+ * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
+ */
+void set_pcie_dereset(void *nbconfig)
+{
+ //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+ u32 i;
+ u32 val;
+ u32 nb_addr;
+
+ val = 0x00000007UL;
+ AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
+ for (i = 0; i < MAX_NB_COUNT; i ++) {
+ nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
+ LibNbPciIndexRMW(nb_addr,
+ NB_HTIU_REGA8,
+ AccessS3SaveWidth32,
+ ~val,
+ val,
+ &(pConfig->Northbridges[i]));
+ }
+}
+
+
+/*************************************************
+ * enable the dedicated function in h8qgi board.
+ *************************************************/
+static void h8qgi_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+#endif
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = h8qgi_enable,
+};
diff --git a/src/mainboard/supermicro/h8qme_fam10/mainboard.c b/src/mainboard/supermicro/h8qme_fam10/mainboard.c
deleted file mode 100644
index 647f623..0000000
--- a/src/mainboard/supermicro/h8qme_fam10/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
-};
diff --git a/src/mainboard/supermicro/h8qme_fam10/ramstage.c b/src/mainboard/supermicro/h8qme_fam10/ramstage.c
new file mode 100644
index 0000000..647f623
--- /dev/null
+++ b/src/mainboard/supermicro/h8qme_fam10/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
+};
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
deleted file mode 100644
index e5a58fe..0000000
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sr5650/cmn.h>
-
-
-void set_pcie_reset(void);
-void set_pcie_dereset(void);
-u8 is_dev3_present(void);
-
-/* 780 board use this function*/
-u8 is_dev3_present(void)
-{
- return 0;
-}
-
-/*
- * TODO: Add the routine info of each PCIE_RESET_L.
- * TODO: Add the reset of each PCIE_RESET_L.
- * PCIE_RESET_GPIO1 -> Slot 0
- * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709
- * PCIE_RESET_GPIO3 -> TMS
- * PCIE_RESET_GPIO4 -> Slot 1
- * PCIE_RESET_GPIO5 -> Slot 2
- ***/
-void set_pcie_reset(void)
-{
- device_t pcie_core_dev;
-
- pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
- set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
-}
-
-void set_pcie_dereset(void)
-{
- device_t pcie_core_dev;
-
- pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
- set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
-}
-
-/*************************************************
-* enable the dedicated function in h8scm board.
-* This function called early than sr5650_enable.
-*************************************************/
-static void h8scm_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
-
- msr_t msr, msr2;
-
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk
- (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
- set_pcie_dereset();
- /* get_ide_dma66(); */
-}
-
-#if CONFIG_HAVE_MAINBOARD_RESOURCES
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-#endif
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD H8SCM Mainboard")
- .enable_dev = h8scm_enable,
-};
diff --git a/src/mainboard/supermicro/h8scm_fam10/ramstage.c b/src/mainboard/supermicro/h8scm_fam10/ramstage.c
new file mode 100644
index 0000000..e5a58fe
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm_fam10/ramstage.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/sr5650/cmn.h>
+
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+u8 is_dev3_present(void);
+
+/* 780 board use this function*/
+u8 is_dev3_present(void)
+{
+ return 0;
+}
+
+/*
+ * TODO: Add the routine info of each PCIE_RESET_L.
+ * TODO: Add the reset of each PCIE_RESET_L.
+ * PCIE_RESET_GPIO1 -> Slot 0
+ * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709
+ * PCIE_RESET_GPIO3 -> TMS
+ * PCIE_RESET_GPIO4 -> Slot 1
+ * PCIE_RESET_GPIO5 -> Slot 2
+ ***/
+void set_pcie_reset(void)
+{
+ device_t pcie_core_dev;
+
+ pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
+ set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
+}
+
+void set_pcie_dereset(void)
+{
+ device_t pcie_core_dev;
+
+ pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
+ set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
+}
+
+/*************************************************
+* enable the dedicated function in h8scm board.
+* This function called early than sr5650_enable.
+*************************************************/
+static void h8scm_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
+
+ msr_t msr, msr2;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk
+ (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk
+ (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ set_pcie_dereset();
+ /* get_ide_dma66(); */
+}
+
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+#endif
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AMD H8SCM Mainboard")
+ .enable_dev = h8scm_enable,
+};
diff --git a/src/mainboard/supermicro/x6dai_g/mainboard.c b/src/mainboard/supermicro/x6dai_g/mainboard.c
deleted file mode 100644
index d9b4bc4..0000000
--- a/src/mainboard/supermicro/x6dai_g/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro X6DAi-G Mainboard")
-};
-
diff --git a/src/mainboard/supermicro/x6dai_g/ramstage.c b/src/mainboard/supermicro/x6dai_g/ramstage.c
new file mode 100644
index 0000000..d9b4bc4
--- /dev/null
+++ b/src/mainboard/supermicro/x6dai_g/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro X6DAi-G Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/x6dhe_g/mainboard.c b/src/mainboard/supermicro/x6dhe_g/mainboard.c
deleted file mode 100644
index c09c95a..0000000
--- a/src/mainboard/supermicro/x6dhe_g/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro X6DHE-G Mainboard")
-};
-
diff --git a/src/mainboard/supermicro/x6dhe_g/ramstage.c b/src/mainboard/supermicro/x6dhe_g/ramstage.c
new file mode 100644
index 0000000..c09c95a
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhe_g/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro X6DHE-G Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/x6dhe_g2/mainboard.c b/src/mainboard/supermicro/x6dhe_g2/mainboard.c
deleted file mode 100644
index c20a842..0000000
--- a/src/mainboard/supermicro/x6dhe_g2/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro X6DHE-G2 Mainboard")
-};
-
diff --git a/src/mainboard/supermicro/x6dhe_g2/ramstage.c b/src/mainboard/supermicro/x6dhe_g2/ramstage.c
new file mode 100644
index 0000000..c20a842
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhe_g2/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro X6DHE-G2 Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/x6dhr_ig/mainboard.c b/src/mainboard/supermicro/x6dhr_ig/mainboard.c
deleted file mode 100644
index 3875fe0..0000000
--- a/src/mainboard/supermicro/x6dhr_ig/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro X6DHR-iG Mainboard")
-};
-
diff --git a/src/mainboard/supermicro/x6dhr_ig/ramstage.c b/src/mainboard/supermicro/x6dhr_ig/ramstage.c
new file mode 100644
index 0000000..3875fe0
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhr_ig/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro X6DHR-iG Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c
deleted file mode 100644
index 981aee8..0000000
--- a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Supermicro X6DHR-iG2 Mainboard")
-};
-
diff --git a/src/mainboard/supermicro/x6dhr_ig2/ramstage.c b/src/mainboard/supermicro/x6dhr_ig2/ramstage.c
new file mode 100644
index 0000000..981aee8
--- /dev/null
+++ b/src/mainboard/supermicro/x6dhr_ig2/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Supermicro X6DHR-iG2 Mainboard")
+};
+
diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c
deleted file mode 100644
index 618eca9..0000000
--- a/src/mainboard/supermicro/x7db8/mainboard.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <delay.h>
-#include <arch/coreboot_tables.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-
-static void mainboard_enable(device_t dev)
-{
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
- .enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/supermicro/x7db8/ramstage.c b/src/mainboard/supermicro/x7db8/ramstage.c
new file mode 100644
index 0000000..618eca9
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/ramstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <delay.h>
+#include <arch/coreboot_tables.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void mainboard_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
deleted file mode 100644
index b87058c..0000000
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include "tn_post_code.h"
-#include "vgabios.h"
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-
-/* Video BIOS Function Extensions Specification
- */
-//Callback Sub-Function 00h - Get LCD Panel ID
-#define LCD_PANEL_ID_NO 0x00 /* No LCD */
-#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
-#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
-#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
-#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
-#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
-#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
-//Callback Sub-Function 05h – Select Boot-up TV Standard
-#define TV_MODE_00 0x00 /* NTSC */
-#define TV_MODE_01 0x01 /* PAL */
-#define TV_MODE_02 0x02 /* PALM */
-#define TV_MODE_03 0x03 /* PAL60 */
-#define TV_MODE_04 0x04 /* NTSCJ */
-#define TV_MODE_05 0x05 /* PALCN */
-#define TV_MODE_06 0x06 /* PALN */
-#define TV_MODE_09 0x09 /* SCART-RGB */
-#define TV_MODE_NO 0xff /* No TV Support */
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA SIO_BASE+1
-
-/* Global configuration registers. */
-#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
-#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
-#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-
-#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
-#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
- LDN the register belongs to, before you can access the register. */
-static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
-{
- outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
-{
- /* Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x2e. */
- /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
- /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
- outb(0x87, IT8712F_CONFIGURATION_PORT);
- outb(0x01, IT8712F_CONFIGURATION_PORT);
- outb(0x55, IT8712F_CONFIGURATION_PORT);
- outb(0x55, IT8712F_CONFIGURATION_PORT);
-}
-
-static void it8712f_exit_conf(void)
-{
- /* Exit the configuration state (MB PnP mode). */
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
-}
-
-/* set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/* Mainboard specific GPIO setup. */
-static void mb_gpio_init(u16 *iobase)
-{
- /* Init Super I/O GPIOs. */
- it8712f_enter_conf();
- outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
- outb(IT8712F_GPIO, SIO_DATA);
- outb(0x62, SIO_INDEX);
- outb((*iobase >> 8), SIO_DATA);
- outb(0x63, SIO_INDEX);
- outb((*iobase & 0xff), SIO_DATA);
- it8712f_exit_conf();
-}
-
-/* The LCD's panel id seletion. */
-static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
-{
- switch (num_id) {
- case 0x1:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
- break;
- case 0x2:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
- break;
- case 0x3:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
- break;
- case 0x4:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
- break;
- case 0x5:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
- break;
- case 0x6:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
- break;
- default:
- vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
- break;
- }
-}
-
-/*************************************************
-* enable the dedicated function in tim5690 board.
-* This function called early than rs690_enable.
-*************************************************/
-static void tim5690_enable(device_t dev)
-{
- rs690_vbios_regs vbios_regs;
- u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
- u8 port2;
-
- printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
-
- mb_gpio_init(&gpio_base);
-
- /* The LCD's panel id seletion by switch. */
- port2 = inb(gpio_base+1);
- lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
-
- /* No support TV */
- vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
- vgabios_init(&vbios_regs);
-
- set_thermal_config();
-}
-
-void mainboard_post(u8 value)
-{
- switch (value) {
- case POST_ENTER_ELF_BOOT:
- technexion_post_code(LED_MESSAGE_FINISH);
- break;
- }
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("TechNexion TIM-5690 Mainboard")
- .enable_dev = tim5690_enable,
-};
diff --git a/src/mainboard/technexion/tim5690/ramstage.c b/src/mainboard/technexion/tim5690/ramstage.c
new file mode 100644
index 0000000..b87058c
--- /dev/null
+++ b/src/mainboard/technexion/tim5690/ramstage.c
@@ -0,0 +1,257 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb600/sb600.h>
+#include <superio/ite/it8712f/it8712f.h>
+#include "tn_post_code.h"
+#include "vgabios.h"
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define SMBUS_IO_BASE 0x1000
+
+
+/* Video BIOS Function Extensions Specification
+ */
+//Callback Sub-Function 00h - Get LCD Panel ID
+#define LCD_PANEL_ID_NO 0x00 /* No LCD */
+#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */
+#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */
+#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */
+#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */
+#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */
+#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */
+//Callback Sub-Function 05h – Select Boot-up TV Standard
+#define TV_MODE_00 0x00 /* NTSC */
+#define TV_MODE_01 0x01 /* PAL */
+#define TV_MODE_02 0x02 /* PALM */
+#define TV_MODE_03 0x03 /* PAL60 */
+#define TV_MODE_04 0x04 /* NTSCJ */
+#define TV_MODE_05 0x05 /* PALCN */
+#define TV_MODE_06 0x06 /* PALN */
+#define TV_MODE_09 0x09 /* SCART-RGB */
+#define TV_MODE_NO 0xff /* No TV Support */
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA SIO_BASE+1
+
+/* Global configuration registers. */
+#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
+#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
+
+#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
+#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ LDN the register belongs to, before you can access the register. */
+static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+{
+ outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+static void it8712f_enter_conf(void)
+{
+ /* Enter the configuration state (MB PnP mode). */
+
+ /* Perform MB PnP setup to put the SIO chip at 0x2e. */
+ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+ outb(0x87, IT8712F_CONFIGURATION_PORT);
+ outb(0x01, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+}
+
+static void it8712f_exit_conf(void)
+{
+ /* Exit the configuration state (MB PnP mode). */
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+/* set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb600 settings for thermal config */
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/* Mainboard specific GPIO setup. */
+static void mb_gpio_init(u16 *iobase)
+{
+ /* Init Super I/O GPIOs. */
+ it8712f_enter_conf();
+ outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX);
+ outb(IT8712F_GPIO, SIO_DATA);
+ outb(0x62, SIO_INDEX);
+ outb((*iobase >> 8), SIO_DATA);
+ outb(0x63, SIO_INDEX);
+ outb((*iobase & 0xff), SIO_DATA);
+ it8712f_exit_conf();
+}
+
+/* The LCD's panel id seletion. */
+static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
+{
+ switch (num_id) {
+ case 0x1:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01;
+ break;
+ case 0x2:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02;
+ break;
+ case 0x3:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03;
+ break;
+ case 0x4:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04;
+ break;
+ case 0x5:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05;
+ break;
+ case 0x6:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06;
+ break;
+ default:
+ vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO;
+ break;
+ }
+}
+
+/*************************************************
+* enable the dedicated function in tim5690 board.
+* This function called early than rs690_enable.
+*************************************************/
+static void tim5690_enable(device_t dev)
+{
+ rs690_vbios_regs vbios_regs;
+ u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
+ u8 port2;
+
+ printk(BIOS_INFO, "Mainboard tim5690 Enable. dev=0x%p\n", dev);
+
+ mb_gpio_init(&gpio_base);
+
+ /* The LCD's panel id seletion by switch. */
+ port2 = inb(gpio_base+1);
+ lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
+
+ /* No support TV */
+ vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
+ vgabios_init(&vbios_regs);
+
+ set_thermal_config();
+}
+
+void mainboard_post(u8 value)
+{
+ switch (value) {
+ case POST_ENTER_ELF_BOOT:
+ technexion_post_code(LED_MESSAGE_FINISH);
+ break;
+ }
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("TechNexion TIM-5690 Mainboard")
+ .enable_dev = tim5690_enable,
+};
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
deleted file mode 100644
index 298132b..0000000
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <boot/tables.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb600/sb600.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS 0x0C /* Alert Response Address */
-#define SMBUS_IO_BASE 0x1000
-
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-#define ADT7461_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
- do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
- do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-
-
-
-/***************************************************
-* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
-* 10/100/1000 chips on board.
-* Both of their pin PERSTn pins are connected to GPIO 5 of the
-* SB600 southbridge.
-****************************************************/
-static void enable_onboard_nic(void)
-{
-
- u8 byte;
- device_t sm_dev;
-
- printk(BIOS_INFO, "enable_onboard_nic.\n");
-
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- byte = pci_read_config8(sm_dev, 0x9a);
- byte |= ( 1 << 7);
- pci_write_config8(sm_dev, 0x9a, byte);
-
- byte=pm_ioread(0x59);
- byte &= ~( 1<< 5);
- pm_iowrite(0x59,byte);
-
- byte = pci_read_config8(sm_dev, 0xA8);
-
- byte |= (1 << 1); //set bit 1 to high
- pci_write_config8(sm_dev, 0xA8, byte);
-}
-
-/* set thermal config
- */
-static void set_thermal_config(void)
-{
- u8 byte;
- u16 word;
- device_t sm_dev;
-
- /* set ADT 7461 */
- ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
- ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
- ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
- ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
-
- ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
- ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
-
- byte = ADT7461_read_byte(0x02); /* read status register to clear it */
- ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
- printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
-
- /* sb600 settings for thermal config */
- /* set SB600 GPIO 64 to GPIO with pull-up */
- byte = pm2_ioread(0x42);
- byte &= 0x3f;
- pm2_iowrite(0x42, byte);
-
- /* set GPIO 64 to input */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word = pci_read_config16(sm_dev, 0x56);
- word |= 1 << 7;
- pci_write_config16(sm_dev, 0x56, word);
-
- /* set GPIO 64 internal pull-up */
- byte = pm2_ioread(0xf0);
- byte &= 0xee;
- pm2_iowrite(0xf0, byte);
-
- /* set Talert to be active low */
- byte = pm_ioread(0x67);
- byte &= ~(1 << 5);
- pm_iowrite(0x67, byte);
-
- /* set Talert to generate ACPI event */
- byte = pm_ioread(0x3c);
- byte &= 0xf3;
- pm_iowrite(0x3c, byte);
-
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
-}
-
-/*************************************************
-* enable the dedicated function in tim8690 board.
-* This function called early than rs690_enable.
-*************************************************/
-static void tim8690_enable(device_t dev)
-{
- printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
-
- enable_onboard_nic();
- set_thermal_config();
-}
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("TechNexion TIM-8690 Mainboard")
- .enable_dev = tim8690_enable,
-};
diff --git a/src/mainboard/technexion/tim8690/ramstage.c b/src/mainboard/technexion/tim8690/ramstage.c
new file mode 100644
index 0000000..298132b
--- /dev/null
+++ b/src/mainboard/technexion/tim8690/ramstage.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb600/sb600.h>
+
+#define ADT7461_ADDRESS 0x4C
+#define ARA_ADDRESS 0x0C /* Alert Response Address */
+#define SMBUS_IO_BASE 0x1000
+
+extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
+ u8 val);
+#define ADT7461_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
+#define ARA_read_byte(address) \
+ do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
+#define ADT7461_write_byte(address, val) \
+ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
+
+
+
+
+/***************************************************
+* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
+* 10/100/1000 chips on board.
+* Both of their pin PERSTn pins are connected to GPIO 5 of the
+* SB600 southbridge.
+****************************************************/
+static void enable_onboard_nic(void)
+{
+
+ u8 byte;
+ device_t sm_dev;
+
+ printk(BIOS_INFO, "enable_onboard_nic.\n");
+
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+ byte = pci_read_config8(sm_dev, 0x9a);
+ byte |= ( 1 << 7);
+ pci_write_config8(sm_dev, 0x9a, byte);
+
+ byte=pm_ioread(0x59);
+ byte &= ~( 1<< 5);
+ pm_iowrite(0x59,byte);
+
+ byte = pci_read_config8(sm_dev, 0xA8);
+
+ byte |= (1 << 1); //set bit 1 to high
+ pci_write_config8(sm_dev, 0xA8, byte);
+}
+
+/* set thermal config
+ */
+static void set_thermal_config(void)
+{
+ u8 byte;
+ u16 word;
+ device_t sm_dev;
+
+ /* set ADT 7461 */
+ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
+ ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
+ ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
+ ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
+
+ ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
+ ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
+
+ byte = ADT7461_read_byte(0x02); /* read status register to clear it */
+ ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
+ printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
+
+ /* sb600 settings for thermal config */
+ /* set SB600 GPIO 64 to GPIO with pull-up */
+ byte = pm2_ioread(0x42);
+ byte &= 0x3f;
+ pm2_iowrite(0x42, byte);
+
+ /* set GPIO 64 to input */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ word = pci_read_config16(sm_dev, 0x56);
+ word |= 1 << 7;
+ pci_write_config16(sm_dev, 0x56, word);
+
+ /* set GPIO 64 internal pull-up */
+ byte = pm2_ioread(0xf0);
+ byte &= 0xee;
+ pm2_iowrite(0xf0, byte);
+
+ /* set Talert to be active low */
+ byte = pm_ioread(0x67);
+ byte &= ~(1 << 5);
+ pm_iowrite(0x67, byte);
+
+ /* set Talert to generate ACPI event */
+ byte = pm_ioread(0x3c);
+ byte &= 0xf3;
+ pm_iowrite(0x3c, byte);
+
+ /* THERMTRIP pin */
+ /* byte = pm_ioread(0x68);
+ * byte |= 1 << 3;
+ * pm_iowrite(0x68, byte);
+ *
+ * byte = pm_ioread(0x55);
+ * byte |= 1 << 0;
+ * pm_iowrite(0x55, byte);
+ *
+ * byte = pm_ioread(0x67);
+ * byte &= ~( 1 << 6);
+ * pm_iowrite(0x67, byte);
+ */
+}
+
+/*************************************************
+* enable the dedicated function in tim8690 board.
+* This function called early than rs690_enable.
+*************************************************/
+static void tim8690_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
+
+ enable_onboard_nic();
+ set_thermal_config();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("TechNexion TIM-8690 Mainboard")
+ .enable_dev = tim8690_enable,
+};
diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c
deleted file mode 100644
index 164b7e8..0000000
--- a/src/mainboard/technologic/ts5300/mainboard.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <cpu/amd/sc520.h>
-
-
-#if 0
-static void irqdump(void)
-{
- volatile unsigned char *irq;
- void *mmcr;
-
-
- int i;
- int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
- 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
- 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
- 0xd30, 0xd31, 0xd32, 0xd33,
- 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
- 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
- -1};
- mmcr = (void *) 0xfffef000;
-
- printk(BIOS_ERR, "mmcr is %p\n", mmcr);
- for(i = 0; irqlist[i] >= 0; i++) {
- irq = mmcr + irqlist[i];
- printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
- }
-
-}
-#endif
-
-/* TODO: finish up mmcr struct in sc520.h, and;
- - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
-*/
-static void enable_dev(struct device *dev) {
- volatile struct mmcr *mmcr = MMCRDEFAULT;
-
- /* currently, nothing in the device to use, so ignore it. */
- printk(BIOS_ERR, "Technologic Systems 5300 ENTER %s\n", __func__);
-
- /* from fuctory bios */
- /* NOTE: the following interrupt settings made interrupts work
- * for hard drive, and serial, but not for ethernet
- */
-
- printk(BIOS_ERR, "Setting up PIC\n");
- /* just do what they say and nobody gets hurt. */
- mmcr->pic.pcicr = 0 ;
- /* all ints to level */
- mmcr->pic.mpicmode = 0;
- mmcr->pic.sl1picmode = 0;
- mmcr->pic.sl2picmode = 0;
-
- mmcr->pic.intpinpol = 0x100;
-
- mmcr->pic.pit0map = 1;
- mmcr->pic.uart1map = 0x0c;
- mmcr->pic.uart2map = 0x0b;
- mmcr->pic.rtcmap = 0x03;
- mmcr->pic.ferrmap = 0x00;
- mmcr->pic.intpinpol = 0x100;
-
- mmcr->pic.gp0imap = 0x00;
- mmcr->pic.gp1imap = 0x02;
- mmcr->pic.gp2imap = 0x07;
- mmcr->pic.gp3imap = 0x05;
- mmcr->pic.gp4imap = 0x06;
- mmcr->pic.gp5imap = 0x0d;
- mmcr->pic.gp6imap = 0x15;
- mmcr->pic.gp7imap = 0x16;
- mmcr->pic.gp8imap = 0x3;
- mmcr->pic.gp9imap = 0x4;
- mmcr->pic.gp10imap = 0x9;
-
- // irqdump();
-
- printk(BIOS_ERR, "Setting up sysarb\n");
- mmcr->dbctl.dbctl = 0x01;
- mmcr->sysarb.ctl = 0x00;
- mmcr->sysarb.menb = 0x1f;
- mmcr->sysarb.prictl = 0x40000f0f;
-
- /* this is bios setting, depends on sysarb above */
- mmcr->hostbridge.ctl = 0x0;
- mmcr->hostbridge.tgtirqctl = 0x0;
- mmcr->hostbridge.tgtirqsta = 0xf00;
- mmcr->hostbridge.mstirqctl = 0x0;
- mmcr->hostbridge.mstirqsta = 0x708;
-
- printk(BIOS_ERR, "Setting up pio\n");
- /* pio */
- mmcr->pio.pfs15_0 = 0xffff;
- mmcr->pio.pfs31_16 = 0xffff;
- mmcr->pio.cspfs = 0xfe;
- mmcr->pio.clksel = 0x13;
- mmcr->pio.dsctl = 0x200;
- mmcr->pio.data15_0 = 0xde04;
- mmcr->pio.data31_16 = 0xef9f;
-
- printk(BIOS_ERR, "Setting up sysmap\n");
- /* system memory map */
- mmcr->sysmap.adddecctl = 0x04;
- mmcr->sysmap.wpvsta = 0x8006;
- mmcr->sysmap.par[1] = 0x340f0070;
- mmcr->sysmap.par[2] = 0x380701f0;
- mmcr->sysmap.par[3] = 0x3c0103f6;
- mmcr->sysmap.par[4] = 0x2c0f0300;
- mmcr->sysmap.par[5] = 0x447c00a0;
- mmcr->sysmap.par[6] = 0xe600000c;
- mmcr->sysmap.par[7] = 0x300046e8;
- mmcr->sysmap.par[8] = 0x500400d0;
- mmcr->sysmap.par[9] = 0x281f0140;
- mmcr->sysmap.par[13] = 0x8a07c940;
- mmcr->sysmap.par[15] = 0xee00400e;
-
- printk(BIOS_ERR, "Setting up gpctl\n");
- mmcr->gpctl.gpcsrt = 0x01;
- mmcr->gpctl.gpcspw = 0x09;
- mmcr->gpctl.gpcsoff = 0x01;
- mmcr->gpctl.gprdw = 0x07;
- mmcr->gpctl.gprdoff = 0x02;
- mmcr->gpctl.gpwrw = 0x07;
- mmcr->gpctl.gpwroff = 0x02;
-
- //mmcr->reset.sysinfo = 0xdf;
- //mmcr->reset.rescfg = 0x5;
- /* their IRQ table is wrong. Just hardwire it */
- //{
- // char pciints[4] = {15, 15, 15, 15};
- // pci_assign_irqs(0, 12, pciints);
- //}
- /* the assigned failed but we just noticed -- there is no
- * dma mapping, and selftest on e100 requires that dma work
- */
- mmcr->dmacontrol.extchanmapa = 0xf210;
- mmcr->dmacontrol.extchanmapb = 0xffff;
-
- printk(BIOS_ERR, "TS5300 EXIT %s\n", __func__);
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Technologic Systems TS-5300 Mainboard")
- .enable_dev = enable_dev
-};
-
diff --git a/src/mainboard/technologic/ts5300/ramstage.c b/src/mainboard/technologic/ts5300/ramstage.c
new file mode 100644
index 0000000..164b7e8
--- /dev/null
+++ b/src/mainboard/technologic/ts5300/ramstage.c
@@ -0,0 +1,148 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/amd/sc520.h>
+
+
+#if 0
+static void irqdump(void)
+{
+ volatile unsigned char *irq;
+ void *mmcr;
+
+
+ int i;
+ int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a,
+ 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c,
+ 0xd20, 0xd21, 0xd22, 0xd28, 0xd29,
+ 0xd30, 0xd31, 0xd32, 0xd33,
+ 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46,
+ 0xd50, 0xd51, 0xd52, 0xd53,0xd54, 0xd55, 0xd56, 0xd57,0xd58, 0xd59, 0xd5a,
+ -1};
+ mmcr = (void *) 0xfffef000;
+
+ printk(BIOS_ERR, "mmcr is %p\n", mmcr);
+ for(i = 0; irqlist[i] >= 0; i++) {
+ irq = mmcr + irqlist[i];
+ printk(BIOS_ERR, "0x%x register @%p is 0x%x\n", irqlist[i], irq, *irq);
+ }
+
+}
+#endif
+
+/* TODO: finish up mmcr struct in sc520.h, and;
+ - set ADDDECTL (now done in raminit.c in cpu/amd/sc520
+*/
+static void enable_dev(struct device *dev) {
+ volatile struct mmcr *mmcr = MMCRDEFAULT;
+
+ /* currently, nothing in the device to use, so ignore it. */
+ printk(BIOS_ERR, "Technologic Systems 5300 ENTER %s\n", __func__);
+
+ /* from fuctory bios */
+ /* NOTE: the following interrupt settings made interrupts work
+ * for hard drive, and serial, but not for ethernet
+ */
+
+ printk(BIOS_ERR, "Setting up PIC\n");
+ /* just do what they say and nobody gets hurt. */
+ mmcr->pic.pcicr = 0 ;
+ /* all ints to level */
+ mmcr->pic.mpicmode = 0;
+ mmcr->pic.sl1picmode = 0;
+ mmcr->pic.sl2picmode = 0;
+
+ mmcr->pic.intpinpol = 0x100;
+
+ mmcr->pic.pit0map = 1;
+ mmcr->pic.uart1map = 0x0c;
+ mmcr->pic.uart2map = 0x0b;
+ mmcr->pic.rtcmap = 0x03;
+ mmcr->pic.ferrmap = 0x00;
+ mmcr->pic.intpinpol = 0x100;
+
+ mmcr->pic.gp0imap = 0x00;
+ mmcr->pic.gp1imap = 0x02;
+ mmcr->pic.gp2imap = 0x07;
+ mmcr->pic.gp3imap = 0x05;
+ mmcr->pic.gp4imap = 0x06;
+ mmcr->pic.gp5imap = 0x0d;
+ mmcr->pic.gp6imap = 0x15;
+ mmcr->pic.gp7imap = 0x16;
+ mmcr->pic.gp8imap = 0x3;
+ mmcr->pic.gp9imap = 0x4;
+ mmcr->pic.gp10imap = 0x9;
+
+ // irqdump();
+
+ printk(BIOS_ERR, "Setting up sysarb\n");
+ mmcr->dbctl.dbctl = 0x01;
+ mmcr->sysarb.ctl = 0x00;
+ mmcr->sysarb.menb = 0x1f;
+ mmcr->sysarb.prictl = 0x40000f0f;
+
+ /* this is bios setting, depends on sysarb above */
+ mmcr->hostbridge.ctl = 0x0;
+ mmcr->hostbridge.tgtirqctl = 0x0;
+ mmcr->hostbridge.tgtirqsta = 0xf00;
+ mmcr->hostbridge.mstirqctl = 0x0;
+ mmcr->hostbridge.mstirqsta = 0x708;
+
+ printk(BIOS_ERR, "Setting up pio\n");
+ /* pio */
+ mmcr->pio.pfs15_0 = 0xffff;
+ mmcr->pio.pfs31_16 = 0xffff;
+ mmcr->pio.cspfs = 0xfe;
+ mmcr->pio.clksel = 0x13;
+ mmcr->pio.dsctl = 0x200;
+ mmcr->pio.data15_0 = 0xde04;
+ mmcr->pio.data31_16 = 0xef9f;
+
+ printk(BIOS_ERR, "Setting up sysmap\n");
+ /* system memory map */
+ mmcr->sysmap.adddecctl = 0x04;
+ mmcr->sysmap.wpvsta = 0x8006;
+ mmcr->sysmap.par[1] = 0x340f0070;
+ mmcr->sysmap.par[2] = 0x380701f0;
+ mmcr->sysmap.par[3] = 0x3c0103f6;
+ mmcr->sysmap.par[4] = 0x2c0f0300;
+ mmcr->sysmap.par[5] = 0x447c00a0;
+ mmcr->sysmap.par[6] = 0xe600000c;
+ mmcr->sysmap.par[7] = 0x300046e8;
+ mmcr->sysmap.par[8] = 0x500400d0;
+ mmcr->sysmap.par[9] = 0x281f0140;
+ mmcr->sysmap.par[13] = 0x8a07c940;
+ mmcr->sysmap.par[15] = 0xee00400e;
+
+ printk(BIOS_ERR, "Setting up gpctl\n");
+ mmcr->gpctl.gpcsrt = 0x01;
+ mmcr->gpctl.gpcspw = 0x09;
+ mmcr->gpctl.gpcsoff = 0x01;
+ mmcr->gpctl.gprdw = 0x07;
+ mmcr->gpctl.gprdoff = 0x02;
+ mmcr->gpctl.gpwrw = 0x07;
+ mmcr->gpctl.gpwroff = 0x02;
+
+ //mmcr->reset.sysinfo = 0xdf;
+ //mmcr->reset.rescfg = 0x5;
+ /* their IRQ table is wrong. Just hardwire it */
+ //{
+ // char pciints[4] = {15, 15, 15, 15};
+ // pci_assign_irqs(0, 12, pciints);
+ //}
+ /* the assigned failed but we just noticed -- there is no
+ * dma mapping, and selftest on e100 requires that dma work
+ */
+ mmcr->dmacontrol.extchanmapa = 0xf210;
+ mmcr->dmacontrol.extchanmapb = 0xffff;
+
+ printk(BIOS_ERR, "TS5300 EXIT %s\n", __func__);
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Technologic Systems TS-5300 Mainboard")
+ .enable_dev = enable_dev
+};
+
diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c
index b9b2f17..f5ec841 100644
--- a/src/mainboard/technologic/ts5300/romstage.c
+++ b/src/mainboard/technologic/ts5300/romstage.c
@@ -26,7 +26,7 @@ void setup_pars(void)
volatile unsigned long *par;
par = (unsigned long *) 0xfffef088;
- /* NOTE: Ron says, move this to mainboard.c */
+ /* NOTE: Ron says, move this to ramstage.c */
*par++ = 0x00000000;
*par++ = 0x340f0070;
*par++ = 0x380701f0;
diff --git a/src/mainboard/televideo/tc7020/mainboard.c b/src/mainboard/televideo/tc7020/mainboard.c
deleted file mode 100644
index ee41109..0000000
--- a/src/mainboard/televideo/tc7020/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Kenji Noguchi <tokyo246 at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("TeleVideo TC7020 Mainboard")
-};
-
diff --git a/src/mainboard/televideo/tc7020/ramstage.c b/src/mainboard/televideo/tc7020/ramstage.c
new file mode 100644
index 0000000..ee41109
--- /dev/null
+++ b/src/mainboard/televideo/tc7020/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Kenji Noguchi <tokyo246 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("TeleVideo TC7020 Mainboard")
+};
+
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
deleted file mode 100644
index ae5872d..0000000
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- * Copyright (C) 2010 Stefan Reinauer <stepan at openbios.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <boot/tables.h>
-#include <delay.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <arch/coreboot_tables.h>
-#include <arch/io.h>
-
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return 0;
-}
-
-// setting the bit disables the led.
-#define PARPORT_GPIO_LED_GREEN (1 << 0)
-#define PARPORT_GPIO_LED_ORANGE (1 << 1)
-#define PARPORT_GPIO_LED_RED (1 << 2)
-#define PARPORT_GPIO_IR_PORT (1 << 6)
-
-static u8 get_parport_gpio(void)
-{
- return inb(0x378);
-}
-
-static void set_parport_gpio(u8 gpios)
-{
- outb(gpios, 0x378);
-}
-
-static void parport_gpios(void)
-{
- u8 pp_gpios = get_parport_gpio();
-
- /* disable red led */
- pp_gpios |= PARPORT_GPIO_LED_RED;
- set_parport_gpio(pp_gpios);
-
- pp_gpios = get_parport_gpio();
-
- printk(BIOS_DEBUG, "IP1000 GPIOs:\n");
- printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios);
- printk(BIOS_DEBUG, " green led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on");
- printk(BIOS_DEBUG, " orange led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on");
- printk(BIOS_DEBUG, " red led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on");
- printk(BIOS_DEBUG, " IR port: %s\n",
- (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on");
-}
-
-static void flash_gpios(void)
-{
- u8 manufacturer_id = read8(0xffbc0000);
- u8 device_id = read8(0xffbc0001);
-
- if ((manufacturer_id == 0x20) &&
- ((device_id == 0x2c) || (device_id == 0x2d))) {
- printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
- (device_id==0x2c)?'4':'8');
- u8 fgpi = read8(0xffbc0100);
- printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
- (fgpi & (1 << 0)) ? 'X' : ' ',
- (fgpi & (1 << 1)) ? 'X' : ' ',
- (fgpi & (1 << 2)) ? 'X' : ' ',
- (fgpi & (1 << 3)) ? 'X' : ' ',
- (fgpi & (1 << 4)) ? 'X' : ' ');
- } else {
- printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n");
- }
-}
-
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-#define BOOT_DISPLAY_DEFAULT 0
-#define BOOT_DISPLAY_CRT (1 << 0)
-#define BOOT_DISPLAY_TV (1 << 1)
-#define BOOT_DISPLAY_EFP (1 << 2)
-#define BOOT_DISPLAY_LCD (1 << 3)
-#define BOOT_DISPLAY_CRT2 (1 << 4)
-#define BOOT_DISPLAY_TV2 (1 << 5)
-#define BOOT_DISPLAY_EFP2 (1 << 6)
-#define BOOT_DISPLAY_LCD2 (1 << 7)
-
- printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
- __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
- switch (M.x86.R_AX) {
- case 0x5f35: /* Boot Display */
- M.x86.R_AX = 0x005f; // Success
- //M.x86.R_CL = BOOT_DISPLAY_TV2;
- M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
- break;
- case 0x5f36: /* Boot TV Format Hook */
- printk(BIOS_DEBUG, "Boot TV Format Hook. TODO\n");
- /* Interrupt was not handled */
- return 0;
- case 0x5f31: /* Post Completion Hook */
- case 0x5f33: /* Hook After Mode Set */
- case 0x5f34: /* Set Panel Fitting Hook */
- case 0x5f38: /* Hook Before Mode Set */
- case 0x5f45: /* Hook Before VESA VBE/DDC */
- case 0x5f46: /* Hook Before VESA VBE/PM */
- case 0x5f47: /* Notif Display Switch Hook */
- case 0x5f65: /* Local Memory Initialization Hook */
- /* Interrupt was not handled */
- return 0;
- default:
- /* Interrupt was not handled */
- return 0;
- }
-
- /* Interrupt handled */
- return 1;
-}
-
-static void int15_install(void)
-{
- typedef int (* yabel_handleIntFunc)(void);
- extern yabel_handleIntFunc yabel_intFuncArray[256];
- yabel_intFuncArray[0x15] = int15_handler;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- parport_gpios();
- flash_gpios();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
- /* Install custom int15 handler for VGA OPROM */
- int15_install();
-#endif
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
- CHIP_NAME("THOMSON IP1000 Mainboard")
-};
diff --git a/src/mainboard/thomson/ip1000/ramstage.c b/src/mainboard/thomson/ip1000/ramstage.c
new file mode 100644
index 0000000..ae5872d
--- /dev/null
+++ b/src/mainboard/thomson/ip1000/ramstage.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
+ * Copyright (C) 2010 Stefan Reinauer <stepan at openbios.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <boot/tables.h>
+#include <delay.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <arch/coreboot_tables.h>
+#include <arch/io.h>
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+
+// setting the bit disables the led.
+#define PARPORT_GPIO_LED_GREEN (1 << 0)
+#define PARPORT_GPIO_LED_ORANGE (1 << 1)
+#define PARPORT_GPIO_LED_RED (1 << 2)
+#define PARPORT_GPIO_IR_PORT (1 << 6)
+
+static u8 get_parport_gpio(void)
+{
+ return inb(0x378);
+}
+
+static void set_parport_gpio(u8 gpios)
+{
+ outb(gpios, 0x378);
+}
+
+static void parport_gpios(void)
+{
+ u8 pp_gpios = get_parport_gpio();
+
+ /* disable red led */
+ pp_gpios |= PARPORT_GPIO_LED_RED;
+ set_parport_gpio(pp_gpios);
+
+ pp_gpios = get_parport_gpio();
+
+ printk(BIOS_DEBUG, "IP1000 GPIOs:\n");
+ printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios);
+ printk(BIOS_DEBUG, " green led: %s\n",
+ (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on");
+ printk(BIOS_DEBUG, " orange led: %s\n",
+ (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on");
+ printk(BIOS_DEBUG, " red led: %s\n",
+ (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on");
+ printk(BIOS_DEBUG, " IR port: %s\n",
+ (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on");
+}
+
+static void flash_gpios(void)
+{
+ u8 manufacturer_id = read8(0xffbc0000);
+ u8 device_id = read8(0xffbc0001);
+
+ if ((manufacturer_id == 0x20) &&
+ ((device_id == 0x2c) || (device_id == 0x2d))) {
+ printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
+ (device_id==0x2c)?'4':'8');
+ u8 fgpi = read8(0xffbc0100);
+ printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
+ (fgpi & (1 << 0)) ? 'X' : ' ',
+ (fgpi & (1 << 1)) ? 'X' : ' ',
+ (fgpi & (1 << 2)) ? 'X' : ' ',
+ (fgpi & (1 << 3)) ? 'X' : ' ',
+ (fgpi & (1 << 4)) ? 'X' : ' ');
+ } else {
+ printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n");
+ }
+}
+
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+#define BOOT_DISPLAY_DEFAULT 0
+#define BOOT_DISPLAY_CRT (1 << 0)
+#define BOOT_DISPLAY_TV (1 << 1)
+#define BOOT_DISPLAY_EFP (1 << 2)
+#define BOOT_DISPLAY_LCD (1 << 3)
+#define BOOT_DISPLAY_CRT2 (1 << 4)
+#define BOOT_DISPLAY_TV2 (1 << 5)
+#define BOOT_DISPLAY_EFP2 (1 << 6)
+#define BOOT_DISPLAY_LCD2 (1 << 7)
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f35: /* Boot Display */
+ M.x86.R_AX = 0x005f; // Success
+ //M.x86.R_CL = BOOT_DISPLAY_TV2;
+ M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
+ break;
+ case 0x5f36: /* Boot TV Format Hook */
+ printk(BIOS_DEBUG, "Boot TV Format Hook. TODO\n");
+ /* Interrupt was not handled */
+ return 0;
+ case 0x5f31: /* Post Completion Hook */
+ case 0x5f33: /* Hook After Mode Set */
+ case 0x5f34: /* Set Panel Fitting Hook */
+ case 0x5f38: /* Hook Before Mode Set */
+ case 0x5f45: /* Hook Before VESA VBE/DDC */
+ case 0x5f46: /* Hook Before VESA VBE/PM */
+ case 0x5f47: /* Notif Display Switch Hook */
+ case 0x5f65: /* Local Memory Initialization Hook */
+ /* Interrupt was not handled */
+ return 0;
+ default:
+ /* Interrupt was not handled */
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+
+static void int15_install(void)
+{
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ parport_gpios();
+ flash_gpios();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+ CHIP_NAME("THOMSON IP1000 Mainboard")
+};
diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c
deleted file mode 100644
index c299bc8..0000000
--- a/src/mainboard/traverse/geos/mainboard.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Traverse Technologies Geos Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/traverse/geos/ramstage.c b/src/mainboard/traverse/geos/ramstage.c
new file mode 100644
index 0000000..c299bc8
--- /dev/null
+++ b/src/mainboard/traverse/geos/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Geos ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "Geos EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Traverse Technologies Geos Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/tyan/s1846/mainboard.c b/src/mainboard/tyan/s1846/mainboard.c
deleted file mode 100644
index fb2034c..0000000
--- a/src/mainboard/tyan/s1846/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S1846 Mainboard")
-};
diff --git a/src/mainboard/tyan/s1846/ramstage.c b/src/mainboard/tyan/s1846/ramstage.c
new file mode 100644
index 0000000..fb2034c
--- /dev/null
+++ b/src/mainboard/tyan/s1846/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S1846 Mainboard")
+};
diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c
deleted file mode 100644
index 5456b9e..0000000
--- a/src/mainboard/tyan/s2735/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2735 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2735/ramstage.c b/src/mainboard/tyan/s2735/ramstage.c
new file mode 100644
index 0000000..5456b9e
--- /dev/null
+++ b/src/mainboard/tyan/s2735/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2735 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c
deleted file mode 100644
index 137aa57..0000000
--- a/src/mainboard/tyan/s2850/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2850 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2850/ramstage.c b/src/mainboard/tyan/s2850/ramstage.c
new file mode 100644
index 0000000..137aa57
--- /dev/null
+++ b/src/mainboard/tyan/s2850/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2850 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2875/mainboard.c b/src/mainboard/tyan/s2875/mainboard.c
deleted file mode 100644
index cbc4c6c..0000000
--- a/src/mainboard/tyan/s2875/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2875 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2875/ramstage.c b/src/mainboard/tyan/s2875/ramstage.c
new file mode 100644
index 0000000..cbc4c6c
--- /dev/null
+++ b/src/mainboard/tyan/s2875/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2875 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c
deleted file mode 100644
index 96e3cf2..0000000
--- a/src/mainboard/tyan/s2880/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2880 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2880/ramstage.c b/src/mainboard/tyan/s2880/ramstage.c
new file mode 100644
index 0000000..96e3cf2
--- /dev/null
+++ b/src/mainboard/tyan/s2880/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2880 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c
deleted file mode 100644
index 5034c5d..0000000
--- a/src/mainboard/tyan/s2881/mainboard.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan
- * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
- * Copyright (C) 2007 Ward Vandewege <ward at gnu.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2881 Mainboard")
-};
diff --git a/src/mainboard/tyan/s2881/ramstage.c b/src/mainboard/tyan/s2881/ramstage.c
new file mode 100644
index 0000000..5034c5d
--- /dev/null
+++ b/src/mainboard/tyan/s2881/ramstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
+ * Copyright (C) 2007 Ward Vandewege <ward at gnu.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2881 Mainboard")
+};
diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c
deleted file mode 100644
index 771d8b6..0000000
--- a/src/mainboard/tyan/s2882/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2882 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2882/ramstage.c b/src/mainboard/tyan/s2882/ramstage.c
new file mode 100644
index 0000000..771d8b6
--- /dev/null
+++ b/src/mainboard/tyan/s2882/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2882 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
deleted file mode 100644
index 446460d..0000000
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2885 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2885/ramstage.c b/src/mainboard/tyan/s2885/ramstage.c
new file mode 100644
index 0000000..446460d
--- /dev/null
+++ b/src/mainboard/tyan/s2885/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2885 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c
deleted file mode 100644
index 155f084..0000000
--- a/src/mainboard/tyan/s2891/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2891 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2891/ramstage.c b/src/mainboard/tyan/s2891/ramstage.c
new file mode 100644
index 0000000..155f084
--- /dev/null
+++ b/src/mainboard/tyan/s2891/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2891 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c
deleted file mode 100644
index 10fd0c0..0000000
--- a/src/mainboard/tyan/s2892/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2892 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2892/ramstage.c b/src/mainboard/tyan/s2892/ramstage.c
new file mode 100644
index 0000000..10fd0c0
--- /dev/null
+++ b/src/mainboard/tyan/s2892/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2892 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c
deleted file mode 100644
index 4de60af..0000000
--- a/src/mainboard/tyan/s2895/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2895 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s2895/ramstage.c b/src/mainboard/tyan/s2895/ramstage.c
new file mode 100644
index 0000000..4de60af
--- /dev/null
+++ b/src/mainboard/tyan/s2895/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2895 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s2912/mainboard.c b/src/mainboard/tyan/s2912/mainboard.c
deleted file mode 100644
index bfdb75e..0000000
--- a/src/mainboard/tyan/s2912/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2912 Mainboard")
-};
diff --git a/src/mainboard/tyan/s2912/ramstage.c b/src/mainboard/tyan/s2912/ramstage.c
new file mode 100644
index 0000000..bfdb75e
--- /dev/null
+++ b/src/mainboard/tyan/s2912/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2912 Mainboard")
+};
diff --git a/src/mainboard/tyan/s2912_fam10/mainboard.c b/src/mainboard/tyan/s2912_fam10/mainboard.c
deleted file mode 100644
index 3fed2f8..0000000
--- a/src/mainboard/tyan/s2912_fam10/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
-};
diff --git a/src/mainboard/tyan/s2912_fam10/ramstage.c b/src/mainboard/tyan/s2912_fam10/ramstage.c
new file mode 100644
index 0000000..3fed2f8
--- /dev/null
+++ b/src/mainboard/tyan/s2912_fam10/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu at amd.com> for AMD.
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
+};
diff --git a/src/mainboard/tyan/s4880/mainboard.c b/src/mainboard/tyan/s4880/mainboard.c
deleted file mode 100644
index ad9adab..0000000
--- a/src/mainboard/tyan/s4880/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S4880 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s4880/ramstage.c b/src/mainboard/tyan/s4880/ramstage.c
new file mode 100644
index 0000000..ad9adab
--- /dev/null
+++ b/src/mainboard/tyan/s4880/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S4880 Mainboard")
+};
+
diff --git a/src/mainboard/tyan/s4882/mainboard.c b/src/mainboard/tyan/s4882/mainboard.c
deleted file mode 100644
index 0595d59..0000000
--- a/src/mainboard/tyan/s4882/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Tyan S4882 Mainboard")
-};
-
diff --git a/src/mainboard/tyan/s4882/ramstage.c b/src/mainboard/tyan/s4882/ramstage.c
new file mode 100644
index 0000000..0595d59
--- /dev/null
+++ b/src/mainboard/tyan/s4882/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Tyan S4882 Mainboard")
+};
+
diff --git a/src/mainboard/via/epia-cn/mainboard.c b/src/mainboard/via/epia-cn/mainboard.c
deleted file mode 100644
index 702b5b0..0000000
--- a/src/mainboard/via/epia-cn/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA EPIA-CN Mainboard")
-};
diff --git a/src/mainboard/via/epia-cn/ramstage.c b/src/mainboard/via/epia-cn/ramstage.c
new file mode 100644
index 0000000..702b5b0
--- /dev/null
+++ b/src/mainboard/via/epia-cn/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-CN Mainboard")
+};
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
deleted file mode 100644
index 49f18df..0000000
--- a/src/mainboard/via/epia-m/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA EPIA-M Mainboard")
-};
-
diff --git a/src/mainboard/via/epia-m/ramstage.c b/src/mainboard/via/epia-m/ramstage.c
new file mode 100644
index 0000000..49f18df
--- /dev/null
+++ b/src/mainboard/via/epia-m/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-M Mainboard")
+};
+
diff --git a/src/mainboard/via/epia-m700/mainboard.c b/src/mainboard/via/epia-m700/mainboard.c
deleted file mode 100644
index 53537e0..0000000
--- a/src/mainboard/via/epia-m700/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA EPIA-M700 Mainboard")
-};
diff --git a/src/mainboard/via/epia-m700/ramstage.c b/src/mainboard/via/epia-m700/ramstage.c
new file mode 100644
index 0000000..53537e0
--- /dev/null
+++ b/src/mainboard/via/epia-m700/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-M700 Mainboard")
+};
diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c
deleted file mode 100644
index 528e891..0000000
--- a/src/mainboard/via/epia-n/mainboard.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA EPIA-N Mainboard")
-};
diff --git a/src/mainboard/via/epia-n/ramstage.c b/src/mainboard/via/epia-n/ramstage.c
new file mode 100644
index 0000000..528e891
--- /dev/null
+++ b/src/mainboard/via/epia-n/ramstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-N Mainboard")
+};
diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c
deleted file mode 100644
index 95edf46..0000000
--- a/src/mainboard/via/epia/mainboard.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA EPIA Mainboard")
-};
-
diff --git a/src/mainboard/via/epia/ramstage.c b/src/mainboard/via/epia/ramstage.c
new file mode 100644
index 0000000..95edf46
--- /dev/null
+++ b/src/mainboard/via/epia/ramstage.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA Mainboard")
+};
+
diff --git a/src/mainboard/via/pc2500e/mainboard.c b/src/mainboard/via/pc2500e/mainboard.c
deleted file mode 100644
index 65aed56..0000000
--- a/src/mainboard/via/pc2500e/mainboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA pc2500e Mainboard")
-};
diff --git a/src/mainboard/via/pc2500e/ramstage.c b/src/mainboard/via/pc2500e/ramstage.c
new file mode 100644
index 0000000..65aed56
--- /dev/null
+++ b/src/mainboard/via/pc2500e/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA pc2500e Mainboard")
+};
diff --git a/src/mainboard/via/vt8454c/mainboard.c b/src/mainboard/via/vt8454c/mainboard.c
deleted file mode 100644
index c6e1b92..0000000
--- a/src/mainboard/via/vt8454c/mainboard.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("VIA VT8454c Mainboard")
-};
-
diff --git a/src/mainboard/via/vt8454c/ramstage.c b/src/mainboard/via/vt8454c/ramstage.c
new file mode 100644
index 0000000..c6e1b92
--- /dev/null
+++ b/src/mainboard/via/vt8454c/ramstage.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA VT8454c Mainboard")
+};
+
diff --git a/src/mainboard/winent/pl6064/mainboard.c b/src/mainboard/winent/pl6064/mainboard.c
deleted file mode 100644
index 0293c7a..0000000
--- a/src/mainboard/winent/pl6064/mainboard.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Win Enterprises, Inc. (anishp at win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the license.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("Win Enterprises PL-6064/65 Mainboard")
- .enable_dev = enable_dev,
-};
diff --git a/src/mainboard/winent/pl6064/ramstage.c b/src/mainboard/winent/pl6064/ramstage.c
new file mode 100644
index 0000000..0293c7a
--- /dev/null
+++ b/src/mainboard/winent/pl6064/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Win Enterprises, Inc. (anishp at win-ent.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the license.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "Win Enterprises PL-6064/65 EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Win Enterprises PL-6064/65 Mainboard")
+ .enable_dev = enable_dev,
+};
diff --git a/src/mainboard/wyse/s50/mainboard.c b/src/mainboard/wyse/s50/mainboard.c
deleted file mode 100644
index 99dfb42..0000000
--- a/src/mainboard/wyse/s50/mainboard.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Nils Jacobs
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-
-static void init(struct device *dev)
-{
- printk(BIOS_DEBUG, "S50 ENTER %s\n", __func__);
- printk(BIOS_DEBUG, "S50 EXIT %s\n", __func__);
-}
-
-static void enable_dev(struct device *dev)
-{
- dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
- CHIP_NAME("WYSE S50 Mainboard")
- .enable_dev = enable_dev,
-};
-
diff --git a/src/mainboard/wyse/s50/ramstage.c b/src/mainboard/wyse/s50/ramstage.c
new file mode 100644
index 0000000..99dfb42
--- /dev/null
+++ b/src/mainboard/wyse/s50/ramstage.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "S50 ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "S50 EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("WYSE S50 Mainboard")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index be2b8cd..0e356f0 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -32,7 +32,7 @@
#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */
-/*implement in mainboard.c*/
+/*implement in ramstage.c*/
void set_pcie_reset(void);
void set_pcie_dereset(void);
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 7286a6d..8b89e59 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -33,7 +33,7 @@
#include "sb_cimx.h" /* AMD CIMX wrapper entries */
-/*implement in mainboard.c*/
+/*implement in ramstage.c*/
void set_pcie_reset(void);
void set_pcie_dereset(void);
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 85485ed..3604c67 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -29,7 +29,7 @@
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
-/*implement in mainboard.c*/
+/*implement in ramstage.c*/
//void set_pcie_assert(void);
//void set_pcie_deassert(void);
void set_pcie_reset(void);
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index f70cd9b..89749a4 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -1396,7 +1396,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
/* 5.9.5 Reset PCIE_GFX Slot */
- /* It is done in mainboard.c */
+ /* It is done in ramstage.c */
set_pcie_reset();
mdelay(1);
set_pcie_dereset();
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index bdbb08a..e86a547 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -53,7 +53,7 @@ static int sata_drive_detect(int portnum, u16 iobar)
return 0;
}
-/* This function can be overloaded in mainboard.c */
+/* This function can be overloaded in ramstage.c */
void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev)
{
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index d358ee8..b9f4361 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -70,7 +70,7 @@ void sb7xx_51xx_early_setup(void);
void sb7xx_51xx_before_pci_init(void);
#else
#include <device/pci.h>
-/* allow override in mainboard.c */
+/* allow override in ramstage.c */
void sb7xx_51xx_setup_sata_phys(struct device *dev);
#endif
diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c
index 209437b..06d5182 100644
--- a/src/southbridge/via/vt8237r/ide.c
+++ b/src/southbridge/via/vt8237r/ide.c
@@ -27,7 +27,7 @@
#include "chip.h"
/**
- * Cable type detect function, weak so it can be overloaded in mainboard.c
+ * Cable type detect function, weak so it can be overloaded in ramstage.c
*/
u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev)
{
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