[coreboot] Patch set updated for coreboot: cd477eb AMD S3: The offset of the nv storage depends on config.h
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Fri Aug 24 17:18:41 CEST 2012
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1485
-gerrit
commit cd477eb12b45292aef3f49f4f14c027224c93699
Author: Zheng Bao <fishbaozi at gmail.com>
Date: Fri Aug 24 23:18:28 2012 +0800
AMD S3: The offset of the nv storage depends on config.h
Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: zheng Bao <fishbaozi at gmail.com>
---
src/southbridge/amd/Kconfig | 11 ++++++++++-
src/southbridge/amd/Makefile.inc | 2 +-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig
index 23f6c06..d2bf958 100644
--- a/src/southbridge/amd/Kconfig
+++ b/src/southbridge/amd/Kconfig
@@ -17,5 +17,14 @@ source src/southbridge/amd/sr5650/Kconfig
# This can be overriden by mainboard/Kconfig
config S3_VOLATILE_POS
- hex
+ hex "s3 volatile position"
default 0xFFFF0000
+ depends on (HAVE_ACPI_RESUME \
+ && (SOUTHBRIDGE_AMD_AGESA_HUDSON \
+ || SOUTHBRIDGE_AMD_CIMX_SB700 \
+ || SOUTHBRIDGE_AMD_CIMX_SB800 \
+ || SOUTHBRIDGE_AMD_CIMX_SB900 \
+ || SOUTHBRIDGE_AMD_SB800 \
+ || SOUTHBRIDGE_AMD_SB700 \
+ || SOUTHBRIDGE_AMD_SB600))
+
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index d2b9b65..1e3309a 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -19,7 +19,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
ifeq ($(CONFIG_CPU_AMD_AGESA), y)
-$(obj)/s3.rom:
+$(obj)/s3.rom: $(obj)/config.h
echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)"
# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp
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