No subject

The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap determines
the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#,WR# and ROMCS#
asserted.

The Boot Flash supported by the SC1200/SC1201 can be
up to 16 MB. It is supported with the ROMCS# signal.

        As the corelogic module positively decodes the memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset, I can have my Flash memory mapped to 
the lower address. Is it?


>From: ron minnich <rminnich at lanl.gov>
>To: Devi Priya <ijpriya at hotmail.com>
>CC: linuxbios at clustermatic.org
>Subject: Re: Flash mapped to lower address?
>Date: Wed, 24 Dec 2003 18:39:20 -0700 (MST)
>
>On Tue, 23 Dec 2003, Devi Priya wrote:
>
> > If i have my Flash memory mapped to the lower address (0x0000-0x3FFFFF),
> > then what modification should be made to linux bios?
>
>why on earth would you map flash to this address? it makes no sense to me.
>
>ron
>
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