[coreboot] Patch set updated for coreboot: c924cbe H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes.

[Kerry Sheh (shekairui@gmail.com)]

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568

-gerrit

commit c924cbee830691c4a776465c09029575d0197c90
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Feb 1 16:05:50 2012 +0800

    H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes.
    
    For mainboard using AMD AGESA framework, lots of AGESA code will be
    compiled into romstage, so romstage becomes larger, especially for mainboard
    support 2 or more processor families.
    H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough,
    so increase to 1M Bytes.
    
    Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/Kconfig |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index e900ea8..201df45 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -123,5 +123,19 @@ config VGA_BIOS_ID
 	depends on VGA_BIOS
 	default "102b,0532"
 
+config XIP_ROM_BASE
+	hex
+	default 0xfff00000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+	help
+	  Overwride the default write through caching size as 1M Bytes.
+	  On some AMD paltform, one socket support 2 kinds of processor family,
+	  Compiling 2 cpu families agesa code will increase the romstage size.
+	  In order to execute romstage in place on the flash rom,
+	  more space is required to be set as write through caching.
+
 endif # BOARD_SUPERMICRO_H8QGI