[coreboot] New patch to review for coreboot: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Feb 15 15:25:53 CET 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/638
-gerrit
commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Feb 15 15:55:57 2012 +0200
Intel cpus: use CPU_PHYSMASK_HI define in CAR
Unifies models 6ex, 6fx and 106cx.
Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/model_106cx/cache_as_ram.inc | 9 ++++++---
src/cpu/intel/model_6ex/cache_as_ram.inc | 11 +++++++----
src/cpu/intel/model_6fx/cache_as_ram.inc | 9 ++++++---
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 824e341..caf5d03 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -22,6 +22,9 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
+#define CPU_MAXPHYADDR 32
+#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -64,7 +67,7 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
- xorl %edx, %edx
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
/* Enable MTRR. */
@@ -112,7 +115,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- xorl %edx, %edx
+ movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -197,7 +200,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
- xorl %edx, %edx
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x39)
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 18ada29..08f5b11 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -22,6 +22,9 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
+#define CPU_MAXPHYADDR 36
+#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -64,7 +67,7 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
- movl $0x0000000f, %edx
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
/* Enable MTRR. */
@@ -112,7 +115,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $0x0000000f, %edx
+ movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -197,7 +200,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
- movl $0x0000000f, %edx // 36bit address space
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
/* Enable caching and Speculative Reads for the last 4MB. */
@@ -207,7 +210,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
- movl $0x0000000f, %edx // 36bit address space
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x39)
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index dfc4f3b..25d8de2 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -22,6 +22,9 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
+#define CPU_MAXPHYADDR 36
+#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -71,7 +74,7 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
- movl $0x0000000f, %edx
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
/* Enable MTRR. */
@@ -119,7 +122,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $0x0000000f, %edx
+ movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@@ -204,7 +207,7 @@ clear_mtrrs:
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
- movl $0x0000000f, %edx // 36bit address space
+ movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(0x39)
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