[coreboot] New patch to review for coreboot: b1709fd SB800: add debug info

[Kerry Sheh (shekairui@gmail.com)]

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/546

-gerrit

commit b1709fdd0839d7e840062fcb2354276d0264dce1
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:19:17 2012 +0800

    SB800: add debug info
    
    Print out pcie gpp device training status at BIOS_DEBUG level in
    the SB800 GPP training process.
    
    Change-Id: Ie50f6ad44b60982dd52253a759eb4c004e0df001
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/vendorcode/amd/cimx/sb800/Gpp.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/Gpp.c b/src/vendorcode/amd/cimx/sb800/Gpp.c
index 72cb1cd..6b89589 100644
--- a/src/vendorcode/amd/cimx/sb800/Gpp.c
+++ b/src/vendorcode/amd/cimx/sb800/Gpp.c
@@ -396,6 +396,7 @@ CheckGppLinkStatus (
         SbStall (1000);                          // Delay 400us
         abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);
         Data32 = readAlink (abIndex) & 0x3F3F3F3F;
+	printk(BIOS_DEBUG, "SB800 GPP port 0x%x training status=0x%x\n", portId, Data32);
 
         if ( (UINT8) (Data32) == 0x10 ) {
           portCfg->PortDetected = TRUE;