[coreboot] Asus m2n-e mcp55 won't boot

Julian Shulika hercares at gmail.com
Mon Jan 30 14:17:32 CET 2012


Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board
turns off after few seconds
The log from serial

Welcome to minicom 2.5

OPTIONS:

Compiled on Dec  4 2011,
11:23:38.
Port
/dev/ttyS0


Press CTRL-A Z for help on special
keys






coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012
starting...
*sysinfo range:
[000cf000,000cf730]
bsp_apicid=0x00

Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
started ap apicid:
SBLink=00
NC node|link=00
entering
optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1

entering
ht_optimize_link
pos=0x8a, unfiltered
freq_cap=0x8075
pos=0x8a, filtered
freq_cap=0x75
pos=0x52, unfiltered
freq_cap=0x807f
pos=0x52, filtered
freq_cap=0x7f
freq_cap1=0x75,
freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6,
needs_reset=0x1
dev2 old_freq=0x0, freq=0x6,
needs_reset=0x1
width_cap1=0x11,
width_cap2=0x11
dev1 input ln_width1=0x4,
ln_width2=0x4
dev1 input
width=0x1
dev1 output ln_width1=0x4,
ln_width2=0x4
dev1 input|output
width=0x11
old dev1 input|output
width=0x11
dev2 input|output
width=0x11
old dev2 input|output
width=0x11
after ht_optimize_link for link pair 0,
reset_needed=0x1
after optimize_link_read_pointers_chain,
reset_needed=0x1
mcp55_num:01

ht reset
-




coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012
starting...
*sysinfo range:
[000cf000,000cf730]
bsp_apicid=0x00

Enabling routing table for node 00
done.
Enabling UP
settings
Disabling read/write/fill probes for UP...
done.
coherent_ht_finalize

done

core0
started:
started ap
apicid:
SBLink=00

NC
node|link=00

entering
optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1

entering
ht_optimize_link
pos=0x8a, unfiltered
freq_cap=0x8075
pos=0x8a, filtered
freq_cap=0x75
pos=0x52, unfiltered
freq_cap=0x7f
pos=0x52, filtered
freq_cap=0x7f
freq_cap1=0x75,
freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6,
needs_reset=0x0
dev2 old_freq=0x6, freq=0x6,
needs_reset=0x0
width_cap1=0x11,
width_cap2=0x11
dev1 input ln_width1=0x4,
ln_width2=0x4
dev1 input
width=0x1
dev1 output ln_width1=0x4,
ln_width2=0x4
dev1 input|output
width=0x11
old dev1 input|output
width=0x11
dev2 input|output
width=0x11
old dev2 input|output
width=0x11
after ht_optimize_link for link pair 0,
reset_needed=0x0
after optimize_link_read_pointers_chain,
reset_needed=0x0
mcp55_num:01

Ram1.00

setting up CPU 00 northbridge
registers
done.

Ram2.00

sdram_set_spd_registers: paramx
:000cef20
Enable 64MuxMode &
BurstLength32
Unbuffered

333MHz

333MHz

set_ecc spd_device:
0x51
Interleaving
disabled
RAM end at 0x00080000
kB
Ram3

ECC
enabled
Initializing memory:
done
Setting variable MTRR 2, base:    0MB, range:  512MB, type
WB
set DQS timing:RcvrEn:Pass1:
00
 CTLRMaxDelay=03

 done

set DQS timing:DQSPos:
00
TrainDQSRdWrPos:
buf_a:000ce9f0
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8d8
 done

set DQS timing:RcvrEn:Pass2:
00
 CTLRMaxDelay=58

 done

Total DQS Training : tsc
[00]=0000000012e40bef
Total DQS Training : tsc
[01]=000000001358f446
Total DQS Training : tsc
[02]=0000000018d60c82
Total DQS Training : tsc
[03]=0000000019771d46
Ram4

v_esp=000cef68

testx =
5a5a5a5a





INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00}
---


Issuing
SOFT_RESET...




coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012
starting...
*sysinfo range:
[000cf000,000cf730]
bsp_apicid=0x00

Enabling routing table for node 00
done.
Enabling UP
settings
Disabling read/write/fill probes for UP...
done.
coherent_ht_finalize

done

core0
started:
started ap
apicid:
SBLink=00

NC
node|link=00

entering
optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1

entering
ht_optimize_link
pos=0x8a, unfiltered
freq_cap=0x8075
pos=0x8a, filtered
freq_cap=0x75
pos=0x52, unfiltered
freq_cap=0x7f
pos=0x52, filtered
freq_cap=0x7f
freq_cap1=0x75,
freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6,
needs_reset=0x0
dev2 old_freq=0x6, freq=0x6,
needs_reset=0x0
width_cap1=0x11,
width_cap2=0x11
dev1 input ln_width1=0x4,
ln_width2=0x4
dev1 input
width=0x1
dev1 output ln_width1=0x4,
ln_width2=0x4
dev1 input|output
width=0x11
old dev1 input|output
width=0x11
dev2 input|output
width=0x11
old dev2 input|output
width=0x11
after ht_optimize_link for link pair 0,
reset_needed=0x0
after optimize_link_read_pointers_chain,
reset_needed=0x0
mcp55_num:01

Ram1.00

setting up CPU 00 northbridge
registers
done.

Ram2.00

sdram_set_spd_registers: paramx
:000cef20
Enable 64MuxMode &
BurstLength32
Unbuffered

333MHz

333MHz

set_ecc spd_device:
0x51
Interleaving
disabled
RAM end at 0x00080000
kB
Ram3

ECC
enabled
Initializing memory:
done
Setting variable MTRR 2, base:    0MB, range:  512MB, type
WB
set DQS timing:RcvrEn:Pass1:
00
 CTLRMaxDelay=03

 done

set DQS timing:DQSPos:
00
TrainDQSRdWrPos:
buf_a:000ce9f0
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8d8
 done

set DQS timing:RcvrEn:Pass2:
00
 CTLRMaxDelay=58

 done

Total DQS Training : tsc
[00]=0000000012e3eacf
Total DQS Training : tsc
[01]=000000001358d326
Total DQS Training : tsc
[02]=0000000018d97cfa
Total DQS Training : tsc
[03]=00000000197a8c56
Ram4

v_esp=000cef68

testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack...
D




INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00}
---


Issuing
SOFT_RESET...




coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012
starting...
*sysinfo range:
[000cf000,000cf730]
bsp_apicid=0x00

Enabling routing table for node 00
done.
Enabling UP
settings
Disabling read/write/fill probes for UP...
done.
coherent_ht_finalize

done

core0
started:
started ap
apicid:
SBLink=00

NC
node|link=00

entering
optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1

entering
ht_optimize_link
pos=0x8a, unfiltered
freq_cap=0x8075
pos=0x8a, filtered
freq_cap=0x75
pos=0x52, unfiltered
freq_cap=0x7f
pos=0x52, filtered
freq_cap=0x7f
freq_cap1=0x75,
freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6,
needs_reset=0x0
dev2 old_freq=0x6, freq=0x6,
needs_reset=0x0
width_cap1=0x11,
width_cap2=0x11
dev1 input ln_width1=0x4,
ln_width2=0x4
dev1 input
width=0x1
dev1 output ln_width1=0x4,
ln_width2=0x4
dev1 input|output
width=0x11
old dev1 input|output
width=0x11
dev2 input|output
width=0x11
old dev2 input|output
width=0x11
after ht_optimize_link for link pair 0,
reset_needed=0x0
after optimize_link_read_pointers_chain,
reset_needed=0x0
mcp55_num:01

Ram1.00

setting up CPU 00 northbridge
registers
done.

Ram2.00

sdram_set_spd_registers: paramx
:000cef20
Enable 64MuxMode &
BurstLength32
Unbuffered

333MHz

333MHz

set_ecc spd_device:
0x51
Interleaving
disabled
RAM end at 0x00080000
kB
Ram3

ECC
enabled
Initializing memory:
done
Setting variable MTRR 2, base:    0MB, range:  512MB, type
WB
set DQS timing:RcvrEn:Pass1:
00
 CTLRMaxDelay=03

 done

set DQS timing:DQSPos:
00
TrainDQSRdWrPos:
buf_a:000ce9f0
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8d8
 done

set DQS timing:RcvrEn:Pass2:
00
 CTLRMaxDelay=58

 done

Total DQS Training : tsc
[00]=0000000012e3ed63
Total DQS Training : tsc
[01]=000000001358f68a
Total DQS Training : tsc
[02]=0000000018d73a6a
Total DQS Training : tsc
[03]=0000000019784e5a
Ram4

v_esp=000cef68

testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack...
m




INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00}
---


Issuing
SOFT_RESET...




coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012
starting...
*sysinfo range:
[000cf000,000cf730]
bsp_apicid=0x00

Enabling routing table for node 00
done.
Enabling UP
settings
Disabling read/write/fill probes for UP...
done.
coherent_ht_finalize

done

core0
started:
started ap
apicid:
SBLink=00

NC
node|link=00

entering
optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1

entering
ht_optimize_link
pos=0x8a, unfiltered
freq_cap=0x8075
pos=0x8a, filtered
freq_cap=0x75
pos=0x52, unfiltered
freq_cap=0x7f
pos=0x52, filtered
freq_cap=0x7f
freq_cap1=0x75,
freq_cap2=0x7f
dev1 old_freq=0x6, freq=0x6,
needs_reset=0x0
dev2 old_freq=0x6, freq=0x6,
needs_reset=0x0
width_cap1=0x11,
width_cap2=0x11
dev1 input ln_width1=0x4,
ln_width2=0x4
dev1 input
width=0x1
dev1 output ln_width1=0x4,
ln_width2=0x4
dev1 input|output
width=0x11
old dev1 input|output
width=0x11
dev2 input|output
width=0x11
old dev2 input|output
width=0x11
after ht_optimize_link for link pair 0,
reset_needed=0x0
after optimize_link_read_pointers_chain,
reset_needed=0x0
mcp55_num:01

Ram1.00

setting up CPU 00 northbridge
registers
done.

Ram2.00

sdram_set_spd_registers: paramx
:000cef20
Enable 64MuxMode &
BurstLength32
Unbuffered

333MHz

333MHz

set_ecc spd_device:
0x51
Interleaving
disabled
RAM end at 0x00080000
kB
Ram3

ECC
enabled
Initializing memory:
done
Setting variable MTRR 2, base:    0MB, range:  512MB, type
WB
set DQS timing:RcvrEn:Pass1:
00
 CTLRMaxDelay=03

 done

set DQS timing:DQSPos:
00
TrainDQSRdWrPos:
buf_a:000ce9f0
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8c8
TrainDQSPos: MutualCSPassW[48]
:000ce8d8
 done

set DQS timing:RcvrEn:Pass2:
00
 CTLRMaxDelay=58

 done

Total DQS Training : tsc
[00]=0000000012e4504b
Total DQS Training : tsc
[01]=0000000013593c4a
Total DQS Training : tsc
[02]=0000000018d6d4b2
Total DQS Training : tsc
[03]=000000001977e9ce
Ram4

v_esp=000cef68

testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack...
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