[coreboot] Patch merged into coreboot/master: 696dc0b Fixes to enable RC6 on IvyBridge

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 696dc0b6d66d34d0c15798f365387ff8f1436e17
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri May 25 10:04:17 2012 -0700

    Fixes to enable RC6 on IvyBridge
    
    - The unneeded poll on non-MT force-wake bit was timing out
    and causing the gma_pm_init_pre_vbios() function to exit
    early so it was not preparing PM registers properly.
    I changed the gtt_poll() calls to not return on timeout
    unless it can't proceed so we don't see half-initialized
    registers.
    
    - RC6+ (Deep Render Standby) is not working reliably so we
    can just enable RC6 in the BIOS and let the kernel decide
    if it wants to enable RC6+ later.
    
    This Kernel message is new in kernel 3.4:
    [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
    
    Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>

Build-Tested: build bot (Jenkins) at Mon Jul 23 23:40:59 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Tue Jul 24 00:02:18 2012, giving +2
See http://review.coreboot.org/1268 for details.

-gerrit