[coreboot] New patch to review for coreboot: 369708b Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Jul 24 01:42:45 CEST 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1332
-gerrit
commit 369708b9bce3a905f26dbb41d6b4f38dd29b25d0
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Tue Jul 10 17:02:21 2012 -0700
Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247
Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
src/cpu/Kconfig | 5 +----
src/cpu/intel/model_206ax/Kconfig | 4 +---
src/cpu/intel/model_206ax/bootblock.c | 10 ----------
src/cpu/intel/model_206ax/model_206ax_init.c | 10 ----------
4 files changed, 2 insertions(+), 27 deletions(-)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index f37bbf6..baf686e 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,13 +62,10 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
-if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
-
config MICROCODE_IN_CBFS
bool "Look for microcode in CBFS"
+ default n
help
Load microcode updates from CBFS instead of compiling them in.
-endif
-
endif # ARCH_X86
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 1d4ff02..071683e 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
+ select MICROCODE_IN_CBFS
config BOOTBLOCK_CPU_INIT
string
@@ -21,14 +22,11 @@ config SMM_TSEG_SIZE
hex
default 0x800000
-if MICROCODE_IN_CBFS
config MICROCODE_INCLUDE_PATH
string
default "src/cpu/intel/model_206ax"
endif
-endif
-
if CPU_INTEL_MODEL_206AX
config CPU_MODEL_NAME
string
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index dbc3591..02958bb 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -25,12 +25,6 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
-#if !CONFIG_MICROCODE_IN_CBFS
-static const uint32_t microcode_updates[] = {
- #include "microcode_blob.h"
-};
-#endif
-
#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"
@@ -125,9 +119,5 @@ static void bootblock_cpu_init(void)
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
enable_rom_caching();
-#if CONFIG_MICROCODE_IN_CBFS
intel_update_microcode_from_cbfs();
-#else
- intel_update_microcode(microcode_updates);
-#endif
}
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 08757d1..70a655a 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -115,12 +115,6 @@ static acpi_cstate_t cstate_map[] = {
{ 0 }
};
-#if !CONFIG_MICROCODE_IN_CBFS
-static const uint32_t microcode_updates[] = {
- #include "microcode_blob.h"
-};
-#endif
-
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
[0] = 0x00,
@@ -421,11 +415,7 @@ static void model_206ax_init(device_t cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
-#if CONFIG_MICROCODE_IN_CBFS
intel_update_microcode_from_cbfs();
-#else
- intel_update_microcode(microcode_updates);
-#endif
/* Clear out pending MCEs */
configure_mca();
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