[coreboot] Patch set updated for coreboot: 4241e40 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Thu Jul 26 01:22:59 CEST 2012
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245
-gerrit
commit 4241e40123f80ffb2e154c9477bb23f18b5e0822
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Fri Jul 20 00:11:21 2012 -0500
buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
This patch aims to improve the microcode in CBFS handling that was
implemented in the last patches from Stefan and the Chromium team.
When the CPU selects MICROCODE_IN_CBFS, the user is given three
choices in Kconfig
- 1) Generate microcode from tree (default)
- 2) Include external microcode file
- 3) Do not put microcode in CBFS
The idea is to give the user full control over including non-free
blobs in the final ROM image.
Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/arch/x86/Makefile.inc | 13 ++++++++--
src/cpu/Kconfig | 43 +++++++++++++++++++++++++++++++++-
src/cpu/amd/model_10xxx/Kconfig | 33 +-------------------------
src/cpu/intel/microcode/Makefile.inc | 4 +-
src/cpu/intel/microcode/microcode.c | 8 +++---
src/cpu/intel/model_206ax/Kconfig | 2 +-
src/include/cpu/intel/microcode.h | 2 +-
7 files changed, 61 insertions(+), 44 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 306f239..521f1db 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -34,9 +34,9 @@ cmos_layout.bin-type = 0x01aa
OPTION_TABLE_H:=$(obj)/option_table.h
endif
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
-cbfs-files-y += microcode_blob.bin
-microcode_blob.bin-file = $(obj)/microcode_blob.bin
+ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y)
+cbfs-files-y += cpu_microcode_blob.bin
+microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
microcode_blob.bin-type = 0x53
endif
@@ -55,6 +55,9 @@ endif
ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE)
+endif
extract_nth=$(word $(1), $(subst |, ,$(2)))
@@ -106,6 +109,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \
$(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+ @printf " CPU uCode cpu_microcode\n"
+ $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode
+endif
mv $@.tmp $@
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index baf686e..ebae1b9 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,10 +62,51 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
-config MICROCODE_IN_CBFS
+config CPU_MICROCODE_IN_CBFS
bool "Look for microcode in CBFS"
default n
help
Load microcode updates from CBFS instead of compiling them in.
endif # ARCH_X86
+
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_GENERATE
+ depends on CPU_MICROCODE_IN_CBFS
+
+config CPU_MICROCODE_CBFS_GENERATE
+ bool "Generate from tree"
+ help
+ Select this option if you want microcode updates to be assembled when
+ building coreboot and included in the final image as a separate CBFS
+ file. Microcode will not be hard-coded into ramstage, and may be
+ removed from the ROM image at a later time with cbfstool.
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ depends on CPU_MICROCODE_IN_CBFS
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ A word of caution: only select this option if you are sure the
+ microcode that you have is newer than the microcode shipping with
+ coreboot.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "Do not include microcode updates"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated.
+
+endchoice
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
\ No newline at end of file
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 221d044..64ac850 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
+ select RESPECTS_UPDATE_CPU_MICROCODE_OPTION
if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
@@ -51,36 +52,4 @@ config SET_FIDVID_CORE_RANGE
endif # SET_FIDVID
-config UPDATE_CPU_MICROCODE
- bool
- default y
-
-config UPDATE_CPU_MICROCODE
- bool "Update CPU microcode"
- default y
- depends on EXPERT && CPU_AMD_MODEL_10XXX
- help
- Select this to apply patches to the CPU microcode provided by
- AMD without source, and distributed with coreboot, to address
- issues in the CPU post production.
-
- Microcode updates distributed with coreboot are not necessarily
- the latest version available from AMD. Updates are only applied
- if they are newer than the microcode already in your CPU.
-
- Unselect this to let Fam10h CPUs run with microcode as shipped
- from factory. No binary microcode patches will be included in the
- coreboot image in that case, which can help with creating an image
- for which complete source code is available, which in turn might
- simplify license compliance.
-
- Microcode updates intend to solve issues that have been discovered
- after CPU production. The common case is that systems work as
- intended with updated microcode, but we have also seen cases where
- issues were solved by not applying the microcode updates.
-
- Note that some operating system include these same microcode
- patches, so you may need to also disable microcode updates in
- your operating system in order for this option to matter.
-
endif # CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f4d0102..754689a 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,14 +1,14 @@
ramstage-y += microcode.c
-ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
+ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y)
SRC_PATH = src/cpu/intel/microcode
FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
$(CC) $(FLAGS) -MMD -c -o $@ $<
-$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
+$(obj)/cpu_microcode_blob.bin: $(obj)/microcode_blob.o
objcopy -j .data -O binary $< $@
-include $(obj)/microcode_blob.d
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index e84bad9..a4471ca 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
#ifdef __PRE_RAM__
#include <arch/cbfs.h>
#else
@@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
static
#endif
void intel_update_microcode(const void *microcode_updates)
@@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
}
}
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
-#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void intel_update_microcode_from_cbfs(void)
{
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 071683e..60338e1 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select MICROCODE_IN_CBFS
+ select CPU_MICROCODE_IN_CBFS
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 289e919..e9c13f9 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -21,7 +21,7 @@
#define __CPU__INTEL__MICROCODE__
#ifndef __PRE_RAM__
-#if CONFIG_MICROCODE_IN_CBFS
+#if CONFIG_CPU_MICROCODE_IN_CBFS
void intel_update_microcode_from_cbfs(void);
#else
void intel_update_microcode(const void *microcode_updates);
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