[coreboot] Patch set updated for coreboot: 0077bb7 Make MTRR min hole alignment 64MB

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Mar 7 02:12:16 CET 2012


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765

-gerrit

commit 0077bb72e00748699551856abef8645ca1652a67
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:05:18 2012 -0800

    Make MTRR min hole alignment 64MB
    
    This affects the algorithm when determining when to
    transform a range into a larger range with a hole.
    
    It is needed when for when I switch on an 8MB TSEG
    and cause the memory maps to go crazy.
    
    Also add header defines for the SMRR.
    
    Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c    |    9 ++++++---
 src/include/cpu/x86/mtrr.h |    3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02b..ed7d93b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
 		/*
-		 * If this range is not divisible by 16MB then instead
+		 * If this range is not divisible then instead
 		 * make a larger range and carve out an uncached hole.
 		 */
 		hole_startk = range_startk + range_sizek;
-		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
 		range_sizek += hole_sizek;
 	}
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7..8b5cc28 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 




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