[coreboot] New patch to review for coreboot: c82896d Makefile: rename linker intermediate variable

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Tue Mar 20 15:05:16 CET 2012


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/802

-gerrit

commit c82896d576c16c91eab36be06743f57ea3d8bc0b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Mar 19 19:12:49 2012 +0200

    Makefile: rename linker intermediate variable
    
    Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig.
    Removed no-op calculation in ldscript.
    
    Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/Kconfig           |    4 ----
 src/arch/x86/Makefile.inc      |    4 ++--
 src/arch/x86/init/bootblock.ld |    7 +------
 3 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c5a0c0e..314646f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -8,10 +8,6 @@ config AP_IN_SIPI_WAIT
 	default n
 	depends on ARCH_X86
 
-config ROMBASE
-	hex
-	default 0xffff0000
-
 config RAMBASE
 	hex
 	default 0x100000
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index d3dac11..fc3cd14 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -342,10 +342,10 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
 # Build the romstage
 $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
-	printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
+	printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld
 	$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
 	$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
-	printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
+	printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld
 	$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }
 	cat $(obj)/location.txt >> $(obj)/location.ld
 	printf ';\n' >> $(obj)/location.ld
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index fd4d3db..27d718f 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -25,13 +25,8 @@ OUTPUT_ARCH(i386)
 TARGET(binary)
 SECTIONS
 {
-	. = CONFIG_ROMBASE;
+	. = ROMSTAGE_BASE;
 
-	/* cut _start into last 64k */
-	_x = .;
-	. = (_x < CONFIG_ROMBASE) ? (CONFIG_ROMBASE) : _x;
-
-	/* This section might be better named .setup */
 	.rom . : {
 		_rom = .;
 		*(.rom.text);




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