[coreboot] New patch to review for coreboot: e1b81de add new LPC controller device ID value

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/968

-gerrit

commit e1b81deaf1c17cb2c6723b8a35a595e0e6edf162
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Apr 7 02:11:36 2012 +0000

    add new LPC controller device ID value
    
    This adds the PCI device id of the LPC controller identifying the
    QPRJ/QS stepping of the Panther Point southbridge.
    
    Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/southbridge/intel/bd82x6x/lpc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1ecaf8f..9a3dc99 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -676,3 +676,8 @@ static const struct pci_driver c216_lpc __pci_driver = {
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= 0x1e55,
 };
+static const struct pci_driver hm75_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1e5d,
+};