[coreboot] New patch to review for coreboot: 22fe62d Sandybridge: Display platform information early It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with.

Tue May 1 01:50:24 CEST 2012

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/975

-gerrit

commit 22fe62dc4d4f662d067719bbac23dfb92891820e
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Apr 18 15:47:32 2012 -0700

    Sandybridge: Display platform information early
    It is important to have the system configuration reported as early as
    possible to have a better idea what exact chipset the platform is
    running with.
    
    This change adds code to have an early coreboot module report the CPU
    and PCH information. CPU info includes the 32 bit feature information
    word, the symbolic processor brand string, and information about some
    features support, as obtained through CPUID instructions.
    
    The PCH information includes the symbolic device name and PCI device
    version.
    
    Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/northbridge/intel/sandybridge/Makefile.inc     |    1 +
 src/northbridge/intel/sandybridge/raminit.c        |    2 +
 .../intel/sandybridge/report_platform.c            |  103 ++++++++++++++++++++
 src/northbridge/intel/sandybridge/sandybridge.h    |    1 +
 4 files changed, 107 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index b72e9fa..79aa6ea 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -25,6 +25,7 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 romstage-y += udelay.c
 romstage-y += raminit.c
 romstage-y += early_init.c
+romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/lib/walkcbfs.S
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index bbb743f..e1d5d26 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -318,6 +318,8 @@ void sdram_initialize(struct pei_data *pei_data)
 	const char *target = "mrc.bin";
 	unsigned long entry;
 
+	report_platform_info();
+
 	/* Wait for ME to be ready */
 	intel_early_me_init();
 	intel_early_me_uma_size();
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
new file mode 100644
index 0000000..d59cfe9
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/cpu.h>
+#include <string.h>
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include "sandybridge.h"
+
+static void report_cpu_info(void)
+{
+	struct cpuid_result cpuidr;
+	u32 i, index;
+	char cpu_string[50]; /* 48 bytes are reported */
+	int vt, txt, aes;
+	const char *mode[] = {"NOT ", ""};
+
+	index = 0x80000000;
+	cpuidr = cpuid(index);
+	if (cpuidr.eax < 0x80000004) {
+		strcpy(cpu_string, "Platform info not available");
+	} else {
+		u32 *p = (u32*) cpu_string;
+		for (i = 2; i <= 4 ; i++) {
+			cpuidr = cpuid(index + i);
+			*p++ = cpuidr.eax;
+			*p++ = cpuidr.ebx;
+			*p++ = cpuidr.ecx;
+			*p++ = cpuidr.edx;
+		}
+	}
+	cpuidr = cpuid(1);
+	printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_string);
+	aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+	txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+	vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+	printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
+	       mode[aes], mode[txt], mode[vt]);
+}
+
+/* The PCI id name match comes from Intel document 472178 */
+static struct {
+	u16 dev_id;
+	const char *dev_name;
+} pch_table [] = {
+	{0x1E41, "Desktop Sample"},
+	{0x1E47, "Q77"},
+	{0x1E48, "Q75"},
+	{0x1E49, "B75"},
+	{0x1E44, "Z77"},
+	{0x1E46, "Z75"},
+	{0x1E4A, "H77"},
+	{0x1E53, "C216"},
+	{0x1E42, "Mobile Sample"},
+	{0x1E55, "QM77"},
+	{0x1E58, "UM77"},
+	{0x1E57, "HM77"},
+	{0x1E59, "HM76"},
+	{0x1E5d, "HM75"},
+	{0x1E43, "SFF Sample"},
+	{0x1E56, "QS77"},
+};
+
+static void report_pch_info(void)
+{
+	int i;
+	u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+
+
+	const char *pch_type = "Unknown";
+	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+		if (pch_table[i].dev_id == dev_id) {
+			pch_type = pch_table[i].dev_name;
+			break;
+		}
+	}
+	printk (BIOS_DEBUG, "PCH type: %s rev id %x\n",
+		pch_type, pci_read_config8(PCH_LPC_DEV, 8));
+}
+
+void report_platform_info(void)
+{
+	report_cpu_info();
+	report_pch_info();
+}
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 9ff6555..1aa3a11 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -218,6 +218,7 @@ void dump_pci_device(unsigned dev);
 void dump_pci_devices(void);
 void dump_spd_registers(void);
 void dump_mem(unsigned start, unsigned end);
+void report_platform_info(void);
 #endif /* !__SMM__ */
 #endif
 #endif


