[coreboot] New patch to review for coreboot: aea1621 Fix issue with PCIe power management setup

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/980

-gerrit

commit aea1621bd1489a910483d2858dc5810c8d48207e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Apr 27 10:58:22 2012 -0700

    Fix issue with PCIe power management setup
    
    The current early PM setup that attempts to configure dynamic clock
    gating relies on PCIe functions to be enabled that may not be.
    Instead of reading port 0 or 4 directly to determine the link width
    use the register that refelects the soft strapping options as this
    will always be available.
    
    Also add a clear register assignment and break for port 0 in the
    switch statement instead of falling through to port 4 as that could
    end up setting the slot power limit based on port 4 values instead
    of based on port 0.
    register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
    
    When port 0 and 4 are disabled they will have 0xE1=0x3C before
    being disabled by the pch enable handler.
    
    LUMPY default:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      pci_read8 0 0x1c 0 0xe1
      0x3f
    
      pci_read8 0 0x1c 3 0xe1
      0x03
    
    LUMPY with PCIe port coalesce enabled:
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      pci_read8 0 0x1c 0 0xe1
      0x3f
    
      pci_read8 0 0x1c 1 0xe1
      0x03
    
    Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/bd82x6x/pcie.c |   44 ++++++++++++++++++++++++----------
 1 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 599692d..5ab18f6 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -25,17 +25,6 @@
 #include <device/pci_ids.h>
 #include "pch.h"
 
-static u16 pcie_port_link_width(int port)
-{
-	u16 link_width;
-
-	link_width = pci_read_config16(
-		dev_find_slot(0, PCI_DEVFN(0x1c, port)), 0x52);
-	link_width >>= 4;
-	link_width &= 0x3f;
-	return link_width;
-}
-
 static void pch_pcie_pm_early(struct device *dev)
 {
 	u16 link_width_p0, link_width_p4;
@@ -43,8 +32,35 @@ static void pch_pcie_pm_early(struct device *dev)
 	u32 reg32;
 	u8 reg8;
 
-	link_width_p0 = pcie_port_link_width(0);
-	link_width_p4 = pcie_port_link_width(4);
+	reg32 = RCBA32(RPC);
+
+	/* Port 0-3 link aggregation from PCIEPCS1[1:0] soft strap */
+	switch (reg32 & 3) {
+	case 3:
+		link_width_p0 = 4;
+		break;
+	case 1:
+	case 2:
+		link_width_p0 = 2;
+		break;
+	case 0:
+	default:
+		link_width_p0 = 1;
+	}
+
+	/* Port 4-7 link aggregation from PCIEPCS2[1:0] soft strap */
+	switch ((reg32 >> 2) & 3) {
+	case 3:
+		link_width_p4 = 4;
+		break;
+	case 1:
+	case 2:
+		link_width_p4 = 2;
+		break;
+	case 0:
+	default:
+		link_width_p4 = 1;
+	}
 
 	/* Enable dynamic clock gating where needed */
 	reg8 = pci_read_config8(dev, 0xe1);
@@ -54,6 +70,8 @@ static void pch_pcie_pm_early(struct device *dev)
 			slot_power_limit = 40; /* 40W for x4 */
 		else if (link_width_p0 == 2)
 			slot_power_limit = 20; /* 20W for x2 */
+		reg8 |= 0x3f;
+		break;
 	case 4: /* Port 4 */
 		if (link_width_p4 == 4)
 			slot_power_limit = 40; /* 40W for x4 */