[coreboot] Dual SPI Flash adapter attempt 2.0

Oliver Schinagl oliver+list at schinagl.nl
Sun May 13 15:39:25 CEST 2012


Just an FYI,

This is the final version that I will send over to seeed after placing 
an order. The only thing that will change is the order number (now it's 
an arbitrary number). If I have to do major changes to the board, I will 
of course send an updated version to the list.

Oliver

On 04/28/12 16:14, Oliver Schinagl wrote:
> Hey all,
>
> Find here all included fixes and modifications. I've increased spacing
> and removed the 'outline' layer. I moved parts to the edge. Since Seeed
> does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
> is ...
>
> If I don't see any feedback on things that need fixing here, I'll set
> out an order for the prototypes :)
>
> Oliver
>
> Have a good weekend all!
>
> On 04/26/12 18:56, Oliver Schinagl wrote:
>> Hey all,
>>
>> Well here it is, the last version which was even harder then the 3rd
>> one. or so it seemed anyhow.
>>
>> I will work on copying these four to the bottom and renaming the labels
>> before sending them off. I'll post the final pcb on this list again,but
>> routing wise, Nothing will change, unless of course someone found a
>> grand mistake.
>>
>> So really, all input is greatly appreciated :D would be shameful to send
>> this off to get printed, just to find bugs and have another batch made.
>>
>> Oliver
>>
>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>> Hi!
>>>
>>> I've worked on a rotated version and planning to do two other
>>> orientations as well, so early feedback is good, so I don't have to
>>> redo them again :)
>>>
>>> Silk screening isn't 100% right, since I still need to rename them
>>> eventually somehow (edit .pcb file directly is probably the easiest
>>> way?)
>>>
>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>> Hi list(s),
>>>>
>>>> Here's my second attempt at routing the previously mailed png of my
>>>> schema.
>>>>
>>>> It was a lot trickier to route then my previous version, but I think it
>>>> worked out!
>>>>
>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>
>>>> Hopefully there's no obvious mistakes and can start working on
>>>> alternative layouts (so it is insert-able in different angles).
>>>>
>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>>>> That said, DRC check passes when I set the copper width/distance to
>>>> 7mil's instead of the current 8 mils.
>>>>
>>>> I'm planning on having these PCB's manufactured by Seeed studio and
>>>> their minimal width is much smaller.
>>>>
>>>> Minimum trace width: 6mil
>>>> Minimum trace/vias/pads space : 6mil
>>>> Minimum silkscreen width : 4mil
>>>> Minimum silkscreen text size : 32mil
>>>>
>>>> I've used a grid size of 10mil and distances of 8 mils, as I didn't
>>>> want
>>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>>> grid
>>>> size of 5 mil's however. Not sure what they mean with a 'minimum
>>>> silkscreen text size' however.
>>>>
>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>> alternative layouts :)
>>>>
>>>>
>>>
>>>
>>
>>
>>
>
>

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