[coreboot] Patch merged into coreboot/master: b6e97b1 Add support for storing POST codes in CMOS

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit b6e97b19ae6a68556838c9801c7824302d72151f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sun Sep 9 19:09:56 2012 -0700

    Add support for storing POST codes in CMOS
    
    This will use 3 bytes of CMOS to keep track of the POST
    code for the current boot while also leaving a record of
    the previous boot.
    
    The active bank is switched early in the bootblock.
    
    Test:
    1) clear cmos
    2) reboot
    3) use "mosys nvram dump" to verify that the first byte
    contains 0x80 and the second byte contains 0xF8
    4) powerd_suspend and then resume
    5) use "mosys nvram dump" to verify that the first byte
    contains 0x81 and the second byte contains 0xFD
    
    Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/1743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Thu Nov  8 09:24:47 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Nov  8 19:40:39 2012, giving +2
See http://review.coreboot.org/1743 for details.

-gerrit