[coreboot] Patch merged into coreboot/master: 313ec9d Sandybridge: Set PEG clock gating

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 313ec9d15bb8c56fc76eb40be920552cb231465e
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Fri Nov 2 14:26:44 2012 -0600

    Sandybridge: Set PEG clock gating
    
    If the PEI System Agent doesn't run PCIe initialization, the PEG
    clock gating will not be setup. Add the PEG clock gating when
    pei_data->pcie_init is 0.
    
    Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    Reviewed-on: http://review.coreboot.org/1827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin at se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Nov 13 20:56:44 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Wed Nov 14 05:39:18 2012, giving +2
See http://review.coreboot.org/1827 for details.

-gerrit