[coreboot] New patch to review for coreboot: 4bb21e7 Add .h files for samsung exynos 5250
Ronald G. Minnich (rminnich@gmail.com)
gerrit at coreboot.org
Tue Nov 27 19:45:58 CET 2012
Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1925
-gerrit
commit 4bb21e7db5c12414b9ba382af4ee404bc46e9e9b
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Tue Nov 27 10:36:06 2012 -0800
Add .h files for samsung exynos 5250
Per a conversation with Stefan, these chip-dependent files are moved
to the src tree, in the manner of other chips (north and southbridge).
Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Signed-off-by: David Hendricks <dhendrix at chromium.org>
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
---
src/Kconfig | 2 +
src/cpu/samsung/exynos5250/ace_sfr.h | 310 ++++++++++++
src/cpu/samsung/exynos5250/ace_sha.h | 41 ++
src/cpu/samsung/exynos5250/adc.h | 27 +
src/cpu/samsung/exynos5250/clk.h | 586 +++++++++++++++++++++
src/cpu/samsung/exynos5250/clock_init.h | 150 ++++++
src/cpu/samsung/exynos5250/cpu.h | 134 +++++
src/cpu/samsung/exynos5250/dmc.h | 211 ++++++++
src/cpu/samsung/exynos5250/dsim.h | 108 ++++
src/cpu/samsung/exynos5250/ehci-s5p.h | 66 +++
src/cpu/samsung/exynos5250/exynos-cpufreq.h | 54 ++
src/cpu/samsung/exynos5250/exynos-tmu.h | 82 +++
src/cpu/samsung/exynos5250/fet.h | 25 +
src/cpu/samsung/exynos5250/fimd.h | 137 +++++
src/cpu/samsung/exynos5250/gpio.h | 482 ++++++++++++++++++
src/cpu/samsung/exynos5250/i2s-regs.h | 146 ++++++
src/cpu/samsung/exynos5250/mmc.h | 27 +
src/cpu/samsung/exynos5250/mshc.h | 31 ++
src/cpu/samsung/exynos5250/periph.h | 71 +++
src/cpu/samsung/exynos5250/pinmux.h | 59 +++
src/cpu/samsung/exynos5250/power.h | 89 ++++
src/cpu/samsung/exynos5250/pwm.h | 27 +
src/cpu/samsung/exynos5250/s5p-dp.h | 513 +++++++++++++++++++
src/cpu/samsung/exynos5250/sata.h | 27 +
src/cpu/samsung/exynos5250/setup.h | 756 ++++++++++++++++++++++++++++
src/cpu/samsung/exynos5250/spi.h | 89 ++++
src/cpu/samsung/exynos5250/sys_proto.h | 27 +
src/cpu/samsung/exynos5250/sysreg.h | 36 ++
src/cpu/samsung/exynos5250/tzpc.h | 52 ++
src/cpu/samsung/exynos5250/uart.h | 71 +++
src/cpu/samsung/exynos5250/watchdog.h | 27 +
31 files changed, 4463 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index fadcbc4..188d0bd 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -204,6 +204,8 @@ config ARCH_X86
bool
default n
+# Warning: The file is included whether or not the if is here.
+# but the if controls how the evaluation occurs.
if ARCH_X86
source src/arch/x86/Kconfig
endif
diff --git a/src/cpu/samsung/exynos5250/ace_sfr.h b/src/cpu/samsung/exynos5250/ace_sfr.h
new file mode 100644
index 0000000..8f1c893
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/ace_sfr.h
@@ -0,0 +1,310 @@
+/*
+ * Header file for Advanced Crypto Engine - SFR definitions
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ACE_SFR_H
+#define __ACE_SFR_H
+
+struct exynos_ace_sfr {
+ unsigned int fc_intstat; /* base + 0 */
+ unsigned int fc_intenset;
+ unsigned int fc_intenclr;
+ unsigned int fc_intpend;
+ unsigned int fc_fifostat;
+ unsigned int fc_fifoctrl;
+ unsigned int fc_global;
+ unsigned int res1;
+ unsigned int fc_brdmas;
+ unsigned int fc_brdmal;
+ unsigned int fc_brdmac;
+ unsigned int res2;
+ unsigned int fc_btdmas;
+ unsigned int fc_btdmal;
+ unsigned int fc_btdmac;
+ unsigned int res3;
+ unsigned int fc_hrdmas;
+ unsigned int fc_hrdmal;
+ unsigned int fc_hrdmac;
+ unsigned int res4;
+ unsigned int fc_pkdmas;
+ unsigned int fc_pkdmal;
+ unsigned int fc_pkdmac;
+ unsigned int fc_pkdmao;
+ unsigned char res5[0x1a0];
+
+ unsigned int aes_control; /* base + 0x200 */
+ unsigned int aes_status;
+ unsigned char res6[0x8];
+ unsigned int aes_in[4];
+ unsigned int aes_out[4];
+ unsigned int aes_iv[4];
+ unsigned int aes_cnt[4];
+ unsigned char res7[0x30];
+ unsigned int aes_key[8];
+ unsigned char res8[0x60];
+
+ unsigned int tdes_control; /* base + 0x300 */
+ unsigned int tdes_status;
+ unsigned char res9[0x8];
+ unsigned int tdes_key[6];
+ unsigned int tdes_iv[2];
+ unsigned int tdes_in[2];
+ unsigned int tdes_out[2];
+ unsigned char res10[0xc0];
+
+ unsigned int hash_control; /* base + 0x400 */
+ unsigned int hash_control2;
+ unsigned int hash_fifo_mode;
+ unsigned int hash_byteswap;
+ unsigned int hash_status;
+ unsigned char res11[0xc];
+ unsigned int hash_msgsize_low;
+ unsigned int hash_msgsize_high;
+ unsigned int hash_prelen_low;
+ unsigned int hash_prelen_high;
+ unsigned int hash_in[16];
+ unsigned int hash_key_in[16];
+ unsigned int hash_iv[8];
+ unsigned char res12[0x30];
+ unsigned int hash_result[8];
+ unsigned char res13[0x20];
+ unsigned int hash_seed[8];
+ unsigned int hash_prng[8];
+ unsigned char res14[0x180];
+
+ unsigned int pka_sfr[5]; /* base + 0x700 */
+};
+
+/* ACE_FC_INT */
+#define ACE_FC_PKDMA (1 << 0)
+#define ACE_FC_HRDMA (1 << 1)
+#define ACE_FC_BTDMA (1 << 2)
+#define ACE_FC_BRDMA (1 << 3)
+#define ACE_FC_PRNG_ERROR (1 << 4)
+#define ACE_FC_MSG_DONE (1 << 5)
+#define ACE_FC_PRNG_DONE (1 << 6)
+#define ACE_FC_PARTIAL_DONE (1 << 7)
+
+/* ACE_FC_FIFOSTAT */
+#define ACE_FC_PKFIFO_EMPTY (1 << 0)
+#define ACE_FC_PKFIFO_FULL (1 << 1)
+#define ACE_FC_HRFIFO_EMPTY (1 << 2)
+#define ACE_FC_HRFIFO_FULL (1 << 3)
+#define ACE_FC_BTFIFO_EMPTY (1 << 4)
+#define ACE_FC_BTFIFO_FULL (1 << 5)
+#define ACE_FC_BRFIFO_EMPTY (1 << 6)
+#define ACE_FC_BRFIFO_FULL (1 << 7)
+
+/* ACE_FC_FIFOCTRL */
+#define ACE_FC_SELHASH_MASK (3 << 0)
+#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */
+#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */
+#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */
+#define ACE_FC_SELBC_MASK (1 << 2)
+#define ACE_FC_SELBC_AES (0 << 2) /* AES */
+#define ACE_FC_SELBC_DES (1 << 2) /* DES */
+
+/* ACE_FC_GLOBAL */
+#define ACE_FC_SSS_RESET (1 << 0)
+#define ACE_FC_DMA_RESET (1 << 1)
+#define ACE_FC_AES_RESET (1 << 2)
+#define ACE_FC_DES_RESET (1 << 3)
+#define ACE_FC_HASH_RESET (1 << 4)
+#define ACE_FC_AXI_ENDIAN_MASK (3 << 6)
+#define ACE_FC_AXI_ENDIAN_LE (0 << 6)
+#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6)
+#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6)
+
+/* Feed control - BRDMA control */
+#define ACE_FC_BRDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_BRDMACFLUSH_ON (1 << 0)
+#define ACE_FC_BRDMACSWAP_ON (1 << 1)
+#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2)
+#define ACE_FC_BRDMACARPROT_OFS (2)
+#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5)
+#define ACE_FC_BRDMACARCACHE_OFS (5)
+
+/* Feed control - BTDMA control */
+#define ACE_FC_BTDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_BTDMACFLUSH_ON (1 << 0)
+#define ACE_FC_BTDMACSWAP_ON (1 << 1)
+#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2)
+#define ACE_FC_BTDMACAWPROT_OFS (2)
+#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5)
+#define ACE_FC_BTDMACAWCACHE_OFS (5)
+
+/* Feed control - HRDMA control */
+#define ACE_FC_HRDMACFLUSH_OFF (0 << 0)
+#define ACE_FC_HRDMACFLUSH_ON (1 << 0)
+#define ACE_FC_HRDMACSWAP_ON (1 << 1)
+#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2)
+#define ACE_FC_HRDMACARPROT_OFS (2)
+#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5)
+#define ACE_FC_HRDMACARCACHE_OFS (5)
+
+/* Feed control - PKDMA control */
+#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3)
+#define ACE_FC_PKDMACDESEND_ON (1 << 2)
+#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1)
+#define ACE_FC_PKDMACFLUSH_ON (1 << 0)
+
+/* Feed control - PKDMA offset */
+#define ACE_FC_SRAMOFFSET_MASK (0xfff)
+
+/* AES control */
+#define ACE_AES_MODE_MASK (1 << 0)
+#define ACE_AES_MODE_ENC (0 << 0)
+#define ACE_AES_MODE_DEC (1 << 0)
+#define ACE_AES_OPERMODE_MASK (3 << 1)
+#define ACE_AES_OPERMODE_ECB (0 << 1)
+#define ACE_AES_OPERMODE_CBC (1 << 1)
+#define ACE_AES_OPERMODE_CTR (2 << 1)
+#define ACE_AES_FIFO_MASK (1 << 3)
+#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */
+#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */
+#define ACE_AES_KEYSIZE_MASK (3 << 4)
+#define ACE_AES_KEYSIZE_128 (0 << 4)
+#define ACE_AES_KEYSIZE_192 (1 << 4)
+#define ACE_AES_KEYSIZE_256 (2 << 4)
+#define ACE_AES_KEYCNGMODE_MASK (1 << 6)
+#define ACE_AES_KEYCNGMODE_OFF (0 << 6)
+#define ACE_AES_KEYCNGMODE_ON (1 << 6)
+#define ACE_AES_SWAP_MASK (0x1f << 7)
+#define ACE_AES_SWAPKEY_OFF (0 << 7)
+#define ACE_AES_SWAPKEY_ON (1 << 7)
+#define ACE_AES_SWAPCNT_OFF (0 << 8)
+#define ACE_AES_SWAPCNT_ON (1 << 8)
+#define ACE_AES_SWAPIV_OFF (0 << 9)
+#define ACE_AES_SWAPIV_ON (1 << 9)
+#define ACE_AES_SWAPDO_OFF (0 << 10)
+#define ACE_AES_SWAPDO_ON (1 << 10)
+#define ACE_AES_SWAPDI_OFF (0 << 11)
+#define ACE_AES_SWAPDI_ON (1 << 11)
+#define ACE_AES_COUNTERSIZE_MASK (3 << 12)
+#define ACE_AES_COUNTERSIZE_128 (0 << 12)
+#define ACE_AES_COUNTERSIZE_64 (1 << 12)
+#define ACE_AES_COUNTERSIZE_32 (2 << 12)
+#define ACE_AES_COUNTERSIZE_16 (3 << 12)
+
+/* AES status */
+#define ACE_AES_OUTRDY_MASK (1 << 0)
+#define ACE_AES_OUTRDY_OFF (0 << 0)
+#define ACE_AES_OUTRDY_ON (1 << 0)
+#define ACE_AES_INRDY_MASK (1 << 1)
+#define ACE_AES_INRDY_OFF (0 << 1)
+#define ACE_AES_INRDY_ON (1 << 1)
+#define ACE_AES_BUSY_MASK (1 << 2)
+#define ACE_AES_BUSY_OFF (0 << 2)
+#define ACE_AES_BUSY_ON (1 << 2)
+
+/* TDES control */
+#define ACE_TDES_MODE_MASK (1 << 0)
+#define ACE_TDES_MODE_ENC (0 << 0)
+#define ACE_TDES_MODE_DEC (1 << 0)
+#define ACE_TDES_OPERMODE_MASK (1 << 1)
+#define ACE_TDES_OPERMODE_ECB (0 << 1)
+#define ACE_TDES_OPERMODE_CBC (1 << 1)
+#define ACE_TDES_SEL_MASK (3 << 3)
+#define ACE_TDES_SEL_DES (0 << 3)
+#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */
+#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */
+#define ACE_TDES_FIFO_MASK (1 << 5)
+#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */
+#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */
+#define ACE_TDES_SWAP_MASK (0xf << 6)
+#define ACE_TDES_SWAPKEY_OFF (0 << 6)
+#define ACE_TDES_SWAPKEY_ON (1 << 6)
+#define ACE_TDES_SWAPIV_OFF (0 << 7)
+#define ACE_TDES_SWAPIV_ON (1 << 7)
+#define ACE_TDES_SWAPDO_OFF (0 << 8)
+#define ACE_TDES_SWAPDO_ON (1 << 8)
+#define ACE_TDES_SWAPDI_OFF (0 << 9)
+#define ACE_TDES_SWAPDI_ON (1 << 9)
+
+/* TDES status */
+#define ACE_TDES_OUTRDY_MASK (1 << 0)
+#define ACE_TDES_OUTRDY_OFF (0 << 0)
+#define ACE_TDES_OUTRDY_ON (1 << 0)
+#define ACE_TDES_INRDY_MASK (1 << 1)
+#define ACE_TDES_INRDY_OFF (0 << 1)
+#define ACE_TDES_INRDY_ON (1 << 1)
+#define ACE_TDES_BUSY_MASK (1 << 2)
+#define ACE_TDES_BUSY_OFF (0 << 2)
+#define ACE_TDES_BUSY_ON (1 << 2)
+
+/* Hash control */
+#define ACE_HASH_ENGSEL_MASK (0xf << 0)
+#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0)
+#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0)
+#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0)
+#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0)
+#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0)
+#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0)
+#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0)
+#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0)
+#define ACE_HASH_ENGSEL_PRNG (0x8 << 0)
+#define ACE_HASH_STARTBIT_ON (1 << 4)
+#define ACE_HASH_USERIV_EN (1 << 5)
+
+/* Hash control 2 */
+#define ACE_HASH_PAUSE_ON (1 << 0)
+
+/* Hash control - FIFO mode */
+#define ACE_HASH_FIFO_MASK (1 << 0)
+#define ACE_HASH_FIFO_OFF (0 << 0)
+#define ACE_HASH_FIFO_ON (1 << 0)
+
+/* Hash control - byte swap */
+#define ACE_HASH_SWAP_MASK (0xf << 0)
+#define ACE_HASH_SWAPKEY_OFF (0 << 0)
+#define ACE_HASH_SWAPKEY_ON (1 << 0)
+#define ACE_HASH_SWAPIV_OFF (0 << 1)
+#define ACE_HASH_SWAPIV_ON (1 << 1)
+#define ACE_HASH_SWAPDO_OFF (0 << 2)
+#define ACE_HASH_SWAPDO_ON (1 << 2)
+#define ACE_HASH_SWAPDI_OFF (0 << 3)
+#define ACE_HASH_SWAPDI_ON (1 << 3)
+
+/* Hash status */
+#define ACE_HASH_BUFRDY_MASK (1 << 0)
+#define ACE_HASH_BUFRDY_OFF (0 << 0)
+#define ACE_HASH_BUFRDY_ON (1 << 0)
+#define ACE_HASH_SEEDSETTING_MASK (1 << 1)
+#define ACE_HASH_SEEDSETTING_OFF (0 << 1)
+#define ACE_HASH_SEEDSETTING_ON (1 << 1)
+#define ACE_HASH_PRNGBUSY_MASK (1 << 2)
+#define ACE_HASH_PRNGBUSY_OFF (0 << 2)
+#define ACE_HASH_PRNGBUSY_ON (1 << 2)
+#define ACE_HASH_PARTIALDONE_MASK (1 << 4)
+#define ACE_HASH_PARTIALDONE_OFF (0 << 4)
+#define ACE_HASH_PARTIALDONE_ON (1 << 4)
+#define ACE_HASH_PRNGDONE_MASK (1 << 5)
+#define ACE_HASH_PRNGDONE_OFF (0 << 5)
+#define ACE_HASH_PRNGDONE_ON (1 << 5)
+#define ACE_HASH_MSGDONE_MASK (1 << 6)
+#define ACE_HASH_MSGDONE_OFF (0 << 6)
+#define ACE_HASH_MSGDONE_ON (1 << 6)
+#define ACE_HASH_PRNGERROR_MASK (1 << 7)
+#define ACE_HASH_PRNGERROR_OFF (0 << 7)
+#define ACE_HASH_PRNGERROR_ON (1 << 7)
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/ace_sha.h b/src/cpu/samsung/exynos5250/ace_sha.h
new file mode 100644
index 0000000..ed4e4d5
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/ace_sha.h
@@ -0,0 +1,41 @@
+/*
+ * Header file for SHA firmware
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ACE_FW_SHA1_H
+#define __ACE_FW_SHA1_H
+
+#define ACE_SHA_TYPE_SHA1 1
+#define ACE_SHA_TYPE_SHA256 2
+
+/**
+ * Computes hash value of input pbuf using ACE
+ *
+ * @param pout A pointer to the output buffer. When complete
+ * 32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ * should allocate at least 32 bytes at pOut in advance.
+ * @param pbuf A pointer to the input buffer
+ * @param buflen Byte length of input buffer
+ * @param hash_type SHA1 or SHA256
+ *
+ * @return 0 Success
+ */
+int ace_sha_hash_digest(uchar *pout, uchar *pbuf, uint buflen, uint hash_type);
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/adc.h b/src/cpu/samsung/exynos5250/adc.h
new file mode 100644
index 0000000..86fcb88
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/adc.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_ADC_H__
+#define __ASM_ARM_ARCH_EXYNOS5_ADC_H__
+
+#include <asm/arch-exynos/adc.h>
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_ADC_H__ */
diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h
new file mode 100644
index 0000000..91b54fd
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/clk.h
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXYNOS5_CLK_H__
+#define __EXYNOS5_CLK_H__
+
+#include <cpu/samsung/exynos-common/clk.h>
+#include <cpu/samsung/exynos5250/pinmux.h>
+
+/*
+ * Set mshci controller instances clock drivder
+ *
+ * @param enum periph_id instance of the mshci controller
+ *
+ * Return 0 if ok else -1
+ */
+int clock_set_mshci(enum periph_id peripheral);
+
+/*
+ * Sets the epll clockrate
+ *
+ * @param rate Required clock rate to the presacaler in Hz
+ *
+ * Return 0 if ok else -1
+ */
+int clock_epll_set_rate(unsigned long rate);
+
+/*
+ * selects the clk source for I2S MCLK
+ */
+void clock_select_i2s_clk_source(void);
+
+/*
+ * Set prescaler division based on input and output frequency
+ * for i2s audio clock
+ *
+ * @param src_frq Source frequency in Hz
+ * @param dst_frq Required MCLK frequency in Hz
+ *
+ * Return 0 if ok else -1
+ */
+int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
+
+/* FIXME(dhendrix): below is stuff from arch/arm/include/asm/arch-exynos5/clock.h
+ (as opposed to the two clk.h files as they were named in u-boot... */
+struct exynos5_clock {
+ unsigned int apll_lock; /* base + 0 */
+ unsigned char res1[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res2[0xf8];
+ unsigned int src_cpu;
+ unsigned char res3[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res4[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res5[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res6[0x1f8];
+ unsigned int gate_sclk_cpu;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res8[0x5f8];
+
+ unsigned int armclk_stopctrl; /* base + 0x1000 */
+ unsigned int atclk_stopctrl;
+ unsigned char res9[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res10[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctr2;
+ unsigned char res11[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res12[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res13[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res14[0x2ce0];
+
+ unsigned int mpll_lock; /* base + 0x4000 */
+ unsigned char res15[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res16[0xf8];
+ unsigned int src_core0;
+ unsigned int src_core1;
+ unsigned char res17[0xf8];
+ unsigned int src_mask_core;
+ unsigned char res18[0x100];
+ unsigned int mux_stat_core1;
+ unsigned char res19[0xf8];
+ unsigned int div_core0;
+ unsigned int div_core1;
+ unsigned int div_sysrgt;
+ unsigned char res20[0xf4];
+ unsigned int div_stat_core0;
+ unsigned int div_stat_core1;
+ unsigned int div_stat_sysrgt;
+ unsigned char res21[0x2f4];
+ unsigned int gate_ip_core;
+ unsigned int gate_ip_sysrgt;
+ unsigned char res22[0xf8];
+ unsigned int clkout_cmu_core;
+ unsigned int clkout_cmu_core_div_stat;
+ unsigned char res23[0x5f8];
+
+ unsigned int dcgidx_map0; /* base + 0x5000 */
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res24[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res25[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res26[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res27[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res28[0x3478];
+
+ unsigned int div_acp; /* base + 0x8500 */
+ unsigned char res29[0xfc];
+ unsigned int div_stat_acp;
+ unsigned char res30[0x1fc];
+ unsigned int gate_ip_acp;
+ unsigned char res31a[0xfc];
+ unsigned int div_syslft;
+ unsigned char res31b[0xc];
+ unsigned int div_stat_syslft;
+ unsigned char res31c[0xc];
+ unsigned int gate_bus_syslft;
+ unsigned char res31d[0xdc];
+ unsigned int clkout_cmu_acp;
+ unsigned int clkout_cmu_acp_div_stat;
+ unsigned char res32[0x38f8];
+
+ unsigned int div_isp0; /* base + 0xc300 */
+ unsigned int div_isp1;
+ unsigned int div_isp2;
+ unsigned char res33[0xf4];
+
+ unsigned int div_stat_isp0; /* base + 0xc400 */
+ unsigned int div_stat_isp1;
+ unsigned int div_stat_isp2;
+ unsigned char res34[0x3f4];
+
+ unsigned int gate_ip_isp0; /* base + 0xc800 */
+ unsigned int gate_ip_isp1;
+ unsigned char res35[0xf8];
+ unsigned int gate_sclk_isp;
+ unsigned char res36[0xc];
+ unsigned int mcuisp_pwr_ctrl;
+ unsigned char res37[0xec];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_div_stat;
+ unsigned char res38[0x3618];
+
+ unsigned int cpll_lock; /* base + 0x10020 */
+ unsigned char res39[0xc];
+ unsigned int epll_lock;
+ unsigned char res40[0xc];
+ unsigned int vpll_lock;
+ unsigned char res41a[0xc];
+ unsigned int gpll_lock;
+ unsigned char res41b[0xcc];
+ unsigned int cpll_con0;
+ unsigned int cpll_con1;
+ unsigned char res42[0x8];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res43[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res44a[0x4];
+ unsigned int gpll_con0;
+ unsigned int gpll_con1;
+ unsigned char res44b[0xb8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned int src_top2;
+ unsigned int src_top3;
+ unsigned int src_gscl;
+ unsigned int src_disp0_0;
+ unsigned int src_disp0_1;
+ unsigned int src_disp1_0;
+ unsigned int src_disp1_1;
+ unsigned char res46[0xc];
+ unsigned int src_mau;
+ unsigned int src_fsys;
+ unsigned char res47[0x8];
+ unsigned int src_peric0;
+ unsigned int src_peric1;
+ unsigned char res48[0x18];
+ unsigned int sclk_src_isp;
+ unsigned char res49[0x9c];
+ unsigned int src_mask_top;
+ unsigned char res50[0xc];
+ unsigned int src_mask_gscl;
+ unsigned int src_mask_disp0_0;
+ unsigned int src_mask_disp0_1;
+ unsigned int src_mask_disp1_0;
+ unsigned int src_mask_disp1_1;
+ unsigned int src_mask_maudio;
+ unsigned char res52[0x8];
+ unsigned int src_mask_fsys;
+ unsigned char res53[0xc];
+ unsigned int src_mask_peric0;
+ unsigned int src_mask_peric1;
+ unsigned char res54[0x18];
+ unsigned int src_mask_isp;
+ unsigned char res55[0x9c];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned int mux_stat_top2;
+ unsigned int mux_stat_top3;
+ unsigned char res56[0xf0];
+ unsigned int div_top0;
+ unsigned int div_top1;
+ unsigned char res57[0x8];
+ unsigned int div_gscl;
+ unsigned int div_disp0_0;
+ unsigned int div_disp0_1;
+ unsigned int div_disp1_0;
+ unsigned int div_disp1_1;
+ unsigned char res59[0x8];
+ unsigned int div_gen;
+ unsigned char res60[0x4];
+ unsigned int div_mau;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peric0;
+ unsigned int div_peric1;
+ unsigned int div_peric2;
+ unsigned int div_peric3;
+ unsigned int div_peric4;
+ unsigned int div_peric5;
+ unsigned char res61[0x10];
+ unsigned int sclk_div_isp;
+ unsigned char res62[0xc];
+ unsigned int div2_ratio0;
+ unsigned int div2_ratio1;
+ unsigned char res63[0x8];
+ unsigned int div4_ratio;
+ unsigned char res64[0x6c];
+ unsigned int div_stat_top0;
+ unsigned int div_stat_top1;
+ unsigned char res65[0x8];
+ unsigned int div_stat_gscl;
+ unsigned int div_stat_disp0_0;
+ unsigned int div_stat_disp0_1;
+ unsigned int div_stat_disp1_0;
+ unsigned int div_stat_disp1_1;
+ unsigned char res67[0x8];
+ unsigned int div_stat_gen;
+ unsigned char res68[0x4];
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peric0;
+ unsigned int div_stat_peric1;
+ unsigned int div_stat_peric2;
+ unsigned int div_stat_peric3;
+ unsigned int div_stat_peric4;
+ unsigned int div_stat_peric5;
+ unsigned char res69[0x10];
+ unsigned int sclk_div_stat_isp;
+ unsigned char res70[0xc];
+ unsigned int div2_stat0;
+ unsigned int div2_stat1;
+ unsigned char res71[0x8];
+ unsigned int div4_stat;
+ unsigned char res72[0x180];
+ unsigned int gate_top_sclk_disp0;
+ unsigned int gate_top_sclk_disp1;
+ unsigned int gate_top_sclk_gen;
+ unsigned char res74[0xc];
+ unsigned int gate_top_sclk_mau;
+ unsigned int gate_top_sclk_fsys;
+ unsigned char res75[0xc];
+ unsigned int gate_top_sclk_peric;
+ unsigned char res76[0x1c];
+ unsigned int gate_top_sclk_isp;
+ unsigned char res77[0xac];
+ unsigned int gate_ip_gscl;
+ unsigned int gate_ip_disp0;
+ unsigned int gate_ip_disp1;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_gen;
+ unsigned char res79[0xc];
+ unsigned int gate_ip_fsys;
+ unsigned char res80[0x4];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peric;
+ unsigned char res81[0xc];
+ unsigned int gate_ip_peris;
+ unsigned char res82[0x1c];
+ unsigned int gate_block;
+ unsigned char res83[0x7c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res84[0x37f8];
+
+ unsigned int src_lex; /* base + 0x14200 */
+ unsigned char res85[0x1fc];
+ unsigned int mux_stat_lex;
+ unsigned char res85b[0xfc];
+ unsigned int div_lex;
+ unsigned char res86[0xfc];
+ unsigned int div_stat_lex;
+ unsigned char res87[0x1fc];
+ unsigned int gate_ip_lex;
+ unsigned char res88[0x1fc];
+ unsigned int clkout_cmu_lex;
+ unsigned int clkout_cmu_lex_div_stat;
+ unsigned char res89[0x3af8];
+
+ unsigned int div_r0x; /* base + 0x18500 */
+ unsigned char res90[0xfc];
+ unsigned int div_stat_r0x;
+ unsigned char res91[0x1fc];
+ unsigned int gate_ip_r0x;
+ unsigned char res92[0x1fc];
+ unsigned int clkout_cmu_r0x;
+ unsigned int clkout_cmu_r0x_div_stat;
+ unsigned char res94[0x3af8];
+
+ unsigned int div_r1x; /* base + 0x1c500 */
+ unsigned char res95[0xfc];
+ unsigned int div_stat_r1x;
+ unsigned char res96[0x1fc];
+ unsigned int gate_ip_r1x;
+ unsigned char res97[0x1fc];
+ unsigned int clkout_cmu_r1x;
+ unsigned int clkout_cmu_r1x_div_stat;
+ unsigned char res98[0x3608];
+
+ unsigned int bpll_lock; /* base + 0x2000c */
+ unsigned char res99[0xfc];
+ unsigned int bpll_con0;
+ unsigned int bpll_con1;
+ unsigned char res100[0xe8];
+ unsigned int src_cdrex;
+ unsigned char res101[0x1fc];
+ unsigned int mux_stat_cdrex;
+ unsigned char res102[0xfc];
+ unsigned int div_cdrex;
+ unsigned int div_cdrex2;
+ unsigned char res103[0xf8];
+ unsigned int div_stat_cdrex;
+ unsigned char res104[0x2fc];
+ unsigned int gate_ip_cdrex;
+ unsigned char res105[0xc];
+ unsigned int c2c_monitor;
+ unsigned int dmc_pwr_ctrl;
+ unsigned char res106[0x4];
+ unsigned int drex2_pause;
+ unsigned char res107[0xe0];
+ unsigned int clkout_cmu_cdrex;
+ unsigned int clkout_cmu_cdrex_div_stat;
+ unsigned char res108[0x8];
+ unsigned int lpddr3phy_ctrl;
+ unsigned char res109a[0xc];
+ unsigned int lpddr3phy_con3;
+ unsigned int pll_div2_sel;
+ unsigned char res109b[0xf5e4];
+};
+
+struct exynos5_mct_regs {
+ uint32_t mct_cfg;
+ uint8_t reserved0[0xfc];
+ uint32_t g_cnt_l;
+ uint32_t g_cnt_u;
+ uint8_t reserved1[0x8];
+ uint32_t g_cnt_wstat;
+ uint8_t reserved2[0xec];
+ uint32_t g_comp0_l;
+ uint32_t g_comp0_u;
+ uint32_t g_comp0_addr_incr;
+ uint8_t reserved3[0x4];
+ uint32_t g_comp1_l;
+ uint32_t g_comp1_u;
+ uint32_t g_comp1_addr_incr;
+ uint8_t reserved4[0x4];
+ uint32_t g_comp2_l;
+ uint32_t g_comp2_u;
+ uint32_t g_comp2_addr_incr;
+ uint8_t reserved5[0x4];
+ uint32_t g_comp3_l;
+ uint32_t g_comp3_u;
+ uint32_t g_comp3_addr_incr;
+ uint8_t reserved6[0x4];
+ uint32_t g_tcon;
+ uint32_t g_int_cstat;
+ uint32_t g_int_enb;
+ uint32_t g_wstat;
+ uint8_t reserved7[0xb0];
+ uint32_t l0_tcntb;
+ uint32_t l0_tcnto;
+ uint32_t l0_icntb;
+ uint32_t l0_icnto;
+ uint32_t l0_frcntb;
+ uint32_t l0_frcnto;
+ uint8_t reserved8[0x8];
+ uint32_t l0_tcon;
+ uint8_t reserved9[0xc];
+ uint32_t l0_int_cstat;
+ uint32_t l0_int_enb;
+ uint8_t reserved10[0x8];
+ uint32_t l0_wstat;
+ uint8_t reserved11[0xbc];
+ uint32_t l1_tcntb;
+ uint32_t l1_tcnto;
+ uint32_t l1_icntb;
+ uint32_t l1_icnto;
+ uint32_t l1_frcntb;
+ uint32_t l1_frcnto;
+ uint8_t reserved12[0x8];
+ uint32_t l1_tcon;
+ uint8_t reserved13[0xc];
+ uint32_t l1_int_cstat;
+ uint32_t l1_int_enb;
+ uint8_t reserved14[0x8];
+ uint32_t l1_wstat;
+};
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
+#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */
+#define TIMEOUT_EPLL_LOCK 1000
+
+#define AUDIO_0_RATIO_MASK 0x0f
+#define AUDIO_1_RATIO_MASK 0x0f
+
+#define CLK_SRC_PERIC1 0x254
+#define AUDIO1_SEL_MASK 0xf
+#define CLK_SRC_AUDIOCDCLK1 0x0
+#define CLK_SRC_XXTI 0x1
+#define CLK_SRC_SCLK_EPLL 0x7
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK 0x1ff
+#define EPLL_CON0_PDIV_MASK 0x3f
+#define EPLL_CON0_SDIV_MASK 0x7
+#define EPLL_CON0_LOCKED_SHIFT 29
+#define EPLL_CON0_MDIV_SHIFT 16
+#define EPLL_CON0_PDIV_SHIFT 8
+#define EPLL_CON0_SDIV_SHIFT 0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
+#define EPLL_CON0_LOCK_DET_EN_MASK 1
+
+/* structure for epll configuration used in audio clock configuration */
+struct st_epll_con_val {
+ unsigned int freq_out; /* frequency out */
+ unsigned int en_lock_det; /* enable lock detect */
+ unsigned int m_div; /* m divider value */
+ unsigned int p_div; /* p divider value */
+ unsigned int s_div; /* s divider value */
+ unsigned int k_dsm; /* k value of delta signal modulator */
+};
+
+/**
+ * Low-level function to set the clock pre-ratio for a peripheral
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param divisor New divisor for this peripheral's clock
+ */
+void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
+
+/**
+ * Low-level function to set the clock ratio for a peripheral
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param divisor New divisor for this peripheral's clock
+ */
+void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
+
+/**
+ * Low-level function that selects the best clock scalars for a given rate and
+ * sets up the given peripheral's clock accordingly.
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param rate Desired clock rate in Hz
+ *
+ * @return zero on success, negative on error
+ */
+int clock_set_rate(enum periph_id periph_id, unsigned int rate);
+
+/**
+ * Decode a peripheral ID from a device node.
+ *
+ * Drivers should always use this function since the actual means of
+ * encoding this information may change in the future as fdt support for
+ * exynos evolves.
+ *
+ * @param blob FDT blob to read from
+ * @param node Node containing the information
+ */
+int clock_decode_periph_id(const void *blob, int node);
+
+/* Clock gate unused IP */
+void clock_gate(void);
+
+enum ddr_mode;
+enum mem_manuf;
+
+const char *clock_get_mem_type_name(enum ddr_mode mem_type);
+
+const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf);
+
+/*
+ * TODO(sjg at chromium.org): Remove this when we have more SPL space.
+ * At present we are using 14148 of 14336 bytes. If we change this function
+ * to be exported in SPL, we go over the edge.
+ */
+/* TODO(dhendrix): do we still need this ifndef? */
+//#ifndef CONFIG_SPL_BUILD
+/**
+ * Get the required memory type and speed (Main U-Boot version).
+ *
+ * This should use the device tree. For now we cannot since this function is
+ * called before the FDT is available.
+ *
+ * @param mem_type Returns memory type
+ * @param frequency_mhz Returns memory speed in MHz
+ * @param arm_freq Returns ARM clock speed in MHz
+ * @param mem_manuf Return Memory Manufacturer name
+ * @return 0 if all ok (if not, this function currently does not return)
+ */
+int clock_get_mem_selection(enum ddr_mode *mem_type,
+ unsigned *frequency_mhz, unsigned *arm_freq,
+ enum mem_manuf *mem_manuf);
+//#endif /* CONFIG_SPL_BUILD */
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h
new file mode 100644
index 0000000..57a0fe6
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/clock_init.h
@@ -0,0 +1,150 @@
+/*
+ * Clock initialization routines
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS_CLOCK_INIT_H
+#define __EXYNOS_CLOCK_INIT_H
+
+enum {
+ MEM_TIMINGS_MSR_COUNT = 4,
+};
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+ unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
+
+ unsigned apll_mdiv;
+ unsigned apll_pdiv;
+ unsigned apll_sdiv;
+
+ unsigned arm2_ratio;
+ unsigned apll_ratio;
+ unsigned pclk_dbg_ratio;
+ unsigned atb_ratio;
+ unsigned periph_ratio;
+ unsigned acp_ratio;
+ unsigned cpud_ratio;
+ unsigned arm_ratio;
+};
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+ enum mem_manuf mem_manuf; /* Memory manufacturer */
+ enum ddr_mode mem_type; /* Memory type */
+ unsigned frequency_mhz; /* Frequency of memory in MHz */
+
+ /* Here follow the timing parameters for the selected memory */
+ uint8_t apll_mdiv;
+ uint8_t apll_pdiv;
+ uint8_t apll_sdiv;
+ uint8_t mpll_mdiv;
+ uint8_t mpll_pdiv;
+ uint8_t mpll_sdiv;
+ uint8_t cpll_mdiv;
+ uint8_t cpll_pdiv;
+ uint8_t cpll_sdiv;
+ uint8_t gpll_pdiv;
+ uint16_t gpll_mdiv;
+ uint8_t gpll_sdiv;
+ uint8_t epll_mdiv;
+ uint8_t epll_pdiv;
+ uint8_t epll_sdiv;
+ uint8_t vpll_mdiv;
+ uint8_t vpll_pdiv;
+ uint8_t vpll_sdiv;
+ uint8_t bpll_mdiv;
+ uint8_t bpll_pdiv;
+ uint8_t bpll_sdiv;
+ uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */
+ uint8_t pclk_cdrex_ratio;
+ unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+ unsigned timing_ref;
+ unsigned timing_row;
+ unsigned timing_data;
+ unsigned timing_power;
+
+ /* DQS, DQ, DEBUG offsets */
+ unsigned phy0_dqs;
+ unsigned phy1_dqs;
+ unsigned phy0_dq;
+ unsigned phy1_dq;
+ uint8_t phy0_tFS;
+ uint8_t phy1_tFS;
+ uint8_t phy0_pulld_dqs;
+ uint8_t phy1_pulld_dqs;
+
+ uint8_t lpddr3_ctrl_phy_reset;
+ uint8_t ctrl_start_point;
+ uint8_t ctrl_inc;
+ uint8_t ctrl_start;
+ uint8_t ctrl_dll_on;
+ uint8_t ctrl_ref;
+
+ uint8_t ctrl_force;
+ uint8_t ctrl_rdlat;
+ uint8_t ctrl_bstlen;
+
+ uint8_t fp_resync;
+ uint8_t iv_size;
+ uint8_t dfi_init_start;
+ uint8_t aref_en;
+
+ uint8_t rd_fetch;
+
+ uint8_t zq_mode_dds;
+ uint8_t zq_mode_term;
+ uint8_t zq_mode_noterm; /* 1 to allow termination disable */
+
+ unsigned memcontrol;
+ unsigned memconfig;
+
+ unsigned membaseconfig0;
+ unsigned membaseconfig1;
+ unsigned prechconfig_tp_cnt;
+ unsigned dpwrdn_cyc;
+ unsigned dsref_cyc;
+ unsigned concontrol;
+ /* Channel and Chip Selection */
+ uint8_t dmc_channels; /* number of memory channels */
+ uint8_t chips_per_channel; /* number of chips per channel */
+ uint8_t chips_to_configure; /* number of chips to configure */
+ uint8_t send_zq_init; /* 1 to send this command */
+ unsigned impedance; /* drive strength impedeance */
+ uint8_t gate_leveling_enable; /* check gate leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * This function can be called from SPL or the main U-Boot.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *clock_get_mem_timings(void);
+
+/*
+ * Initialize clock for the device
+ */
+void system_clock_init(void);
+#endif
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
new file mode 100644
index 0000000..f6d7c65
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS5250_CPU_H
+#define _EXYNOS5250_CPU_H
+
+#include <cpu/samsung/exynos-common/cpu.h>
+
+/* EXYNOS5 */
+#define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */
+#define EXYNOS5_PRO_ID 0x10000000
+#define EXYNOS5_CLOCK_BASE 0x10010000
+#define EXYNOS5_POWER_BASE 0x10040000
+#define EXYNOS5_SWRESET 0x10040400
+#define EXYNOS5_SYSREG_BASE 0x10050000
+#define EXYNOS5_TZPC1_DECPROT1SET 0x10110810
+#define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000
+#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_ACE_SFR_BASE 0x10830000
+#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
+#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
+#define EXYNOS5_GPIO_PART4_BASE 0x10D10000 /* V00..V37 */
+#define EXYNOS5_GPIO_PART5_BASE 0x10D100C0 /* V40..V47 */
+#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE 0x11400000 /* A00..Y67 */
+#define EXYNOS5_GPIO_PART2_BASE 0x11400c00 /* X00..X37 */
+#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5_USBPHY_BASE 0x12130000
+#define EXYNOS5_USBOTG_BASE 0x12140000
+
+#ifndef CONFIG_OF_CONTROL
+#define EXYNOS5_MMC_BASE 0x12200000
+#define EXYNOS5_MSHC_BASE 0x12240000
+#endif
+
+#define EXYNOS5_SROMC_BASE 0x12250000
+#define EXYNOS5_UART_BASE 0x12C00000
+
+#define EXYNOS5_SPI1_BASE 0x12D30000
+#ifndef CONFIG_OF_CONTROL
+#define EXYNOS5_I2C_BASE 0x12C60000
+#define EXYNOS5_SPI_BASE 0x12D20000
+#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE 0x131A0000
+#endif
+#define EXYNOS5_I2S_BASE 0x12D60000
+#define EXYNOS5_GPIO_PART3_BASE 0x13400000 /* E00..H17 */
+#define EXYNOS5_FIMD_BASE 0x14400000
+#define EXYNOS5_DISP1_CTRL_BASE 0x14420000
+#define EXYNOS5_MIPI_DSI1_BASE 0x14500000
+
+#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
+
+/* Compatibility defines */
+#define EXYNOS_POWER_BASE EXYNOS5_POWER_BASE
+
+/* Marker values stored at the bottom of IRAM stack by SPL */
+#define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET 0x10000
+
+#ifndef __ASSEMBLY__
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int samsung_get_base_##device(void) \
+{ \
+ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
+SAMSUNG_BASE(dsim, MIPI_DSI1_BASE)
+SAMSUNG_BASE(disp_ctrl, DISP1_CTRL_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
+SAMSUNG_BASE(gpio_part5, GPIO_PART5_BASE)
+SAMSUNG_BASE(gpio_part6, GPIO_PART6_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+
+#ifndef CONFIG_OF_CONTROL
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(mshci, MSHC_BASE)
+#endif
+
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
+SAMSUNG_BASE(spi1, SPI1_BASE)
+#ifndef CONFIG_OF_CONTROL
+SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+#endif
+#endif
+
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#define EXYNOS_I2C_MAX_CONTROLLERS 8
+
+/* helper function to map mmio address to peripheral id */
+enum periph_id exynos5_get_periph_id(unsigned base_addr);
+
+#endif /* _EXYNOS5250_CPU_H */
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
new file mode 100644
index 0000000..d1dfbb1
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -0,0 +1,211 @@
+#ifndef __DMC_H__
+#define __DMC_H__
+
+#ifndef __ASSEMBLER__
+struct exynos5_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+ unsigned int directcmd;
+ unsigned int prechconfig;
+ unsigned int phycontrol0;
+ unsigned char res1[0xc];
+ unsigned int pwrdnconfig;
+ unsigned int timingpzq;
+ unsigned int timingref;
+ unsigned int timingrow;
+ unsigned int timingdata;
+ unsigned int timingpower;
+ unsigned int phystatus;
+ unsigned char res2[0x4];
+ unsigned int chipstatus_ch0;
+ unsigned int chipstatus_ch1;
+ unsigned char res3[0x4];
+ unsigned int mrstatus;
+ unsigned char res4[0x8];
+ unsigned int qoscontrol0;
+ unsigned char resr5[0x4];
+ unsigned int qoscontrol1;
+ unsigned char res6[0x4];
+ unsigned int qoscontrol2;
+ unsigned char res7[0x4];
+ unsigned int qoscontrol3;
+ unsigned char res8[0x4];
+ unsigned int qoscontrol4;
+ unsigned char res9[0x4];
+ unsigned int qoscontrol5;
+ unsigned char res10[0x4];
+ unsigned int qoscontrol6;
+ unsigned char res11[0x4];
+ unsigned int qoscontrol7;
+ unsigned char res12[0x4];
+ unsigned int qoscontrol8;
+ unsigned char res13[0x4];
+ unsigned int qoscontrol9;
+ unsigned char res14[0x4];
+ unsigned int qoscontrol10;
+ unsigned char res15[0x4];
+ unsigned int qoscontrol11;
+ unsigned char res16[0x4];
+ unsigned int qoscontrol12;
+ unsigned char res17[0x4];
+ unsigned int qoscontrol13;
+ unsigned char res18[0x4];
+ unsigned int qoscontrol14;
+ unsigned char res19[0x4];
+ unsigned int qoscontrol15;
+ unsigned char res20[0x14];
+ unsigned int ivcontrol;
+ unsigned int wrtra_config;
+ unsigned int rdlvl_config;
+ unsigned char res21[0x8];
+ unsigned int brbrsvconfig;
+ unsigned int brbqosconfig;
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned char res22[0xc];
+ unsigned int wrlvl_config;
+ unsigned char res23[0xc];
+ unsigned int perevcontrol;
+ unsigned int perev0config;
+ unsigned int perev1config;
+ unsigned int perev2config;
+ unsigned int perev3config;
+ unsigned char res24[0xdebc];
+ unsigned int pmnc_ppc_a;
+ unsigned char res25[0xc];
+ unsigned int cntens_ppc_a;
+ unsigned char res26[0xc];
+ unsigned int cntenc_ppc_a;
+ unsigned char res27[0xc];
+ unsigned int intens_ppc_a;
+ unsigned char res28[0xc];
+ unsigned int intenc_ppc_a;
+ unsigned char res29[0xc];
+ unsigned int flag_ppc_a;
+ unsigned char res30[0xac];
+ unsigned int ccnt_ppc_a;
+ unsigned char res31[0xc];
+ unsigned int pmcnt0_ppc_a;
+ unsigned char res32[0xc];
+ unsigned int pmcnt1_ppc_a;
+ unsigned char res33[0xc];
+ unsigned int pmcnt2_ppc_a;
+ unsigned char res34[0xc];
+ unsigned int pmcnt3_ppc_a;
+};
+
+struct exynos5_phy_control {
+ unsigned int phy_con0;
+ unsigned int phy_con1;
+ unsigned int phy_con2;
+ unsigned int phy_con3;
+ unsigned int phy_con4;
+ unsigned char res1[4];
+ unsigned int phy_con6;
+ unsigned char res2[4];
+ unsigned int phy_con8;
+ unsigned int phy_con9;
+ unsigned int phy_con10;
+ unsigned char res3[4];
+ unsigned int phy_con12;
+ unsigned int phy_con13;
+ unsigned int phy_con14;
+ unsigned int phy_con15;
+ unsigned int phy_con16;
+ unsigned char res4[4];
+ unsigned int phy_con17;
+ unsigned int phy_con18;
+ unsigned int phy_con19;
+ unsigned int phy_con20;
+ unsigned int phy_con21;
+ unsigned int phy_con22;
+ unsigned int phy_con23;
+ unsigned int phy_con24;
+ unsigned int phy_con25;
+ unsigned int phy_con26;
+ unsigned int phy_con27;
+ unsigned int phy_con28;
+ unsigned int phy_con29;
+ unsigned int phy_con30;
+ unsigned int phy_con31;
+ unsigned int phy_con32;
+ unsigned int phy_con33;
+ unsigned int phy_con34;
+ unsigned int phy_con35;
+ unsigned int phy_con36;
+ unsigned int phy_con37;
+ unsigned int phy_con38;
+ unsigned int phy_con39;
+ unsigned int phy_con40;
+ unsigned int phy_con41;
+ unsigned int phy_con42;
+};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT 28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
+#endif
+#endif
diff --git a/src/cpu/samsung/exynos5250/dsim.h b/src/cpu/samsung/exynos5250/dsim.h
new file mode 100644
index 0000000..38a4c98
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/dsim.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for Exynos5 MIPI-DSIM
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_DSIM_H__
+#define __EXYNOS5_DSIM_H__
+
+/* DSIM register map */
+struct exynos5_dsim {
+ unsigned int status;
+ unsigned int swrst;
+ unsigned int clkctrl;
+ unsigned int timeout;
+ unsigned int config;
+ unsigned int escmode;
+ unsigned int mdresol;
+ unsigned int mvporch;
+ unsigned int mhporch;
+ unsigned int msync;
+ unsigned int sdresol;
+ unsigned int intsrc;
+ unsigned int intmsk;
+ unsigned int pkthdr;
+ unsigned int payload;
+ unsigned int rxfifo;
+ unsigned int res1;
+ unsigned int fifoctrl;
+ unsigned int res2;
+ unsigned int pllctrl;
+ unsigned int plltmr;
+ unsigned int phyacchr;
+ unsigned int phyacchr1;
+};
+
+#define ENABLE 1
+#define DISABLE 0
+
+#define DSIM_SWRST (1 << 0)
+#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5)
+#define DATA_LANE_0_EN (1 << 0)
+#define DATA_LANE_1_EN (1 << 1)
+#define DATA_LANE_2_EN (1 << 2)
+#define DATA_LANE_3_EN (1 << 3)
+#define CLK_LANE_EN (1 << 4)
+#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \
+ DATA_LANE_1_EN | \
+ DATA_LANE_2_EN | \
+ DATA_LANE_3_EN
+#define MAIN_PIX_FORMAT_OFFSET 12
+#define RGB_565_16_BIT 0x4
+#define VIDEO_MODE (1 << 25)
+#define BURST_MODE (1 << 26)
+
+
+#define DSIM_PHYACCHR_AFC_EN (1 << 14)
+#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
+
+#define DSIM_PLLCTRL_PMS_OFFSET 1
+#define DSIM_FREQ_BAND_OFFSET 24
+
+#define LANE_ESC_CLK_EN_ALL (0x1f << 19)
+#define BYTE_CLK_EN (1 << 24)
+#define DSIM_ESC_CLK_EN (1 << 28)
+#define TXREQUEST_HS_CLK_ON (1 << 31)
+
+#define LP_MODE_ENABLE (1 << 7)
+#define STOP_STATE_CNT_OFFSET 21
+
+#define MAIN_VBP_OFFSET 0
+#define STABLE_VFP_OFFSET 16
+#define CMD_ALLOW_OFFSET 28
+
+#define MAIN_HBP_OFFSET 0
+#define MAIN_HFP_OFFSET 16
+
+#define MAIN_HSA_OFFSET 0
+#define MAIN_VSA_OFFSET 22
+
+#define MAIN_STANDBY (1 << 31)
+#define MAIN_VRESOL_OFFSET 16
+#define MAIN_HRESOL_OFFSET 0
+
+#define SFR_FIFO_EMPTY (1 << 29)
+
+#define DSIM_PLL_EN_SHIFT (1 << 23)
+#define PLL_STABLE (1 << 31)
+
+#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK (1 << 8)
+#define DSIM_TX_READY_HS_CLK (1 << 10)
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/ehci-s5p.h b/src/cpu/samsung/exynos5250/ehci-s5p.h
new file mode 100644
index 0000000..56abb60
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/ehci-s5p.h
@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Vivek Gautam <gautam.vivek at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+
+#define CLK_24MHZ 5
+
+#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
+#define HOST_CTRL0_COMMONON_N (1 << 9)
+#define HOST_CTRL0_SIDDQ (1 << 6)
+#define HOST_CTRL0_FORCESLEEP (1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (1 << 3)
+#define HOST_CTRL0_UTMISWRST (1 << 2)
+#define HOST_CTRL0_LINKSWRST (1 << 1)
+#define HOST_CTRL0_PHYSWRST (1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN (1 << 29)
+#define EHCICTRL_ENAINCR4 (1 << 28)
+#define EHCICTRL_ENAINCR8 (1 << 27)
+#define EHCICTRL_ENAINCR16 (1 << 26)
+
+/* Register map for PHY control */
+struct usb_phy {
+ unsigned int usbphyctrl0;
+ unsigned int usbphytune0;
+ unsigned int reserved1[2];
+ unsigned int hsicphyctrl1;
+ unsigned int hsicphytune1;
+ unsigned int reserved2[2];
+ unsigned int hsicphyctrl2;
+ unsigned int hsicphytune2;
+ unsigned int reserved3[2];
+ unsigned int ehcictrl;
+ unsigned int ohcictrl;
+ unsigned int usbotgsys;
+ unsigned int reserved4;
+ unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
diff --git a/src/cpu/samsung/exynos5250/exynos-cpufreq.h b/src/cpu/samsung/exynos5250/exynos-cpufreq.h
new file mode 100644
index 0000000..1c28e77
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/exynos-cpufreq.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS - CPU frequency scaling support
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Define various levels of ARM frequency */
+enum cpufreq_level {
+ CPU_FREQ_L200, /* 200 MHz */
+ CPU_FREQ_L300, /* 300 MHz */
+ CPU_FREQ_L400, /* 400 MHz */
+ CPU_FREQ_L500, /* 500 MHz */
+ CPU_FREQ_L600, /* 600 MHz */
+ CPU_FREQ_L700, /* 700 MHz */
+ CPU_FREQ_L800, /* 800 MHz */
+ CPU_FREQ_L900, /* 900 MHz */
+ CPU_FREQ_L1000, /* 1000 MHz */
+ CPU_FREQ_L1100, /* 1100 MHz */
+ CPU_FREQ_L1200, /* 1200 MHz */
+ CPU_FREQ_L1300, /* 1300 MHz */
+ CPU_FREQ_L1400, /* 1400 MHz */
+ CPU_FREQ_L1500, /* 1500 MHz */
+ CPU_FREQ_L1600, /* 1600 MHz */
+ CPU_FREQ_L1700, /* 1700 MHz */
+ CPU_FREQ_LCOUNT,
+};
+
+/*
+ * Initialize ARM frequency scaling
+ *
+ * @param blob FDT blob
+ * @return int value, 0 for success
+ */
+int exynos5250_cpufreq_init(const void *blob);
+
+/*
+ * Switch ARM frequency to new level
+ *
+ * @param new_freq_level enum cpufreq_level, states new frequency
+ * @return int value, 0 for success
+ */
+int exynos5250_set_frequency(enum cpufreq_level new_freq_level);
diff --git a/src/cpu/samsung/exynos5250/exynos-tmu.h b/src/cpu/samsung/exynos5250/exynos-tmu.h
new file mode 100644
index 0000000..ad9e394
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/exynos-tmu.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Akshay Saraswat <Akshay.s at samsung.com>
+ *
+ * EXYNOS - Thermal Management Unit
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_THERMAL_H
+#define __ASM_ARCH_THERMAL_H
+
+struct tmu_reg {
+ unsigned triminfo;
+ unsigned rsvd1;
+ unsigned rsvd2;
+ unsigned rsvd3;
+ unsigned rsvd4;
+ unsigned triminfo_control;
+ unsigned rsvd5;
+ unsigned rsvd6;
+ unsigned tmu_control;
+ unsigned rsvd7;
+ unsigned tmu_status;
+ unsigned sampling_internal;
+ unsigned counter_value0;
+ unsigned counter_value1;
+ unsigned rsvd8;
+ unsigned rsvd9;
+ unsigned current_temp;
+ unsigned rsvd10;
+ unsigned rsvd11;
+ unsigned rsvd12;
+ unsigned threshold_temp_rise;
+ unsigned threshold_temp_fall;
+ unsigned rsvd13;
+ unsigned rsvd14;
+ unsigned past_temp3_0;
+ unsigned past_temp7_4;
+ unsigned past_temp11_8;
+ unsigned past_temp15_12;
+ unsigned inten;
+ unsigned intstat;
+ unsigned intclear;
+ unsigned rsvd15;
+ unsigned emul_con;
+};
+
+enum tmu_status_t {
+ TMU_STATUS_INIT = 0,
+ TMU_STATUS_NORMAL,
+ TMU_STATUS_WARNING,
+ TMU_STATUS_TRIPPED,
+};
+
+/*
+ * Monitors status of the TMU device and exynos temperature
+ *
+ * @param temp pointer to the current temperature value
+ * @return enum tmu_status_t value, code indicating event to execute
+ * and -1 on error
+ */
+enum tmu_status_t tmu_monitor(int *temp);
+
+/*
+ * Initialize TMU device
+ *
+ * @param blob FDT blob
+ * @return int value, 0 for success
+ */
+int tmu_init(const void *blob);
+#endif
diff --git a/src/cpu/samsung/exynos5250/fet.h b/src/cpu/samsung/exynos5250/fet.h
new file mode 100644
index 0000000..e76bcbf
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/fet.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_FET_H
+#define __ASM_ARM_ARCH_EXYNOS5_FET_H
+
+/* The FET IDs for TPS65090 PMU chip. */
+enum {
+ FET_ID_BL = 1
+ FET_ID_VIDEO,
+ FET_ID_WWAN,
+ FET_ID_SDCARD,
+ FET_ID_CAMOUT,
+ FET_ID_LCD,
+ FET_ID_TS
+};
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/fimd.h b/src/cpu/samsung/exynos5250/fimd.h
new file mode 100644
index 0000000..a46ad5a
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/fimd.h
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for Exynos5 FIMD
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_FIMD_H__
+#define __EXYNOS5_FIMD_H__
+
+/* FIMD register map */
+struct exynos5_fimd {
+ /* This is an incomplete list. Add registers as and when required */
+ unsigned int vidcon0;
+ unsigned char res1[0x1c];
+ unsigned int wincon0;
+ unsigned int wincon1;
+ unsigned int wincon2;
+ unsigned int wincon3;
+ unsigned int wincon4;
+ unsigned int shadowcon;
+ unsigned char res2[0x8];
+ unsigned int vidosd0a;
+ unsigned int vidosd0b;
+ unsigned int vidosd0c;
+ unsigned char res3[0x54];
+ unsigned int vidw00add0b0;
+ unsigned char res4[0x2c];
+ unsigned int vidw00add1b0;
+ unsigned char res5[0x2c];
+ unsigned int vidw00add2;
+ unsigned char res6[0x3c];
+ unsigned int w1keycon0;
+ unsigned int w1keycon1;
+ unsigned int w2keycon0;
+ unsigned int w2keycon1;
+ unsigned int w3keycon0;
+ unsigned int w3keycon1;
+ unsigned int w4keycon0;
+ unsigned int w4keycon1;
+ unsigned char res7[0x20];
+ unsigned int win0map;
+ unsigned char res8[0xdc];
+ unsigned int blendcon;
+ unsigned char res9[0x18];
+ unsigned int dpclkcon;
+};
+
+#define W0_SHADOW_PROTECT (0x1 << 10)
+#define COMPKEY_F 0xffffff
+#define ENVID_F_ON (0x1 << 0)
+#define ENVID_ON (0x1 << 1)
+#define CLKVAL_F 0xb
+#define CLKVAL_F_OFFSET 6
+
+/*
+ * Structure containing display panel specific data for FIMD
+ */
+struct exynos5_fimd_panel {
+ unsigned int is_dp:1; /* Display Panel interface is eDP */
+ unsigned int is_mipi:1; /* Display Panel interface is MIPI */
+ unsigned int fixvclk:2; /* VCLK hold scheme at data underflow */
+
+ /*
+ * Polarity of the VCLK active edge
+ * 0-falling
+ * 1-rising
+ */
+ unsigned int ivclk:1;
+ unsigned int clkval_f; /* Divider to create pixel clock */
+
+ unsigned int upper_margin; /* Vertical Backporch */
+ unsigned int lower_margin; /* Vertical frontporch */
+ unsigned int vsync; /* Vertical Sync Pulse Width */
+ unsigned int left_margin; /* Horizantal Backporch */
+ unsigned int right_margin; /* Horizontal Frontporch */
+ unsigned int hsync; /* Horizontal Sync Pulse Width */
+ unsigned int xres; /* X Resolution */
+ unsigned int yres; /* Y Resopultion */
+};
+
+/* LCDIF Register Map */
+struct exynos5_disp_ctrl {
+ unsigned int vidout_con;
+ unsigned int vidcon1;
+ unsigned char res1[0x8];
+ unsigned int vidtcon0;
+ unsigned int vidtcon1;
+ unsigned int vidtcon2;
+ unsigned int vidtcon3;
+ unsigned char res2[0x184];
+ unsigned int trigcon;
+};
+
+#define VCLK_RISING_EDGE (1 << 7)
+#define VCLK_RUNNING (1 << 9)
+
+#define CHANNEL0_EN (1 << 0)
+
+#define VSYNC_PULSE_WIDTH_VAL 0x3
+#define VSYNC_PULSE_WIDTH_OFFSET 0
+#define V_FRONT_PORCH_VAL 0x3
+#define V_FRONT_PORCH_OFFSET 8
+#define V_BACK_PORCH_VAL 0x3
+#define V_BACK_PORCH_OFFSET 16
+
+#define HSYNC_PULSE_WIDTH_VAL 0x3
+#define HSYNC_PULSE_WIDTH_OFFSET 0
+#define H_FRONT_PORCH_VAL 0x3
+#define H_FRONT_PORCH_OFFSET 8
+#define H_BACK_PORCH_VAL 0x3
+#define H_BACK_PORCH_OFFSET 16
+
+#define HOZVAL_OFFSET 0
+#define LINEVAL_OFFSET 11
+
+#define BPPMODE_F_RGB_16BIT_565 0x5
+#define BPPMODE_F_OFFSET 2
+#define ENWIN_F_ENABLE (1 << 0)
+#define HALF_WORD_SWAP_EN (1 << 16)
+
+#define OSD_RIGHTBOTX_F_OFFSET 11
+#define OSD_RIGHTBOTY_F_OFFSET 0
+#endif
diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h
new file mode 100644
index 0000000..b45cf5c
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/gpio.h
@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef EXYNOS5250_GPIO_H_
+#define EXYNOS5250_GPIO_H_
+
+#include <cpu/samsung/exynos-common/gpio.h>
+
+struct exynos5_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank a2;
+ struct s5p_gpio_bank b0;
+ struct s5p_gpio_bank b1;
+ struct s5p_gpio_bank b2;
+ struct s5p_gpio_bank b3;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank c2;
+ struct s5p_gpio_bank c3;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+};
+
+struct exynos5_gpio_part2 {
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos5_gpio_part3 {
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+};
+
+struct exynos5_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+};
+
+struct exynos5_gpio_part5 {
+ struct s5p_gpio_bank v4;
+};
+
+struct exynos5_gpio_part6 {
+ struct s5p_gpio_bank z;
+};
+
+enum {
+ /* GPIO banks are split into this many parts */
+ EXYNOS_GPIO_NUM_PARTS = 6
+};
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos5_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ GPIO_A00,
+ GPIO_A01,
+ GPIO_A02,
+ GPIO_A03,
+ GPIO_A04,
+ GPIO_A05,
+ GPIO_A06,
+ GPIO_A07,
+ GPIO_A10,
+ GPIO_A11,
+ GPIO_A12,
+ GPIO_A13,
+ GPIO_A14,
+ GPIO_A15,
+ GPIO_A16,
+ GPIO_A17,
+ GPIO_A20,
+ GPIO_A21,
+ GPIO_A22,
+ GPIO_A23,
+ GPIO_A24,
+ GPIO_A25,
+ GPIO_A26,
+ GPIO_A27,
+ GPIO_B00, /* 0x18 */
+ GPIO_B01,
+ GPIO_B02,
+ GPIO_B03,
+ GPIO_B04,
+ GPIO_B05,
+ GPIO_B06,
+ GPIO_B07,
+ GPIO_B10,
+ GPIO_B11,
+ GPIO_B12,
+ GPIO_B13,
+ GPIO_B14,
+ GPIO_B15,
+ GPIO_B16,
+ GPIO_B17,
+ GPIO_B20,
+ GPIO_B21,
+ GPIO_B22,
+ GPIO_B23,
+ GPIO_B24,
+ GPIO_B25,
+ GPIO_B26,
+ GPIO_B27,
+ GPIO_B30,
+ GPIO_B31,
+ GPIO_B32,
+ GPIO_B33,
+ GPIO_B34,
+ GPIO_B35,
+ GPIO_B36,
+ GPIO_B37,
+ GPIO_C00, /* 0x38 */
+ GPIO_C01,
+ GPIO_C02,
+ GPIO_C03,
+ GPIO_C04,
+ GPIO_C05,
+ GPIO_C06,
+ GPIO_C07,
+ GPIO_C10,
+ GPIO_C11,
+ GPIO_C12,
+ GPIO_C13,
+ GPIO_C14,
+ GPIO_C15,
+ GPIO_C16,
+ GPIO_C17,
+ GPIO_C20,
+ GPIO_C21,
+ GPIO_C22,
+ GPIO_C23,
+ GPIO_C24,
+ GPIO_C25,
+ GPIO_C26,
+ GPIO_C27,
+ GPIO_C30,
+ GPIO_C31,
+ GPIO_C32,
+ GPIO_C33,
+ GPIO_C34,
+ GPIO_C35,
+ GPIO_C36,
+ GPIO_C37,
+ GPIO_D00, /* 0x58 */
+ GPIO_D01,
+ GPIO_D02,
+ GPIO_D03,
+ GPIO_D04,
+ GPIO_D05,
+ GPIO_D06,
+ GPIO_D07,
+ GPIO_D10,
+ GPIO_D11,
+ GPIO_D12,
+ GPIO_D13,
+ GPIO_D14,
+ GPIO_D15,
+ GPIO_D16,
+ GPIO_D17,
+ GPIO_Y00, /* 0x68 */
+ GPIO_Y01,
+ GPIO_Y02,
+ GPIO_Y03,
+ GPIO_Y04,
+ GPIO_Y05,
+ GPIO_Y06,
+ GPIO_Y07,
+ GPIO_Y10,
+ GPIO_Y11,
+ GPIO_Y12,
+ GPIO_Y13,
+ GPIO_Y14,
+ GPIO_Y15,
+ GPIO_Y16,
+ GPIO_Y17,
+ GPIO_Y20,
+ GPIO_Y21,
+ GPIO_Y22,
+ GPIO_Y23,
+ GPIO_Y24,
+ GPIO_Y25,
+ GPIO_Y26,
+ GPIO_Y27,
+ GPIO_Y30,
+ GPIO_Y31,
+ GPIO_Y32,
+ GPIO_Y33,
+ GPIO_Y34,
+ GPIO_Y35,
+ GPIO_Y36,
+ GPIO_Y37,
+ GPIO_Y40,
+ GPIO_Y41,
+ GPIO_Y42,
+ GPIO_Y43,
+ GPIO_Y44,
+ GPIO_Y45,
+ GPIO_Y46,
+ GPIO_Y47,
+ GPIO_Y50,
+ GPIO_Y51,
+ GPIO_Y52,
+ GPIO_Y53,
+ GPIO_Y54,
+ GPIO_Y55,
+ GPIO_Y56,
+ GPIO_Y57,
+ GPIO_Y60,
+ GPIO_Y61,
+ GPIO_Y62,
+ GPIO_Y63,
+ GPIO_Y64,
+ GPIO_Y65,
+ GPIO_Y66,
+ GPIO_Y67,
+
+ /* GPIO_PART2_STARTS */
+ GPIO_MAX_PORT_PART_1,
+ GPIO_X00 = GPIO_MAX_PORT_PART_1, /* 0xa0 */
+ GPIO_X01,
+ GPIO_X02,
+ GPIO_X03,
+ GPIO_X04,
+ GPIO_X05,
+ GPIO_X06,
+ GPIO_X07,
+ GPIO_X10,
+ GPIO_X11,
+ GPIO_X12,
+ GPIO_X13,
+ GPIO_X14,
+ GPIO_X15,
+ GPIO_X16,
+ GPIO_X17,
+ GPIO_X20,
+ GPIO_X21,
+ GPIO_X22,
+ GPIO_X23,
+ GPIO_X24,
+ GPIO_X25,
+ GPIO_X26,
+ GPIO_X27,
+ GPIO_X30,
+ GPIO_X31,
+ GPIO_X32,
+ GPIO_X33,
+ GPIO_X34,
+ GPIO_X35,
+ GPIO_X36,
+ GPIO_X37,
+
+ /* GPIO_PART3_STARTS */
+ GPIO_MAX_PORT_PART_2,
+ GPIO_E00 = GPIO_MAX_PORT_PART_2, /* 0xc0 */
+ GPIO_E01,
+ GPIO_E02,
+ GPIO_E03,
+ GPIO_E04,
+ GPIO_E05,
+ GPIO_E06,
+ GPIO_E07,
+ GPIO_E10,
+ GPIO_E11,
+ GPIO_E12,
+ GPIO_E13,
+ GPIO_E14,
+ GPIO_E15,
+ GPIO_E16,
+ GPIO_E17,
+ GPIO_F00, /* 0xd0 */
+ GPIO_F01,
+ GPIO_F02,
+ GPIO_F03,
+ GPIO_F04,
+ GPIO_F05,
+ GPIO_F06,
+ GPIO_F07,
+ GPIO_F10,
+ GPIO_F11,
+ GPIO_F12,
+ GPIO_F13,
+ GPIO_F14,
+ GPIO_F15,
+ GPIO_F16,
+ GPIO_F17,
+ GPIO_G00,
+ GPIO_G01,
+ GPIO_G02,
+ GPIO_G03,
+ GPIO_G04,
+ GPIO_G05,
+ GPIO_G06,
+ GPIO_G07,
+ GPIO_G10,
+ GPIO_G11,
+ GPIO_G12,
+ GPIO_G13,
+ GPIO_G14,
+ GPIO_G15,
+ GPIO_G16,
+ GPIO_G17,
+ GPIO_G20,
+ GPIO_G21,
+ GPIO_G22,
+ GPIO_G23,
+ GPIO_G24,
+ GPIO_G25,
+ GPIO_G26,
+ GPIO_G27,
+ GPIO_H00,
+ GPIO_H01,
+ GPIO_H02,
+ GPIO_H03,
+ GPIO_H04,
+ GPIO_H05,
+ GPIO_H06,
+ GPIO_H07,
+ GPIO_H10,
+ GPIO_H11,
+ GPIO_H12,
+ GPIO_H13,
+ GPIO_H14,
+ GPIO_H15,
+ GPIO_H16,
+ GPIO_H17,
+
+ /* GPIO_PART4_STARTS */
+ GPIO_MAX_PORT_PART_3,
+ GPIO_V00 = GPIO_MAX_PORT_PART_3,
+ GPIO_V01,
+ GPIO_V02,
+ GPIO_V03,
+ GPIO_V04,
+ GPIO_V05,
+ GPIO_V06,
+ GPIO_V07,
+ GPIO_V10,
+ GPIO_V11,
+ GPIO_V12,
+ GPIO_V13,
+ GPIO_V14,
+ GPIO_V15,
+ GPIO_V16,
+ GPIO_V17,
+ GPIO_V20,
+ GPIO_V21,
+ GPIO_V22,
+ GPIO_V23,
+ GPIO_V24,
+ GPIO_V25,
+ GPIO_V26,
+ GPIO_V27,
+ GPIO_V30,
+ GPIO_V31,
+ GPIO_V32,
+ GPIO_V33,
+ GPIO_V34,
+ GPIO_V35,
+ GPIO_V36,
+ GPIO_V37,
+
+ /* GPIO_PART5_STARTS */
+ GPIO_MAX_PORT_PART_4,
+ GPIO_V40 = GPIO_MAX_PORT_PART_4,
+ GPIO_V41,
+ GPIO_V42,
+ GPIO_V43,
+ GPIO_V44,
+ GPIO_V45,
+ GPIO_V46,
+ GPIO_V47,
+
+ /* GPIO_PART6_STARTS */
+ GPIO_MAX_PORT_PART_5,
+ GPIO_Z0 = GPIO_MAX_PORT_PART_5,
+ GPIO_Z1,
+ GPIO_Z2,
+ GPIO_Z3,
+ GPIO_Z4,
+ GPIO_Z5,
+ GPIO_Z6,
+ GPIO_MAX_PORT
+};
+
+#define gpio_status gpio_info
+
+/**
+ * Set GPIO pin configuration.
+ *
+ * @param gpio GPIO pin
+ * @param cfg Either GPIO_INPUT, GPIO_OUTPUT, or GPIO_IRQ
+ */
+void gpio_cfg_pin(int gpio, int cfg);
+
+/**
+ * Set GPIO pull mode.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_PULL_DOWN or GPIO_PULL_UP
+ */
+void gpio_set_pull(int gpio, int mode);
+
+/**
+ * Set GPIO drive strength level.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_DRV_1X, GPIO_DRV_2X, GPIO_DRV_3X, or GPIO_DRV_4X
+ */
+void gpio_set_drv(int gpio, int mode);
+
+/**
+ * Set GPIO drive rate.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_DRV_FAST or GPIO_DRV_SLOW
+ */
+void gpio_set_rate(int gpio, int mode);
+
+/* FIXME(dhendrix) use generic arch/gpio.h API instead */
+//int gpio_direction_input(unsigned gpio);
+//int gpio_direction_output(unsigned gpio, int value);
+
+/**
+ * Decode a list of GPIOs into an integer.
+ *
+ * TODO(sjg at chromium.org): This could perhaps become a generic function?
+ *
+ * Each GPIO pin can be put into three states using external resistors:
+ * - pulled up
+ * - pulled down
+ * - not connected
+ *
+ * Read each GPIO in turn to produce an integer value. The first GPIO
+ * produces a number 1 * (0 to 2), the second produces 3 * (0 to 2), etc.
+ * In this way, each GPIO increases the number of possible states by a
+ * factor of 3.
+ *
+ * @param gpio_list List of GPIO numbers to decode
+ * @param count Number of GPIOs in list
+ * @return -1 if the value cannot be determined, or any GPIO number is
+ * invalid. Otherwise returns the calculated value
+ */
+int gpio_decode_number(unsigned gpio_list[], int count);
+
+void gpio_info(void);
+
+#endif /* EXYNOS5250_GPIO_H_ */
diff --git a/src/cpu/samsung/exynos5250/i2s-regs.h b/src/cpu/samsung/exynos5250/i2s-regs.h
new file mode 100644
index 0000000..19267ca
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/i2s-regs.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar at samsung.com>
+ *
+ * Taken from the kernel code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define I2SCON 0x0
+#define I2SMOD 0x4
+#define I2SFIC 0x8
+#define I2SPSR 0xc
+#define I2STXD 0x10
+#define I2SRXD 0x14
+#define I2SFICS 0x18
+#define I2STXDS 0x1c
+#define I2SAHB 0x20
+#define I2SSTR0 0x24
+#define I2SSIZE 0x28
+#define I2STRNCNT 0x2c
+#define I2SLVL0ADDR 0x30
+#define I2SLVL1ADDR 0x34
+#define I2SLVL2ADDR 0x38
+#define I2SLVL3ADDR 0x3c
+
+#define CON_RSTCLR (1 << 31)
+#define CON_FRXOFSTATUS (1 << 26)
+#define CON_FRXORINTEN (1 << 25)
+#define CON_FTXSURSTAT (1 << 24)
+#define CON_FTXSURINTEN (1 << 23)
+#define CON_TXSDMA_PAUSE (1 << 20)
+#define CON_TXSDMA_ACTIVE (1 << 18)
+
+#define CON_FTXURSTATUS (1 << 17)
+#define CON_FTXURINTEN (1 << 16)
+#define CON_TXFIFO2_EMPTY (1 << 15)
+#define CON_TXFIFO1_EMPTY (1 << 14)
+#define CON_TXFIFO2_FULL (1 << 13)
+#define CON_TXFIFO1_FULL (1 << 12)
+
+#define CON_LRINDEX (1 << 11)
+#define CON_TXFIFO_EMPTY (1 << 10)
+#define CON_RXFIFO_EMPTY (1 << 9)
+#define CON_TXFIFO_FULL (1 << 8)
+#define CON_RXFIFO_FULL (1 << 7)
+#define CON_TXDMA_PAUSE (1 << 6)
+#define CON_RXDMA_PAUSE (1 << 5)
+#define CON_TXCH_PAUSE (1 << 4)
+#define CON_RXCH_PAUSE (1 << 3)
+#define CON_TXDMA_ACTIVE (1 << 2)
+#define CON_RXDMA_ACTIVE (1 << 1)
+#define CON_ACTIVE (1 << 0)
+
+#define MOD_OPCLK_CDCLK_OUT (0 << 30)
+#define MOD_OPCLK_CDCLK_IN (1 << 30)
+#define MOD_OPCLK_BCLK_OUT (2 << 30)
+#define MOD_OPCLK_PCLK (3 << 30)
+#define MOD_OPCLK_MASK (3 << 30)
+#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
+
+#define MOD_BLCS_SHIFT 26
+#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT)
+
+#define MOD_BLCP_SHIFT 24
+#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
+
+#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
+#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
+#define MOD_C1DD_HHALF (1 << 19)
+#define MOD_C1DD_LHALF (1 << 18)
+#define MOD_DC2_EN (1 << 17)
+#define MOD_DC1_EN (1 << 16)
+#define MOD_BLC_16BIT (0 << 13)
+#define MOD_BLC_8BIT (1 << 13)
+#define MOD_BLC_24BIT (2 << 13)
+#define MOD_BLC_MASK (3 << 13)
+
+#define MOD_IMS_SYSMUX (1 << 10)
+#define MOD_SLAVE (1 << 11)
+#define MOD_TXONLY (0 << 8)
+#define MOD_RXONLY (1 << 8)
+#define MOD_TXRX (2 << 8)
+#define MOD_MASK (3 << 8)
+#define MOD_LR_LLOW (0 << 7)
+#define MOD_LR_RLOW (1 << 7)
+#define MOD_SDF_IIS (0 << 5)
+#define MOD_SDF_MSB (1 << 5)
+#define MOD_SDF_LSB (2 << 5)
+#define MOD_SDF_MASK (3 << 5)
+#define MOD_RCLK_256FS (0 << 3)
+#define MOD_RCLK_512FS (1 << 3)
+#define MOD_RCLK_384FS (2 << 3)
+#define MOD_RCLK_768FS (3 << 3)
+#define MOD_RCLK_MASK (3 << 3)
+#define MOD_BCLK_32FS (0 << 1)
+#define MOD_BCLK_48FS (1 << 1)
+#define MOD_BCLK_16FS (2 << 1)
+#define MOD_BCLK_24FS (3 << 1)
+#define MOD_BCLK_MASK (3 << 1)
+#define MOD_8BIT (1 << 0)
+
+#define MOD_CDCLKCON (1 << 12)
+
+#define PSR_PSREN (1 << 15)
+
+#define FIC_TXFLUSH (1 << 15)
+#define FIC_RXFLUSH (1 << 7)
+
+#define AHB_INTENLVL0 (1 << 24)
+#define AHB_LVL0INT (1 << 20)
+#define AHB_CLRLVL0INT (1 << 16)
+#define AHB_DMARLD (1 << 5)
+#define AHB_INTMASK (1 << 3)
+#define AHB_DMAEN (1 << 0)
+#define AHB_LVLINTMASK (0xf << 20)
+
+#define I2SSIZE_TRNMSK (0xffff)
+#define I2SSIZE_SHIFT (16)
+
+#endif /* __I2S_REGS_H__ */
diff --git a/src/cpu/samsung/exynos5250/mmc.h b/src/cpu/samsung/exynos5250/mmc.h
new file mode 100644
index 0000000..24acbc1
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_MMC_H__
+#define __ASM_ARM_ARCH_EXYNOS5_MMC_H__
+
+#include <asm/arch-exynos/mmc.h>
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_MMC_H__ */
diff --git a/src/cpu/samsung/exynos5250/mshc.h b/src/cpu/samsung/exynos5250/mshc.h
new file mode 100644
index 0000000..d8e3ad0
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/mshc.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_MSHC_H__
+#define __ASM_ARM_ARCH_EXYNOS5_MSHC_H__
+
+#include <asm/arch-exynos/mshc.h>
+
+#define MAX_MSHCI_CLOCK 52000000 /* Max limit for mshc clock is 52MHz */
+#define MIN_MSHCI_CLOCK 400000 /* Lower limit for mshc clock is 400KHz */
+#define COMMAND_TIMEOUT 10000
+#define TIMEOUT_MS 100
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_MSHC_H__ */
diff --git a/src/cpu/samsung/exynos5250/periph.h b/src/cpu/samsung/exynos5250/periph.h
new file mode 100644
index 0000000..e14829e
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/periph.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2012 The Chromium Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __EXYNOS_PERIPH_H
+#define __EXYNOS_PERIPH_H
+
+/*
+ * Peripherals requiring clock/pinmux configuration. List will
+ * grow with support for more devices getting added.
+ *
+ * At present the order is arbitrary - we may be able to take advantage
+ * of some orthogonality later.
+ */
+enum periph_id {
+ PERIPH_ID_UART0,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+
+ /* TODO: make sequential again when FDT doesn't hardcode. */
+ PERIPH_ID_SROMC = 9,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_LCD,
+ PERIPH_ID_BACKLIGHT,
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_DPHPD, /* eDP hot plug detect */
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_SATA,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/pinmux.h b/src/cpu/samsung/exynos5250/pinmux.h
new file mode 100644
index 0000000..81c0087
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/pinmux.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS_PINMUX_H
+#define __EXYNOS_PINMUX_H
+
+//#include <asm/arch/periph.h>
+#include "periph.h"
+
+enum {
+ PINMUX_FLAG_NONE = 0x00000000,
+
+ /* Flags for eMMC */
+ PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
+
+ /*
+ * Flags for SPI.
+ */
+ PINMUX_FLAG_SLAVE_MODE = 1 << 0, /* Slave mode */
+
+ /* Flags for SROM controller */
+ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
+ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral peripheral to be configured
+ * @param flags configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(enum periph_id peripheral, int flags);
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
new file mode 100644
index 0000000..59a0257
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for Exynos5 PMU
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_POWER_H__
+#define __EXYNOS5_POWER_H__
+
+#define MIPI_PHY1_CONTROL_ENABLE (1 << 0)
+#define MIPI_PHY1_CONTROL_M_RESETN (1 << 2)
+
+#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
+#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
+#define POWER_ENABLE_HW_TRIP (1UL << 31)
+
+#define DPTX_PHY_ENABLE (1 << 0)
+
+/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
+#define PMU_DEBUG_XXTI 0x1000
+/* Mask bit[12:8] for xxti clock selection */
+#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
+
+/* Power Management Unit register map */
+struct exynos5_power {
+ /* Add registers as and when required */
+ uint8_t reserved1[0x0400];
+ uint32_t sw_reset; /* 0x0400 */
+ uint8_t reserved2[0x0304];
+ uint32_t usb_host_phy_ctrl; /* 0x0708 */
+ uint8_t reserved3[0x8];
+ uint32_t mipi_phy1_control; /* 0x0714 */
+ uint8_t reserved4[0x8];
+ uint32_t dptx_phy_control; /* 0x0720 */
+ uint8_t reserved5[0xdc];
+ uint32_t inform0; /* 0x0800 */
+ uint32_t inform1; /* 0x0804 */
+ uint8_t reserved6[0x1f8];
+ uint32_t pmu_debug; /* 0x0A00*/
+ uint8_t reserved7[0x2908];
+ uint32_t ps_hold_ctrl; /* 0x330c */
+} __attribute__ ((__packed__));
+
+/**
+ * Perform a software reset.
+ */
+void power_reset(void);
+
+/**
+ * Power off the system; it should never return.
+ */
+void power_shutdown(void);
+
+/* Enable DPTX PHY */
+void power_enable_dp_phy(void);
+
+void power_enable_usb_phy(void);
+void power_disable_usb_phy(void);
+
+/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
+void power_enable_hw_thermal_trip(void);
+
+/* Initialize the pmic voltages to power up the system */
+int power_init(void);
+
+/* Read the reset status. */
+uint32_t power_read_reset_status(void);
+
+/* Read the resume function and call it. */
+void power_exit_wakeup(void);
+
+/* pmu debug is used for xclkout, enable xclkout with source as XXTI */
+void power_enable_xclkout(void);
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/pwm.h b/src/cpu/samsung/exynos5250/pwm.h
new file mode 100644
index 0000000..e7ae208
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/pwm.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_PWM_H__
+#define __ASM_ARM_ARCH_EXYNOS5_PWM_H__
+
+#include <asm/arch-exynos/pwm.h>
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_PWM_H__ */
diff --git a/src/cpu/samsung/exynos5250/s5p-dp.h b/src/cpu/samsung/exynos5250/s5p-dp.h
new file mode 100644
index 0000000..5322383
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/s5p-dp.h
@@ -0,0 +1,513 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for Exynos5 DP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_DP_H__
+#define __EXYNOS5_DP_H__
+
+/* DSIM register map */
+struct exynos5_dp {
+ unsigned char res1[0x10];
+ unsigned int dp_tx_version;
+ unsigned int dp_tx_sw_reset;
+ unsigned int func_en_1;
+ unsigned int func_en_2;
+ unsigned int video_ctl_1;
+ unsigned int video_ctl_2;
+ unsigned int video_ctl_3;
+ unsigned int video_ctl_4;
+ unsigned int clr_blue_cb;
+ unsigned int clr_green_y;
+ unsigned int clr_red_cr;
+ unsigned int video_ctl_8;
+ unsigned char res2[0x4];
+ unsigned int video_ctl_10;
+ unsigned int total_line_l;
+ unsigned int total_line_h;
+ unsigned int active_line_l;
+ unsigned int active_line_h;
+ unsigned int v_f_porch;
+ unsigned int vsync;
+ unsigned int v_b_porch;
+ unsigned int total_pixel_l;
+ unsigned int total_pixel_h;
+ unsigned int active_pixel_l;
+ unsigned int active_pixel_h;
+ unsigned int h_f_porch_l;
+ unsigned int h_f_porch_h;
+ unsigned int hsync_l;
+ unsigned int hysnc_h;
+ unsigned int h_b_porch_l;
+ unsigned int h_b_porch_h;
+ unsigned int vid_status;
+ unsigned int total_line_sta_l;
+ unsigned int total_line_sta_h;
+ unsigned int active_line_sta_l;
+ unsigned int active_line_sta_h;
+ unsigned int v_f_porch_sta;
+ unsigned int vsync_sta;
+ unsigned int v_b_porch_sta;
+ unsigned int total_pixel_sta_l;
+ unsigned int total_pixel_sta_h;
+ unsigned int active_pixel_sta_l;
+ unsigned int active_pixel_sta_h;
+ unsigned int h_f_porch_sta_l;
+ unsigned int h_f_porch_sta_h;
+ unsigned int hsync_sta_l;
+ unsigned int hsync_sta_h;
+ unsigned int h_b_porch_sta_l;
+ unsigned int h_b_porch__sta_h;
+ unsigned char res3[0x288];
+ unsigned int lane_map;
+ unsigned char res4[0x10];
+ unsigned int analog_ctl_1;
+ unsigned int analog_ctl_2;
+ unsigned int analog_ctl_3;
+ unsigned int pll_filter_ctl_1;
+ unsigned int tx_amp_tuning_ctl;
+ unsigned char res5[0xc];
+ unsigned int aux_hw_retry_ctl;
+ unsigned char res6[0x2c];
+ unsigned int int_state;
+ unsigned int common_int_sta_1;
+ unsigned int common_int_sta_2;
+ unsigned int common_int_sta_3;
+ unsigned int common_int_sta_4;
+ unsigned char res7[0x8];
+ unsigned int dp_int_sta;
+ unsigned int common_int_mask_1;
+ unsigned int common_int_mask_2;
+ unsigned int common_int_mask_3;
+ unsigned int common_int_mask_4;
+ unsigned char res8[0x08];
+ unsigned int int_sta_mask;
+ unsigned int int_ctl;
+ unsigned char res9[0x200];
+ unsigned int sys_ctl_1;
+ unsigned int sys_ctl_2;
+ unsigned int sys_ctl_3;
+ unsigned int sys_ctl_4;
+ unsigned int dp_vid_ctl;
+ unsigned char res10[0x2c];
+ unsigned int pkt_send_ctl;
+ unsigned char res11[0x4];
+ unsigned int dp_hdcp_ctl;
+ unsigned char res12[0x34];
+ unsigned int link_bw_set;
+ unsigned int lane_count_set;
+ unsigned int dp_training_ptn_set;
+ unsigned int ln0_link_trn_ctl;
+ unsigned int ln1_link_trn_ctl;
+ unsigned int ln2_link_trn_ctl;
+ unsigned int ln3_link_trn_ctl;
+ unsigned int dp_dn_spread;
+ unsigned int dp_hw_link_training;
+ unsigned char res13[0x1c];
+ unsigned int dp_debug_ctl;
+ unsigned int dp_hpd_deglitch_l;
+ unsigned int dp_hpd_deglitch_h;
+ unsigned char res14[0x14];
+ unsigned int dp_link_debug_ctl;
+ unsigned char res15[0x1c];
+ unsigned int m_vid_0;
+ unsigned int m_vid_1;
+ unsigned int m_vid_2;
+ unsigned int n_vid_0;
+ unsigned int n_vid_1;
+ unsigned int n_vid_2;
+ unsigned int m_vid_mon;
+ unsigned int dp_pll_ctl;
+ unsigned int dp_phy_pd;
+ unsigned int dp_phy_test;
+ unsigned char res16[0x8];
+ unsigned int dp_video_fifo_thrd;
+ unsigned char res17[0x8];
+ unsigned int dp_audio_margin;
+ unsigned int dp_dn_spread_ctl_1;
+ unsigned int dp_dn_spread_ctl_2;
+ unsigned char res18[0x18];
+ unsigned int dp_m_cal_ctl;
+ unsigned int m_vid_gen_filter_th;
+ unsigned char res19[0x14];
+ unsigned int m_aud_gen_filter_th;
+ unsigned int aux_ch_sta;
+ unsigned int aux_err_num;
+ unsigned int aux_ch_defer_dtl;
+ unsigned int aux_rx_comm;
+ unsigned int buf_data_ctl;
+ unsigned int aux_ch_ctl_1;
+ unsigned int aux_addr_7_0;
+ unsigned int aux_addr_15_8;
+ unsigned int aux_addr_19_16;
+ unsigned int aux_ch_ctl_2;
+ unsigned char res20[0x18];
+ unsigned int buf_data_0;
+ unsigned char res21[0x3c];
+ unsigned int soc_general_ctl;
+};
+/* DP_TX_SW_RESET */
+#define RESET_DP_TX (1 << 0)
+
+/* DP_FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N (1 << 7)
+#define SLAVE_VID_FUNC_EN_N (1 << 5)
+#define AUD_FIFO_FUNC_EN_N (1 << 4)
+#define AUD_FUNC_EN_N (1 << 3)
+#define HDCP_FUNC_EN_N (1 << 2)
+#define CRC_FUNC_EN_N (1 << 1)
+#define SW_FUNC_EN_N (1 << 0)
+
+/* DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N (1 << 7)
+#define AUX_FUNC_EN_N (1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0)
+
+/* DP_VIDEO_CTL_1 */
+#define VIDEO_EN (1 << 7)
+#define HDCP_VIDEO_MUTE (1 << 6)
+
+/* DP_VIDEO_CTL_1 */
+#define IN_D_RANGE_MASK (1 << 7)
+#define IN_D_RANGE_SHIFT (7)
+#define IN_D_RANGE_CEA (1 << 7)
+#define IN_D_RANGE_VESA (0 << 7)
+#define IN_BPC_MASK (7 << 4)
+#define IN_BPC_SHIFT (4)
+#define IN_BPC_12_BITS (3 << 4)
+#define IN_BPC_10_BITS (2 << 4)
+#define IN_BPC_8_BITS (1 << 4)
+#define IN_BPC_6_BITS (0 << 4)
+#define IN_COLOR_F_MASK (3 << 0)
+#define IN_COLOR_F_SHIFT (0)
+#define IN_COLOR_F_YCBCR444 (2 << 0)
+#define IN_COLOR_F_YCBCR422 (1 << 0)
+#define IN_COLOR_F_RGB (0 << 0)
+
+/* DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK (1 << 7)
+#define IN_YC_COEFFI_SHIFT (7)
+#define IN_YC_COEFFI_ITU709 (1 << 7)
+#define IN_YC_COEFFI_ITU601 (0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK (1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT (4)
+#define VID_CHK_UPDATE_TYPE_1 (1 << 4)
+#define VID_CHK_UPDATE_TYPE_0 (0 << 4)
+
+/* DP_VIDEO_CTL_10 */
+#define FORMAT_SEL (1 << 4)
+#define INTERACE_SCAN_CFG (1 << 2)
+#define VSYNC_POLARITY_CFG (1 << 1)
+#define HSYNC_POLARITY_CFG (1 << 0)
+
+/* DP_LANE_MAP */
+#define LANE3_MAP_LOGIC_LANE_0 (0 << 6)
+#define LANE3_MAP_LOGIC_LANE_1 (1 << 6)
+#define LANE3_MAP_LOGIC_LANE_2 (2 << 6)
+#define LANE3_MAP_LOGIC_LANE_3 (3 << 6)
+#define LANE2_MAP_LOGIC_LANE_0 (0 << 4)
+#define LANE2_MAP_LOGIC_LANE_1 (1 << 4)
+#define LANE2_MAP_LOGIC_LANE_2 (2 << 4)
+#define LANE2_MAP_LOGIC_LANE_3 (3 << 4)
+#define LANE1_MAP_LOGIC_LANE_0 (0 << 2)
+#define LANE1_MAP_LOGIC_LANE_1 (1 << 2)
+#define LANE1_MAP_LOGIC_LANE_2 (2 << 2)
+#define LANE1_MAP_LOGIC_LANE_3 (3 << 2)
+#define LANE0_MAP_LOGIC_LANE_0 (0 << 0)
+#define LANE0_MAP_LOGIC_LANE_1 (1 << 0)
+#define LANE0_MAP_LOGIC_LANE_2 (2 << 0)
+#define LANE0_MAP_LOGIC_LANE_3 (3 << 0)
+
+/* DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_SHIFT 8
+#define AUX_BIT_PERIOD_MASK 7
+
+#define AUX_HW_RETRY_INTERVAL_SHIFT 3
+#define AUX_HW_RETRY_INTERVAL_600_US 0
+#define AUX_HW_RETRY_INTERVAL_800_US 1
+#define AUX_HW_RETRY_INTERVAL_1000_US 2
+#define AUX_HW_RETRY_INTERVAL_1800_US 3
+#define AUX_HW_RETRY_COUNT_SHIFT 0
+#define AUX_HW_RETRY_COUNT_MASK 7
+
+/* DP_COMMON_INT_STA_1 */
+#define VSYNC_DET (1 << 7)
+#define PLL_LOCK_CHG (1 << 6)
+#define SPDIF_ERR (1 << 5)
+#define SPDIF_UNSTBL (1 << 4)
+#define VID_FORMAT_CHG (1 << 3)
+#define AUD_CLK_CHG (1 << 2)
+#define VID_CLK_CHG (1 << 1)
+#define SW_INT (1 << 0)
+
+/* DP_COMMON_INT_STA_2 */
+#define ENC_EN_CHG (1 << 6)
+#define HW_BKSV_RDY (1 << 3)
+#define HW_SHA_DONE (1 << 2)
+#define HW_AUTH_STATE_CHG (1 << 1)
+#define HW_AUTH_DONE (1 << 0)
+
+/* DP_COMMON_INT_STA_3 */
+#define AFIFO_UNDER (1 << 7)
+#define AFIFO_OVER (1 << 6)
+#define R0_CHK_FLAG (1 << 5)
+
+/* DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE (1 << 7)
+#define PSR_INACTIVE (1 << 6)
+#define SPDIF_BI_PHASE_ERR (1 << 5)
+#define HOTPLUG_CHG (1 << 2)
+#define HPD_LOST (1 << 1)
+#define PLUG (1 << 0)
+
+/* DP_INT_STA */
+#define INT_HPD (1 << 6)
+#define HW_TRAINING_FINISH (1 << 5)
+#define RPLY_RECEIV (1 << 1)
+#define AUX_ERR (1 << 0)
+
+/* DP_INT_CTL */
+#define INT_POL0 (1 << 0)
+#define INT_POL1 (1 << 1)
+#define SOFT_INT_CTRL (1 << 2)
+
+/* DP_SYS_CTL_1 */
+#define DET_STA (1 << 2)
+#define FORCE_DET (1 << 1)
+#define DET_CTRL (1 << 0)
+
+/* DP_SYS_CTL_2 */
+#define CHA_CRI_SHIFT 4
+#define CHA_CRI_MASK 0xf
+#define CHA_STA (1 << 2)
+#define FORCE_CHA (1 << 1)
+#define CHA_CTRL (1 << 0)
+
+/* DP_SYS_CTL_3 */
+#define HPD_STATUS (1 << 6)
+#define F_HPD (1 << 5)
+#define HPD_CTRL (1 << 4)
+#define HDCP_RDY (1 << 3)
+#define STRM_VALID (1 << 2)
+#define F_VALID (1 << 1)
+#define VALID_CTRL (1 << 0)
+
+/* DP_SYS_CTL_4 */
+#define FIX_M_AUD (1 << 4)
+#define ENHANCED (1 << 3)
+#define FIX_M_VID (1 << 2)
+#define M_VID_UPDATE_CTRL (3 << 0)
+
+/* DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE (1 << 9)
+#define HW_LINK_TRAINING_PATTERN (1 << 8)
+#define SCRAMBLING_DISABLE (1 << 5)
+#define SCRAMBLING_ENABLE (0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK (3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7 (3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2 (1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE (0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK (3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL (0 << 0)
+
+/* DP_LN0_LINK_TRAINING_CTL */
+#define PRE_EMPHASIS_SET_SHIFT (3)
+
+/* DP_DEBUG_CTL */
+#define PLL_LOCK (1 << 4)
+#define F_PLL_LOCK (1 << 3)
+#define PLL_LOCK_CTRL (1 << 2)
+#define PN_INV (1 << 0)
+
+/* DP_M_VID */
+#define M_VID_0_VALUE_SHIFT 0
+#define M_VID_1_VALUE_SHIFT 8
+#define M_VID_2_VALUE_SHIFT 16
+
+/* DP_M_VID */
+#define N_VID_0_VALUE_SHIFT 0
+#define N_VID_1_VALUE_SHIFT 8
+#define N_VID_2_VALUE_SHIFT 16
+
+/* DP_PLL_CTL */
+#define DP_PLL_PD (1 << 7)
+#define DP_PLL_RESET (1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT (1 << 4)
+#define DP_PLL_REF_BIT_1_1250V (5 << 0)
+#define DP_PLL_REF_BIT_1_2500V (7 << 0)
+
+/* DP_PHY_PD */
+#define DP_PHY_PD (1 << 5)
+#define AUX_PD (1 << 4)
+#define CH3_PD (1 << 3)
+#define CH2_PD (1 << 2)
+#define CH1_PD (1 << 1)
+#define CH0_PD (1 << 0)
+
+/* DP_PHY_TEST */
+#define MACRO_RST (1 << 5)
+#define CH1_TEST (1 << 1)
+#define CH0_TEST (1 << 0)
+
+/* DP_AUX_CH_STA */
+#define AUX_BUSY (1 << 4)
+#define AUX_STATUS_MASK (0xf << 0)
+
+/* DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN (1 << 7)
+#define DEFER_COUNT_SHIFT 0
+#define DEFER_COUNT_MASK 0x7f
+
+/* DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER (2 << 2)
+#define AUX_RX_COMM_AUX_DEFER (2 << 0)
+
+/* DP_BUFFER_DATA_CTL */
+#define BUF_CLR (1 << 7)
+
+/* Maximum number of tries for Aux Transaction */
+#define MAX_AUX_RETRY_COUNT 10
+
+/* DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH_SHIFT 4
+#define AUX_LENGTH_MASK 0xf
+
+#define AUX_TX_COMM_MASK (0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION (1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION (0 << 3)
+#define AUX_TX_COMM_MOT (1 << 2)
+#define AUX_TX_COMM_WRITE (0 << 0)
+#define AUX_TX_COMM_READ (1 << 0)
+
+/* DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0_SHIFT 0
+#define AUX_ADDR_7_0_MASK 0xff
+
+/* DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8_SHIFT 8
+#define AUX_ADDR_15_8_MASK 0xff
+
+/* DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16_SHIFT 16
+#define AUX_ADDR_19_16_MASK 0x0f
+
+/* DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY (1 << 1)
+#define AUX_EN (1 << 0)
+
+/* DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE (1 << 8)
+#define AUDIO_MODE_MASTER_MODE (0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN (1 << 4)
+#define VIDEO_MASTER_CLK_SEL (1 << 2)
+#define VIDEO_MASTER_MODE_EN (1 << 1)
+#define VIDEO_MODE_MASK (1 << 0)
+#define VIDEO_MODE_SLAVE_MODE (1 << 0)
+#define VIDEO_MODE_MASTER_MODE (0 << 0)
+
+#define HW_TRAINING_ERROR_CODE (7<<4)
+#define HW_TRAINING_EN (1<<0)
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR 0x50
+#define I2C_E_EDID_DEVICE_ADDR 0x30
+
+#define EDID_BLOCK_LENGTH 0x80
+#define EDID_HEADER_PATTERN 0x00
+#define EDID_EXTENSION_FLAG 0x7e
+#define EDID_CHECKSUM 0x7f
+
+/* Definition for DPCD Register */
+#define DPCD_ADDR_DPCD_REV 0x0000
+#define DPCD_ADDR_MAX_LINK_RATE 0x0001
+#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
+#define DPCD_ADDR_LINK_BW_SET 0x0100
+#define DPCD_ADDR_LANE_COUNT_SET 0x0101
+#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
+#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
+#define DPCD_ADDR_LANE0_1_STATUS 0x0202
+#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
+#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
+#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
+#define DPCD_ADDR_TEST_REQUEST 0x0218
+#define DPCD_ADDR_TEST_RESPONSE 0x0260
+#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
+#define DPCD_ADDR_SINK_POWER_STATE 0x0600
+
+/* DPCD_ADDR_MAX_LANE_COUNT */
+#define DPCD_MAX_LANE_COUNT_MASK 0x1f
+
+/* DPCD_ADDR_LANE_COUNT_SET */
+#define DPCD_ENHANCED_FRAME_EN (1 << 7)
+#define DPCD_LANE_COUNT_SET_MASK 0x1f
+
+/* DPCD_ADDR_TRAINING_PATTERN_SET */
+#define DPCD_SCRAMBLING_DISABLED (1 << 5)
+#define DPCD_SCRAMBLING_ENABLED (0 << 5)
+#define DPCD_TRAINING_PATTERN_2 (2 << 0)
+#define DPCD_TRAINING_PATTERN_1 (1 << 0)
+#define DPCD_TRAINING_PATTERN_DISABLED (0 << 0)
+
+/* DPCD_ADDR_LANE0_1_STATUS */
+#define DPCD_LANE_SYMBOL_LOCKED (1 << 2)
+#define DPCD_LANE_CHANNEL_EQ_DONE (1 << 1)
+#define DPCD_LANE_CR_DONE (1 << 0)
+#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE | \
+ DPCD_LANE_CHANNEL_EQ_DONE | \
+ DPCD_LANE_SYMBOL_LOCKED)
+
+/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
+#define DPCD_LINK_STATUS_UPDATED (1 << 7)
+#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
+#define DPCD_INTERLANE_ALIGN_DONE (1 << 0)
+
+/* DPCD_ADDR_TEST_REQUEST */
+#define DPCD_TEST_EDID_READ (1 << 2)
+
+/* DPCD_ADDR_TEST_RESPONSE */
+#define DPCD_TEST_EDID_CHECKSUM_WRITE (1 << 2)
+
+/* DPCD_ADDR_SINK_POWER_STATE */
+#define DPCD_SET_POWER_STATE_D0 (1 << 0)
+#define DPCD_SET_POWER_STATE_D4 (2 << 0)
+
+/* Allow DP Gating clock and set FIMD source to 267 Mhz for DP */
+void clock_init_dp_clock(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have can_block=1 to complete the init.
+ *
+ * @param blob fdt blob containing LCD information
+ * @param can_block 1 to wait until all init is complete, and then return
+ * 0 to return immediately, potentially doing nothing if it
+ * is not yet time for the next init.
+ */
+int exynos_lcd_check_next_stage(const void *blob, int can_block);
+#endif
diff --git a/src/cpu/samsung/exynos5250/sata.h b/src/cpu/samsung/exynos5250/sata.h
new file mode 100644
index 0000000..912228e
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/sata.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __EXYNOS5_SATA_H
+#define __EXYNOS5_SATA_H
+
+int exynos5_sata_init(const void *blob);
+#endif
+
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h
new file mode 100644
index 0000000..5e59232
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/setup.h
@@ -0,0 +1,756 @@
+/*
+ * Machine Specific Values for SMDK5250 board based on Exynos5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x00203800)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (0x00203800)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x00000000
+#define VPLL_CON2_VAL 0x00000080
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x00203800
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
+#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
+#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8 (3 << 20)
+#define DMC_MEMCONTROL_BL_4 (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
+#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
+#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
+
+#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
+#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
+#define DMC_MEMBASECONFIG_VAL(x) ( \
+ DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
+ DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
+)
+
+#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL 0xFF000000
+#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
+#define DFI_INIT_START (1 << 28)
+#define EMPTY (1 << 8)
+#define AREF_EN (1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO (1 << 2)
+#define DFI_INIT_COMPLETE_CH1 (1 << 3)
+
+#define RDLVL_COMPLETE_CHO (1 << 14)
+#define RDLVL_COMPLETE_CH1 (1 << 15)
+
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
+#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
+#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
+ | (APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (ACP_RATIO << 8) \
+ | (CPUD_RATIO << 4) \
+ | (ARM_RATIO))
+
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x2
+#define COPY_RATIO 0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL 0x00000000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL 0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL 0x00120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL 0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL 0x00000311
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x1
+
+/* CLK_DIV_CDREX */
+#define MCLK_CDREX2_RATIO 0x0
+#define ACLK_EFCON_RATIO 0x1
+#define MCLK_DPHY_RATIO 0x1
+#define MCLK_CDREX_RATIO 0x1
+#define ACLK_C2C_200_RATIO 0x1
+#define C2C_CLK_400_RATIO 0x1
+#define PCLK_CDREX_RATIO 0x1
+#define ACLK_CDREX_RATIO 0x1
+
+#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
+ | (C2C_CLK_400_RATIO << 6) \
+ | (PCLK_CDREX_RATIO << 4) \
+ | (ACLK_CDREX_RATIO))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID_SEL 0x0
+#define MUX_ACLK_400_G3D_MID_SEL 0x0
+#define MUX_ACLK_333_SEL 0x0
+#define MUX_ACLK_300_DISP1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_ACLK_166_SEL 0x0
+#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
+ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+ | (MUX_ACLK_400_G3D_MID_SEL << 20) \
+ | (MUX_ACLK_333_SEL << 16) \
+ | (MUX_ACLK_300_DISP1_SEL << 15) \
+ | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
+ | (MUX_ACLK_200_SEL << 12) \
+ | (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_G3D_SEL 0x1
+#define MUX_ACLK_400_ISP_SEL 0x0
+#define MUX_ACLK_400_IOP_SEL 0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
+#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
+ |(MUX_ACLK_400_ISP_SEL << 24) \
+ |(MUX_ACLK_400_IOP_SEL << 20) \
+ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
+ |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
+ |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
+
+/* CLK_SRC_TOP2 */
+#define MUX_GPLL_SEL 0x1
+#define MUX_BPLL_USER_SEL 0x0
+#define MUX_MPLL_USER_SEL 0x0
+#define MUX_VPLL_SEL 0x1
+#define MUX_EPLL_SEL 0x1
+#define MUX_CPLL_SEL 0x1
+#define VPLLSRC_SEL 0x0
+#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
+ | (MUX_BPLL_USER_SEL << 24) \
+ | (MUX_MPLL_USER_SEL << 20) \
+ | (MUX_VPLL_SEL << 16) \
+ | (MUX_EPLL_SEL << 12) \
+ | (MUX_CPLL_SEL << 8) \
+ | (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL 0x1
+#define MUX_ACLK_400_SUB_SEL 0x1
+#define MUX_ACLK_266_ISP_SUB_SEL 0x1
+#define MUX_ACLK_266_GPS_SUB_SEL 0x0
+#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
+#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
+ | (MUX_ACLK_400_SUB_SEL << 20) \
+ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+ | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+ | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+ | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_DISP1_RATIO 0x2
+#define ACLK_400_G3D_RATIO 0x0
+#define ACLK_333_RATIO 0x0
+#define ACLK_266_RATIO 0x2
+#define ACLK_200_RATIO 0x3
+#define ACLK_166_RATIO 0x1
+#define ACLK_133_RATIO 0x1
+#define ACLK_66_RATIO 0x5
+
+#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
+ | (ACLK_400_G3D_RATIO << 24) \
+ | (ACLK_333_RATIO << 20) \
+ | (ACLK_266_RATIO << 16) \
+ | (ACLK_200_RATIO << 12) \
+ | (ACLK_166_RATIO << 8) \
+ | (ACLK_133_RATIO << 4) \
+ | (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
+#define ACLK_66_PRE_RATIO 0x1
+#define ACLK_400_ISP_RATIO 0x1
+#define ACLK_400_IOP_RATIO 0x1
+#define ACLK_300_GSCL_RATIO 0x2
+
+#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+ | (ACLK_66_PRE_RATIO << 24) \
+ | (ACLK_400_ISP_RATIO << 20) \
+ | (ACLK_400_IOP_RATIO << 16) \
+ | (ACLK_300_GSCL_RATIO << 12))
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x546)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x546)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x546)
+/* GPLL_LOCK */
+#define GPLL_LOCK_VAL (0x546)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x3A98)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x3A98)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x546)
+
+#define MUX_MCLK_CDREX_SEL (1 << 4)
+#define MUX_MCLK_DPHY_SEL (1 << 8)
+
+#define MUX_APLL_SEL_MASK (1 << 0)
+#define MUX_MPLL_FOUT_SEL (1 << 4)
+#define MUX_BPLL_FOUT_SEL (1 << 0)
+#define MUX_MPLL_SEL_MASK (1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
+#define MUX_CPLL_SEL_MASK (1 << 8)
+#define MUX_EPLL_SEL_MASK (1 << 12)
+#define MUX_VPLL_SEL_MASK (1 << 16)
+#define MUX_GPLL_SEL_MASK (1 << 28)
+#define MUX_BPLL_SEL_MASK (1 << 0)
+#define MUX_HPM_SEL_MASK (1 << 20)
+#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define APLL_CON0_LOCKED (1 << 29)
+#define MPLL_CON0_LOCKED (1 << 29)
+#define BPLL_CON0_LOCKED (1 << 29)
+#define CPLL_CON0_LOCKED (1 << 29)
+#define EPLL_CON0_LOCKED (1 << 29)
+#define GPLL_CON0_LOCKED (1 << 29)
+#define VPLL_CON0_LOCKED (1 << 29)
+#define CLK_REG_DISABLE 0x0
+#define TOP2_VAL 0x0110000
+
+/* CLK_SRC_PERIC0 */
+#define PWM_SEL 6
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+/* SRC_CLOCK = SCLK_MPLL */
+#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define SPI0_SEL 6
+#define SPI1_SEL 6
+#define SPI2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
+ | (SPI1_SEL << 20) \
+ | (SPI0_SEL << 16))
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL 6
+#define SPI1_ISP_SEL 6
+#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
+ | (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO 0xf
+#define SPI1_ISP_RATIO 0xf
+#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
+ | (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_PERIL0 */
+#define UART5_RATIO 7
+#define UART4_RATIO 7
+#define UART3_RATIO 7
+#define UART2_RATIO 7
+#define UART1_RATIO 7
+#define UART0_RATIO 7
+
+#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO))
+/* CLK_DIV_PERIC1 */
+#define SPI1_RATIO 0x7
+#define SPI0_RATIO 0xf
+#define SPI1_SUB_RATIO 0x0
+#define SPI0_SUB_RATIO 0x0
+#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
+ | ((SPI1_RATIO << 16) \
+ | (SPI0_SUB_RATIO << 8) \
+ | (SPI0_RATIO << 0)))
+
+/* CLK_DIV_PERIC2 */
+#define SPI2_RATIO 0xf
+#define SPI2_SUB_RATIO 0x0
+#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
+ | (SPI2_RATIO << 0))
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK 0xf
+#define MMC2_RATIO_VAL 0x3
+#define MMC2_RATIO_OFFSET 0
+
+#define MMC2_PRE_RATIO_MASK 0xff
+#define MMC2_PRE_RATIO_VAL 0x9
+#define MMC2_PRE_RATIO_OFFSET 8
+
+#define MMC3_RATIO_MASK 0xf
+#define MMC3_RATIO_VAL 0x1
+#define MMC3_RATIO_OFFSET 16
+
+#define MMC3_PRE_RATIO_MASK 0xff
+#define MMC3_PRE_RATIO_VAL 0x0
+#define MMC3_PRE_RATIO_OFFSET 24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP0 */
+#define CLK_DIV_ISP0_VAL 0x31
+
+/* CLK_DIV_ISP1 */
+#define CLK_DIV_ISP1_VAL 0x0
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x6
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW (1 << 4)
+
+/* CLK_GATE_IP_SYSRGT */
+#define CLK_C2C_MASK (1 << 1)
+
+/* CLK_GATE_IP_ACP */
+#define CLK_SMMUG2D_MASK (1 << 7)
+#define CLK_SMMUSSS_MASK (1 << 6)
+#define CLK_SMMUMDMA_MASK (1 << 5)
+#define CLK_ID_REMAPPER_MASK (1 << 4)
+#define CLK_G2D_MASK (1 << 3)
+#define CLK_SSS_MASK (1 << 2)
+#define CLK_MDMA_MASK (1 << 1)
+#define CLK_SECJTAG_MASK (1 << 0)
+
+/* CLK_GATE_BUS_SYSLFT */
+#define CLK_EFCLK_MASK (1 << 16)
+
+/* CLK_GATE_IP_ISP0 */
+#define CLK_UART_ISP_MASK (1 << 31)
+#define CLK_WDT_ISP_MASK (1 << 30)
+#define CLK_PWM_ISP_MASK (1 << 28)
+#define CLK_MTCADC_ISP_MASK (1 << 27)
+#define CLK_I2C1_ISP_MASK (1 << 26)
+#define CLK_I2C0_ISP_MASK (1 << 25)
+#define CLK_MPWM_ISP_MASK (1 << 24)
+#define CLK_MCUCTL_ISP_MASK (1 << 23)
+#define CLK_INT_COMB_ISP_MASK (1 << 22)
+#define CLK_SMMU_MCUISP_MASK (1 << 13)
+#define CLK_SMMU_SCALERP_MASK (1 << 12)
+#define CLK_SMMU_SCALERC_MASK (1 << 11)
+#define CLK_SMMU_FD_MASK (1 << 10)
+#define CLK_SMMU_DRC_MASK (1 << 9)
+#define CLK_SMMU_ISP_MASK (1 << 8)
+#define CLK_GICISP_MASK (1 << 7)
+#define CLK_ARM9S_MASK (1 << 6)
+#define CLK_MCUISP_MASK (1 << 5)
+#define CLK_SCALERP_MASK (1 << 4)
+#define CLK_SCALERC_MASK (1 << 3)
+#define CLK_FD_MASK (1 << 2)
+#define CLK_DRC_MASK (1 << 1)
+#define CLK_ISP_MASK (1 << 0)
+
+/* CLK_GATE_IP_ISP1 */
+#define CLK_SPI1_ISP_MASK (1 << 13)
+#define CLK_SPI0_ISP_MASK (1 << 12)
+#define CLK_SMMU3DNR_MASK (1 << 7)
+#define CLK_SMMUDIS1_MASK (1 << 6)
+#define CLK_SMMUDIS0_MASK (1 << 5)
+#define CLK_SMMUODC_MASK (1 << 4)
+#define CLK_3DNR_MASK (1 << 2)
+#define CLK_DIS_MASK (1 << 1)
+#define CLK_ODC_MASK (1 << 0)
+
+/* CLK_GATE_IP_GSCL */
+#define CLK_SMMUFIMC_LITE2_MASK (1 << 20)
+#define CLK_SMMUFIMC_LITE1_MASK (1 << 12)
+#define CLK_SMMUFIMC_LITE0_MASK (1 << 11)
+#define CLK_SMMUGSCL3_MASK (1 << 10)
+#define CLK_SMMUGSCL2_MASK (1 << 9)
+#define CLK_SMMUGSCL1_MASK (1 << 8)
+#define CLK_SMMUGSCL0_MASK (1 << 7)
+#define CLK_GSCL_WRAP_B_MASK (1 << 6)
+#define CLK_GSCL_WRAP_A_MASK (1 << 5)
+#define CLK_CAMIF_TOP_MASK (1 << 4)
+#define CLK_GSCL3_MASK (1 << 3)
+#define CLK_GSCL2_MASK (1 << 2)
+#define CLK_GSCL1_MASK (1 << 1)
+#define CLK_GSCL0_MASK (1 << 0)
+
+/* CLK_GATE_IP_MFC */
+#define CLK_SMMUMFCR_MASK (1 << 2)
+#define CLK_SMMUMFCL_MASK (1 << 1)
+#define CLK_MFC_MASK (1 << 0)
+
+#define SCLK_MPWM_ISP_MASK (1 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_SMMUTVX_MASK (1 << 9)
+#define CLK_ASYNCTVX_MASK (1 << 7)
+#define CLK_HDMI_MASK (1 << 6)
+#define CLK_MIXER_MASK (1 << 5)
+#define CLK_DSIM1_MASK (1 << 3)
+
+/* CLK_GATE_IP_GEN */
+#define CLK_SMMUMDMA1_MASK (1 << 9)
+#define CLK_SMMUJPEG_MASK (1 << 7)
+#define CLK_SMMUROTATOR_MASK (1 << 6)
+#define CLK_MDMA1_MASK (1 << 4)
+#define CLK_JPEG_MASK (1 << 2)
+#define CLK_ROTATOR_MASK (1 << 1)
+
+/* CLK_GATE_IP_FSYS */
+#define CLK_WDT_IOP_MASK (1 << 30)
+#define CLK_SMMUMCU_IOP_MASK (1 << 26)
+#define CLK_SATA_PHY_I2C_MASK (1 << 25)
+#define CLK_SATA_PHY_CTRL_MASK (1 << 24)
+#define CLK_MCUCTL_MASK (1 << 23)
+#define CLK_NFCON_MASK (1 << 22)
+#define CLK_SMMURTIC_MASK (1 << 11)
+#define CLK_RTIC_MASK (1 << 9)
+#define CLK_MIPI_HSI_MASK (1 << 8)
+#define CLK_USBOTG_MASK (1 << 7)
+#define CLK_SATA_MASK (1 << 6)
+#define CLK_PDMA1_MASK (1 << 2)
+#define CLK_PDMA0_MASK (1 << 1)
+#define CLK_MCU_IOP_MASK (1 << 0)
+
+/* CLK_GATE_IP_PERIC */
+#define CLK_HS_I2C3_MASK (1 << 31)
+#define CLK_HS_I2C2_MASK (1 << 30)
+#define CLK_HS_I2C1_MASK (1 << 29)
+#define CLK_HS_I2C0_MASK (1 << 28)
+#define CLK_AC97_MASK (1 << 27)
+#define CLK_SPDIF_MASK (1 << 26)
+#define CLK_PCM2_MASK (1 << 23)
+#define CLK_PCM1_MASK (1 << 22)
+#define CLK_I2S2_MASK (1 << 21)
+#define CLK_I2S1_MASK (1 << 20)
+#define CLK_SPI2_MASK (1 << 18)
+#define CLK_SPI0_MASK (1 << 16)
+#define CLK_I2CHDMI_MASK (1 << 14)
+#define CLK_I2C7_MASK (1 << 13)
+#define CLK_I2C6_MASK (1 << 12)
+#define CLK_I2C5_MASK (1 << 11)
+#define CLK_I2C4_MASK (1 << 10)
+#define CLK_I2C3_MASK (1 << 9)
+#define CLK_I2C2_MASK (1 << 8)
+#define CLK_I2C1_MASK (1 << 7)
+#define CLK_I2C0_MASK (1 << 6)
+
+/* CLK_GATE_IP_PERIS */
+#define CLK_RTC_MASK (1 << 20)
+#define CLK_TZPC9_MASK (1 << 15)
+#define CLK_TZPC8_MASK (1 << 14)
+#define CLK_TZPC7_MASK (1 << 13)
+#define CLK_TZPC6_MASK (1 << 12)
+#define CLK_TZPC5_MASK (1 << 11)
+#define CLK_TZPC4_MASK (1 << 10)
+#define CLK_TZPC3_MASK (1 << 9)
+#define CLK_TZPC2_MASK (1 << 8)
+#define CLK_TZPC1_MASK (1 << 7)
+#define CLK_TZPC0_MASK (1 << 6)
+#define CLK_CHIPID_MASK (1 << 0)
+
+/* CLK_GATE_BLOCK */
+#define CLK_ACP_MASK (1 << 7)
+
+/* CLK_GATE_IP_CDREX */
+#define CLK_TZASC_DRBXW_MASK (1 << 23)
+#define CLK_TZASC_DRBXR_MASK (1 << 22)
+#define CLK_TZASC_XLBXW_MASK (1 << 21)
+#define CLK_TZASC_XLBXR_MASK (1 << 20)
+#define CLK_TZASC_XR1BXW_MASK (1 << 19)
+#define CLK_TZASC_XR1BXR_MASK (1 << 18)
+#define CLK_DPHY1_MASK (1 << 5)
+#define CLK_DPHY0_MASK (1 << 4)
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
+
+#define PHY_CON0_RESET_VAL 0x17020a40
+#define P0_CMD_EN (1 << 14)
+#define BYTE_RDLVL_EN (1 << 13)
+#define CTRL_SHGATE (1 << 8)
+
+#define PHY_CON1_RESET_VAL 0x09210100
+#define CTRL_GATEDURADJ_MASK (0xf << 20)
+
+#define PHY_CON2_RESET_VAL 0x00010004
+#define INIT_DESKEW_EN (1 << 6)
+#define RDLVL_GATE_EN (1 << 24)
+
+/*ZQ Configurations */
+#define PHY_CON16_RESET_VAL 0x08000304
+
+#define ZQ_CLK_DIV_EN (1 << 18)
+#define ZQ_MANUAL_STR (1 << 1)
+#define ZQ_DONE (1 << 0)
+
+#define CTRL_RDLVL_GATE_ENABLE 1
+#define CTRL_RDLVL_GATE_DISABLE 1
+
+/* Direct Command */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_PALL 0x01000000
+#define DIRECT_CMD_ZQINIT 0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT 28
+#define DIRECT_CMD_CHIP_SHIFT 20
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL 0x0
+#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
+#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
+#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
+#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM 0x5
+#define IMP_OUTPUT_DRV_30_OHM 0x7
+#define CA_CK_DRVR_DS_OFFSET 9
+#define CA_CKE_DRVR_DS_OFFSET 6
+#define CA_CS_DRVR_DS_OFFSET 3
+#define CA_ADR_DRVR_DS_OFFSET 0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+
+struct mem_timings;
+
+/* Errors that we can encourter in low-level setup */
+enum {
+ SETUP_ERR_OK,
+ SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+ SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
+
+/* Functions common between LPDDR2 and DDR3 */
+void sdelay(unsigned long);
+
+/* CPU info initialization code */
+void cpu_info_init(void);
+
+void mem_ctrl_init(void);
+/*
+ * Memory variant specific initialization code
+ *
+ * @param mem Memory timings for this memory type.
+ * @param mem_iv_size Memory interleaving size is a configurable parameter
+ * which the DMC uses to decide how to split a memory
+ * chunk into smaller chunks to support concurrent
+ * accesses; may vary across boards.
+ * @return 0 if ok, SETUP_ERR_... if there is a problem
+ */
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+
+/* FIXME(dhendrix): why is this here? commenting it out and we'll use
+ clock_init.h instead */
+//void system_clock_init(void);
+
+void tzpc_init(void);
+/*
+ * Configure ZQ I/O interface
+ *
+ * @param mem Memory timings for this memory type.
+ * @param phy0_ctrl Pointer to struct containing PHY0 control reg
+ * @param phy1_ctrl Pointer to struct containing PHY1 control reg
+ * @return 0 if ok, -1 on error
+ */
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl);
+
+/*
+ * Send NOP and MRS/EMRS Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/*
+ * Send PALL Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/*
+ * Configure the memconfig and membaseconfig registers
+ *
+ * @param mem Memory timings for this memory type.
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ */
+void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/* Set the PS-Hold drive value */
+void ps_hold_setup(void);
+/*
+ * Reset the DLL. This function is common between DDR3 and LPDDR2.
+ * However, the reset value is different. So we are passing a flag
+ * ddr_mode to distinguish between LPDDR2 and DDR3.
+ *
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ * @param ddr_mode Type of DDR memory
+ */
+void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
+#endif
diff --git a/src/cpu/samsung/exynos5250/spi.h b/src/cpu/samsung/exynos5250/spi.h
new file mode 100644
index 0000000..3430ac1
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/spi.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+ unsigned int ch_cfg; /* 0x00 */
+ unsigned char reserved0[4];
+ unsigned int mode_cfg; /* 0x08 */
+ unsigned int cs_reg; /* 0x0c */
+ unsigned char reserved1[4];
+ unsigned int spi_sts; /* 0x14 */
+ unsigned int tx_data; /* 0x18 */
+ unsigned int rx_data; /* 0x1c */
+ unsigned int pkt_cnt; /* 0x20 */
+ unsigned char reserved2[4];
+ unsigned int swap_cfg; /* 0x28 */
+ unsigned int fb_clk; /* 0x2c */
+ unsigned char padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ 50000000
+
+#define SPI_TIMEOUT_MS 10
+
+#define SF_READ_DATA_CMD 0x3
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN (1 << 6)
+#define SPI_CH_RST (1 << 5)
+#define SPI_SLAVE_MODE (1 << 4)
+#define SPI_CH_CPOL_L (1 << 3)
+#define SPI_CH_CPHA_B (1 << 2)
+#define SPI_RX_CH_ON (1 << 1)
+#define SPI_TX_CH_ON (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE (1 << 25)
+#define SPI_FIFO_LVL_MASK 0x1ff
+#define SPI_TX_LVL_OFFSET 6
+#define SPI_RX_LVL_OFFSET 15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS (0 << 0)
+#define SPI_FB_DELAY_90 (1 << 0)
+#define SPI_FB_DELAY_180 (2 << 0)
+#define SPI_FB_DELAY_270 (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN (1 << 16)
+
+/* Swap config */
+#define SPI_TX_SWAP_EN (1 << 0)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_TX_HWORD_SWAP (1 << 3)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_RX_SWAP_EN (1 << 4)
+#define SPI_RX_BYTE_SWAP (1 << 6)
+#define SPI_RX_HWORD_SWAP (1 << 7)
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/src/cpu/samsung/exynos5250/sys_proto.h b/src/cpu/samsung/exynos5250/sys_proto.h
new file mode 100644
index 0000000..f25dcd1
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/sys_proto.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_SYS_PROTO_H__
+#define __ASM_ARM_ARCH_EXYNOS5_SYS_PROTO_H__
+
+#include <asm/arch-exynos/sys_proto.h>
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_SYS_PROTO_H__ */
diff --git a/src/cpu/samsung/exynos5250/sysreg.h b/src/cpu/samsung/exynos5250/sysreg.h
new file mode 100644
index 0000000..f081495
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/sysreg.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Register map for Exynos5 sysreg
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS5_SYSREG_H__
+#define __EXYNOS5_SYSREG_H__
+
+/* sysreg map */
+struct exynos5_sysreg {
+ /* Add registers as and when required */
+ unsigned char res1[0x214];
+ unsigned int disp1blk_cfg;
+ unsigned char res2[0x18];
+ unsigned int usb20_phy_cfg;
+};
+
+#define FIMDBYPASS_DISP1 (1 << 15)
+#define USB20_PHY_CFG_EN (1 << 0)
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/tzpc.h b/src/cpu/samsung/exynos5250/tzpc.h
new file mode 100644
index 0000000..b9937b8
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/tzpc.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TZPC_H_
+#define __TZPC_H_
+
+#ifndef __ASSEMBLER__
+struct exynos5_tzpc {
+ unsigned int r0size;
+ char res1[0x7FC];
+ unsigned int decprot0stat;
+ unsigned int decprot0set;
+ unsigned int decprot0clr;
+ unsigned int decprot1stat;
+ unsigned int decprot1set;
+ unsigned int decprot1clr;
+ unsigned int decprot2stat;
+ unsigned int decprot2set;
+ unsigned int decprot2clr;
+ unsigned int decprot3stat;
+ unsigned int decprot3set;
+ unsigned int decprot3clr;
+ char res2[0x7B0];
+ unsigned int periphid0;
+ unsigned int periphid1;
+ unsigned int periphid2;
+ unsigned int periphid3;
+ unsigned int pcellid0;
+ unsigned int pcellid1;
+ unsigned int pcellid2;
+ unsigned int pcellid3;
+};
+#endif
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/uart.h b/src/cpu/samsung/exynos5250/uart.h
new file mode 100644
index 0000000..8190c67
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/uart.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2012 The ChromiumOS Authors
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ * Heungjun Kim <riverful.kim at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This file is based off of arch/arm/include/asm/arch-exynos5/uart.h
+ * from u-boot.
+ */
+
+#ifndef __EXYNOS5_UART_H_
+#define __EXYNOS5_UART_H_
+
+#include <types.h>
+
+/* FIXME: should these move into a Kconfig file? */
+#define EXYNOS5_UART0_BASE 0x12c00000
+#define EXYNOS5_UART1_BASE 0x12c10000
+#define EXYNOS5_UART2_BASE 0x12c20000
+#define EXYNOS5_UART3_BASE 0x12c30000
+#define EXYNOS5_ISP_UART_BASE 0x13190000
+
+#if 0
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+#endif
+
+struct s5p_uart {
+ uint32_t ulcon;
+ uint32_t ucon;
+ uint32_t ufcon;
+ uint32_t umcon;
+ uint32_t utrstat;
+ uint32_t uerstat;
+ uint32_t ufstat;
+ uint32_t umstat;
+ uint8_t utxh;
+ uint8_t res1[3];
+ uint8_t urxh;
+ uint8_t res2[3];
+ uint32_t ubrdiv;
+ uint32_t ufracval;
+ uint32_t uintp;
+ uint32_t uints;
+ uint32_t uintm;
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
+#endif
diff --git a/src/cpu/samsung/exynos5250/watchdog.h b/src/cpu/samsung/exynos5250/watchdog.h
new file mode 100644
index 0000000..f35dde4
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/watchdog.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_WATCHDOG_H__
+#define __ASM_ARM_ARCH_EXYNOS5_WATCHDOG_H__
+
+#include <asm/arch-exynos/watchdog.h>
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_WATCHDOG_H__ */
More information about the coreboot
mailing list