[coreboot] Large BAR size crashes the BIOS
u9012063 at gmail.com
Thu Sep 6 02:19:24 CEST 2012
I'm newbie to PC BIOS and would like to ask a couple of questions.
I had a PCIe device (it's an NTB device) with default the size of its
BAR2 is 64M. I boot up my machine and reprogram the BAR2 size to 2G
and reboot. Then I found I no longer to boot up my Desktop (ASUS),
even when I unplug the PCIe deivce. There is no POST message shown up,
no beeps, and nothing shown on screen. I guess requesting 2G PCI space
causes address space overflow and overwrite the BIOS code?
I'm really curious about the reason so I start looking at the coreboot
code in LXR to see how BIOS handles large PCI device space. Can
someone give me some directions in the source code?
1. Where is the address assignment / predefined address location for
all the devices?
2. Is there a upper limit for PCI bar size? or is there an address
range defined for all PCI devices? I checked the pci_read_rom_resource
and it seems not having an upper bound.
3. Is BIOS running at real mode or protected mode?
4. Is there an upper address limit that a BIOS can address? Someone
told me BIOS can only addresses up to 8G.
btw, I'm using the BIOS code from ASUS (model: P8Q67)
Thanks a lot!
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