[coreboot] porting to GA-945GCM

Wed Apr 10 09:22:49 CEST 2013

Dear Guangzhe Lee,

Am Mittwoch, den 10.04.2013, 13:31 +0800 schrieb CTO of SPCTNC:

[…]

> I'm from China.
> 
> My name is Guangzhe Lee. and I'm new in Coreboot.

welcome to coreboot! Could you please tell me, what your first name
(also known as given name) is. Is it Guangzhe? My first name is Paul.

Please note that coreboot is officially spelled all lowercase.y

As a side note, please adhere to the netiquette [1] and most importantly
configure your mail program, Microsoft Outlook, to just send plain text
messages and no HTML stuff.

> I'm porting Coreboot to Gigabyte GA-945GCM board( LGA775socket / i945GC /
> ICH7 / IT8718F ).

Awesome. Please always provide URLs to make looking up information easy.
On the GIGABYTE Web site I found not exactly the GA-945GCM but only some
boards with a suffix, like GA-945GCM-S2 [2].

> Romstage passed successfully, but after jumping to Ramstage console message
> don't appear any more.

That is strange. Could you also post your .config and upload your
current patch to our Gerrit instance for review [3]. (You can use your
Google Mail account for the OpenID login.)

> I tried to debug by GDB (using ttyS0), but it also fail.

I think GDB is not tested that much. Thanks for doing that. I am going
to split that problem into a separate thread though so that for example
the mailing list archive is easier to use.

> I try the POST code, but the post card always displays "2C"->"2D"->"2E" ->
> "2F". My post codes don't appear on the post card.

As we do not have your no code, we cannot say for sure where this hangs.

> Please help me.
> 
> - How can I fix the problem.
> 
> - How can I fix gdb problem.
>
> I'm sending 
> 
>   -  gdb message   and
> 
>   -  the console log of the booting.

[… GDB log …]

> <<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>>
>
> 
> coreboot-4.0-3784-g1cc4737-dirty Fri Apr  5 22:44:35 BOT 2013 starting...
>
> 
> Intel(R) 82945GC Chipset
> 
> (G)MCH capable of up to DDR2-533
> 
> Setting up static southbridge registers... GPIOS... done.
> 
> Disabling Watchdog reboot... done.
> 
> Setting up static northbridge registers... done.
> 
> Waiting for MCHBAR to come up...ok
> 
> PM1_CNT: 00001c00
> 
> SMBus controller enabled.
> 
> Setting up RAM controller.
> 
> This mainboard supports Dual Channel Operation.
> 
> DDR II Channel 0 Socket 0: x8DDS
> 
> DDR II Channel 0 Socket 1: N/A
> 
> DDR II Channel 1 Socket 0: N/A
> 
> DDR II Channel 1 Socket 1: N/A
> 
> lowest common cas = 4
> 
> Probing Speed 2
> 
>   DIMM: 0
> 
>     Current CAS mask: 0070; idx=1, tCLK=30, tAC=45:    OK
> 
>   DIMM: 1
> 
>   DIMM: 2
> 
>   DIMM: 3
> 
>   freq_cas_mask for speed 2: 0030
> 
> Memory will be driven at 667MHz with CAS=4 clocks
> 
> tRAS = 15 cycles
> 
> tRP = 5 cycles
> 
> tRCD = 5 cycles
> 
> Refresh: 7.8us
> 
> tWR = 5 cycles
> 
> DIMM 0 side 0 = 1024 MB
> 
> DIMM 0 side 1 = 1024 MB
> 
> tRFC = 43 cycles
> 
> Setting Graphics Frequency...
> 
> FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz
> 
> Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok
> 
> Setting mode of operation for memory channels...Single Channel 0 only.
> 
> DCC=0x00000400
> 
> Programming Clock Crossing...MEM=memclk: unknown register value 0
> 
> memclk: unknown register value 0

Not sure if the above is important.

[…]

> RAM initialization finished.

That is a good thing as RAM is the hardest part. Otherwise this was
suspected as the 945* chipset is one of the best supported and most
tested ones.

> Setting up Egress Port RCRB
> 
> Loading port arbitration table ...ok
> 
> Wait for VC1 negotiation ...ok
> 
> Setting up DMI RCRB
> 
> Wait for VC1 negotiation ...done..
> 
> Internal graphics: enabled
> 
> Waiting for DMI hardware...ok
> 
> Enabling PCI Express x16 Link
> 
> SLOTSTS: 0000
> 
> Disabling PCI Express x16 Link
> 
> Wait for link to enter detect state... ok
> 
> Setting up Root Complex Topology
> 
> <-Setting up Root Complex Topology
> 
> high_ram_base: 0x        7f6e0000, 0x          120000
> 
> Loading image.
> 
> CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000
> 
> CBFS: CBFS location: 0x0~0x7f000, align: 64
> 
> CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
> 
> CBFS:  - load entry 0x0 file name (16 bytes)...
> 
> CBFS:  (unmatched file @0x0: cmos_layout.bin)
> 
> CBFS:  - load entry 0x540 file name (32 bytes)...
> 
> CBFS:  (unmatched file @0x540: fallback/romstage)
> 
> CBFS:  - load entry 0xca00 file name (32 bytes)...
> 
> CBFS: Found file (offset=0xca38, len=367928).
> 
> CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @
> 0x1
> 
> 00000
> 
> CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900
> 
> CBFS: src=10f2efa, dst=10f2efa
> 
> CBFS: stage loaded.
> 
> Jumping to image.

Normally at least the coreboot header should be printed, so jumping to
the image fails.

What upstream revision do you base your changes on? Do not forget to
post your Kconfig file `.config`. And lastly show us the content of your
ROM by pasting the output of the following command.

    ./build/cbfstool build/coreboot.rom print

Thanks,

Paul

[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette
[2] http://www.gigabyte.de/products/product-page.aspx?pid=2520#ov
[3] http://www.coreboot.org/Git
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