[coreboot] Patch set updated for coreboot: 8c710f6 Add MMCONF resource to AMD fam15tn PCI_DOMAIN

[Steven Sherk (steven.sherk@se-eng.com)]

Steven Sherk (steven.sherk at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2260

-gerrit

commit 8c710f65d0cd57aacaf8c20f4f748c4e76fa5337
Author: Steven Sherk <steven.sherk at se-eng.com>
Date:   Fri Feb 1 09:22:35 2013 -0700

    Add MMCONF resource to AMD fam15tn PCI_DOMAIN
    
    In the process of verifying change it was discovered the MMCONF
    default base address 0xA0000000 was set below mem_top 0xE0000000
    and bus number 256 wasn't a relistic number. The Kconfig defaults were
    changed to mirror fam15 defaults base address 0xF8000000 and bus
    number 64. Verified changes with boot to OS.
    
    This is a port of the following:
    commit d5c998be99709c92f200b3b08aed2ca3fee2d519
    
    	The coreboot resource allocator doesn't respect resources
    	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
    	PCI_DOMAIN to prevent overlap with PCI devices.
    
    original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
        Signed-off-by: Marc Jones <marc.jones at se-eng.com
        URL - http://review.coreboot.org/#/c/2167/
    
    Change-Id: I47660061538f8889f528b9b880a82645074886a7
    Signed-off-by: Steven Sherk <steven.sherk at se-eng.com>
---
 src/northbridge/amd/agesa/family15tn/Kconfig       |  4 +--
 src/northbridge/amd/agesa/family15tn/northbridge.c | 31 +++++++++++++---------
 2 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig
index b78b01d..5f08593 100644
--- a/src/northbridge/amd/agesa/family15tn/Kconfig
+++ b/src/northbridge/amd/agesa/family15tn/Kconfig
@@ -33,10 +33,10 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 
 config MMCONF_BASE_ADDRESS
 	hex
-	default 0xA0000000
+	default 0xF8000000
 
 config MMCONF_BUS_NUMBER
 	int
-	default 256
+	default 64
 
 endif
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index eb63ead..68b6429 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -337,6 +337,19 @@ static void nb_read_resources(device_t dev)
 			amdfam15_link_read_bases(dev, nodeid, link->link_num);
 		}
 	}
+
+	/*
+	 * This MMCONF resource must be reserved in the PCI_DOMAIN.
+	 * It is not honored by the coreboot resource allocator if it is in
+	 * the APIC_CLUSTER.
+	 */
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *resource = new_resource(dev, 0xc0010058);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+#endif
 }
 
 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
@@ -440,6 +453,12 @@ static void nb_set_resources(device_t dev)
 			assign_resources(bus);
 		}
 	}
+
+	/* Print the MMCONF region if it has been reserved. */
+	res = find_resource(dev, 0xc0010058);
+	if (res) {
+		report_resource_stored(dev, res, " <mmconfig>");
+	}
 }
 
 static void northbridge_init(struct device *dev)
@@ -1077,22 +1096,10 @@ static void cpu_bus_noop(device_t dev)
 
 static void cpu_bus_read_resources(device_t dev)
 {
-#if CONFIG_MMCONF_SUPPORT
-	struct resource *resource = new_resource(dev, 0xc0010058);
-	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
-		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
-#endif
 }
 
 static void cpu_bus_set_resources(device_t dev)
 {
-	struct resource *resource = find_resource(dev, 0xc0010058);
-	if (resource) {
-		report_resource_stored(dev, resource, " <mmconfig>");
-	}
-	pci_dev_set_resources(dev);
 }
 
 static struct device_operations cpu_bus_ops = {