[coreboot] New patch to review for coreboot: 02a1c7b Persimmon: drop useless DDR3 voltage code copied from Inagua

[Jens Rottmann (JRottmann@LiPPERTembedded.de)]

Jens Rottmann (JRottmann at LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2448

-gerrit

commit 02a1c7b40fd5b41cd8360162c55e5df71c33db87
Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
Date:   Mon Feb 18 20:26:50 2013 +0100

    Persimmon: drop useless DDR3 voltage code copied from Inagua
    
    Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V,
    which it does according to data read from the SO-DIMM's SPD EEPROM.
    
    On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are
    unconnected, there is no way to change the 1.5 V DDR3 voltage (save
    unsoldering a resistor). The whole code copied over from Inagua is
    useless.
    
    Removed the code, instead a comment hints at Inagua, for people who do designs
    based on Persimmon but do have a way to change VMEM.
    
    The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code
    select the RAM timings for the actually supplied voltage instead of the
    hoped-for but unavailable lower voltage. I have no idea how to test this, but
    in any case it can't hurt.
    
    Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba
    Signed-off-by: Jens Rottmann <JRottmann at LiPPERTembedded.de>
---
 src/mainboard/amd/persimmon/BiosCallOuts.c | 82 ++----------------------------
 1 file changed, 4 insertions(+), 78 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 52eb9dd..b355278 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -445,84 +445,10 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt
 /*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-	AGESA_STATUS		Status;
-	UINTN			 FcnData;
-	MEM_DATA_STRUCT	 *MemData;
-	UINT32			AcpiMmioAddr;
-	UINT32			GpioMmioAddr;
-	UINT8			 Data8;
-	UINT16			Data16;
-	UINT8			 TempData8;
-
-	FcnData = Data;
-	MemData = ConfigPtr;
-
-	Status	= AGESA_SUCCESS;
-	/* Get SB MMIO Base (AcpiMmioAddr) */
-	WriteIo8 (0xCD6, 0x27);
-	Data8	 = ReadIo8(0xCD7);
-	Data16	= Data8<<8;
-	WriteIo8 (0xCD6, 0x26);
-	Data8	 = ReadIo8(0xCD7);
-	Data16	|= Data8;
-	AcpiMmioAddr = (UINT32)Data16 << 16;
-	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2+BIT3;
-	Data8 &= ~BIT4;
-	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2+BIT3;
-	Data8 &= ~BIT4;
-	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-	switch(MemData->ParameterListPtr->DDR3Voltage){
-	case VOLT1_35:
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-	}
-	return Status;
+	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
+	// Make sure the right speed settings are selected.
+	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
+	return AGESA_SUCCESS;
 }
 
 /*	Call the host environment interface to provide a user hook opportunity. */