[coreboot] Patch set updated for coreboot: 93b5c94 snow: add cpu_cluster and domain resources via devicetree.cb

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2420

-gerrit

commit 93b5c94d881c14ca507277e0bd6658e020170174
Author: David Hendricks <dhendrix at chromium.org>
Date:   Fri Feb 15 16:23:23 2013 -0800

    snow: add cpu_cluster and domain resources via devicetree.cb
    
    This patch will cause the resource allocator to actually set aside
    the memory resources using methods in the previous patch. The coreboot
    table output will include "RAM" entries (there were none before):
    
    coreboot memory table:
     0. 0000000040400000-00000000bff001ff: RAM
     1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES
     2. 00000000bff01000-00000000bfffffff: RAM
    
    Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/mainboard/google/snow/devicetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index f88835e..4c88ea8 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -19,8 +19,14 @@
 
 # FIXME: this is just a stub for now
 chip cpu/samsung/exynos5250
+
+device cpu_cluster 0 on
+end
+
+device domain 0 on
 	chip drivers/generic/generic # I2C0 controller
 		device i2c 6 on end # ?
 		device i2c 9 on end # ?
 	end
 end
+end