[coreboot] New patch to review for coreboot: 81c9624 Omit extra clock timing table entries to save some space
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Fri Jan 11 02:40:38 CET 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2088
-gerrit
commit 81c9624ff1fa79b7feeaa0bacaf314be63f3c764
Author: David Hendricks <dhendrix at chromium.org>
Date: Mon Dec 31 16:34:21 2012 -0800
Omit extra clock timing table entries to save some space
This is just a temporary hack to give us some more room to breathe
while developing proper bootblock and romstage code...
Change-Id: I0d114b6e69187bf4d0dce6ab2ac538c3e112bd7f
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/cpu/samsung/exynos5250/clock.c | 9 +++++++++
src/cpu/samsung/exynos5250/clock_init.c | 15 +++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c
index 0250d77..41a653e 100644
--- a/src/cpu/samsung/exynos5250/clock.c
+++ b/src/cpu/samsung/exynos5250/clock.c
@@ -169,6 +169,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
+ /* FIXME (dhendrix): temporarily omitted for space */
+#ifndef __PRE_RAM__
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
@@ -202,6 +204,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
+#endif /* __PRE_RAM__ */
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
@@ -239,10 +242,13 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
+ /* FIXME (dhendrix): temporarily omitted for space */
+#ifndef __PRE_RAM__
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
}
+#endif /* __PRE_RAM__ */
return sub_clk;
}
@@ -466,6 +472,8 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
return 0;
}
+/* FIXME(dhendrix): temporarily omitted for space */
+#if 0
int clock_set_mshci(enum periph_id peripheral)
{
struct exynos5_clock *clk =
@@ -504,6 +512,7 @@ int clock_set_mshci(enum periph_id peripheral)
}
return 0;
}
+#endif
#ifdef CONFIG_OF_CONTROL
int clock_decode_periph_id(const void *blob, int node)
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index d2abfa9..a8a50ea 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -40,6 +40,9 @@
#include "setup.h"
struct arm_clk_ratios arm_clk_ratios[] = {
+ /* FIXME(dhendrix): this is just a stop-gap measure to reduce image
+ size while we implement bootblock and romstage functionality */
+#if 0
{
.arm_freq_mhz = 600,
@@ -116,6 +119,8 @@ struct arm_clk_ratios arm_clk_ratios[] = {
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}, {
+#endif
+ {
.arm_freq_mhz = 1700,
.apll_mdiv = 0x1a9,
@@ -238,6 +243,10 @@ struct mem_timings mem_timings[] = {
.send_zq_init = 1,
.impedance = IMP_OUTPUT_DRV_30_OHM,
.gate_leveling_enable = 0,
+ /* FIXME(dhendrix): this is just a stop-gap measure to reduce image
+ size while we implement bootblock and romstage functionality */
+ }
+#if 0
}, {
.mem_manuf = MEM_MANUF_SAMSUNG,
.mem_type = DDR_MODE_DDR3,
@@ -552,6 +561,7 @@ struct mem_timings mem_timings[] = {
.impedance = IMP_OUTPUT_DRV_40_OHM,
.gate_leveling_enable = 1,
}
+#endif
};
/**
@@ -723,6 +733,8 @@ struct arm_clk_ratios *get_arm_ratios(void)
struct mem_timings *clock_get_mem_timings(void)
{
+ return &mem_timings[0];
+#if 0
struct mem_timings *mem;
enum ddr_mode mem_type;
enum mem_manuf mem_manuf;
@@ -741,6 +753,7 @@ struct mem_timings *clock_get_mem_timings(void)
}
}
return NULL;
+#endif
}
void system_clock_init()
@@ -855,7 +868,6 @@ void system_clock_init()
setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL);
}
-
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
@@ -979,7 +991,6 @@ void system_clock_init()
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
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