[coreboot] Patch set updated for coreboot: 5d4c30d F15tn: Fix all warnings, enable warnings as errors
Martin Roth (martin.roth@se-eng.com)
gerrit at coreboot.org
Mon Jan 21 19:15:13 CET 2013
Martin Roth (martin.roth at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2171
-gerrit
commit 5d4c30d90b2ffad4fef534e95c3b57465e33e0ec
Author: Martin Roth <martin.roth at se-eng.com>
Date: Thu Jan 17 16:28:30 2013 -0700
F15tn: Fix all warnings, enable warnings as errors
Enable 'all warnings being treated as errors' in thatcher and parmer.
Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
this is the location of the previous definition
In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
this is the location of the previous definition
Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/mainboard/amd/parmer/Kconfig | 4 ----
src/mainboard/amd/parmer/mainboard.c | 2 +-
src/mainboard/amd/thatcher/Kconfig | 4 ----
src/mainboard/amd/thatcher/mainboard.c | 2 +-
src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c | 4 ++--
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h | 4 ++++
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c | 4 ++--
src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 2 +-
12 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
index a4da2e2..9e42697 100644
--- a/src/mainboard/amd/parmer/Kconfig
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -100,10 +100,6 @@ config VGA_BIOS_ID
string
default "1002,9900"
-config WARNINGS_ARE_ERRORS
- bool
- default n
-
config HUDSON_LEGACY_FREE
bool
default y
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
index a83cd42..7c5dfc0 100644
--- a/src/mainboard/amd/parmer/mainboard.c
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -22,10 +22,10 @@
#include <device/pci.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
+#include "BiosCallOuts.h"
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
-#include "BiosCallOuts.h"
#include <cpu/amd/agesa/s3_resume.h>
#include "agesawrapper.h"
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index 0fe97fa..a68226c 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -101,10 +101,6 @@ config VGA_BIOS_ID
string
default "1002,9917"
-config WARNINGS_ARE_ERRORS
- bool
- default n
-
config HUDSON_LEGACY_FREE
bool
default y
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index bc1d591..d1c389c 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -22,10 +22,10 @@
#include <device/pci.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
+#include "BiosCallOuts.h"
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
-#include "BiosCallOuts.h"
#include <cpu/amd/agesa/s3_resume.h>
#include "agesawrapper.h"
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index df632e3..a22fc9d 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -29,12 +29,12 @@
#include <lib.h>
#include <cpu/cpu.h>
#include <cbmem.h>
+#include <AGESA.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/mtrr.h>
#include <Porting.h>
-#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
#include <cpu/amd/amdfam15.h>
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
index ffb33ab..4038181 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -288,5 +288,5 @@ GetGlobalCpuFeatureListAddress (
AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
- *Address = (UINT64 *)(AddressValue);
+ *Address = (UINT64 *)(intptr_t)(AddressValue);
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
index af00f26..525bb1d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c
@@ -242,7 +242,7 @@ SaveDeviceContext (
UINT64 EndAddress;
VOID *OrMask;
- StartAddress = (UINT64)DeviceList;
+ StartAddress = (UINT64)(intptr_t)DeviceList;
Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
@@ -306,7 +306,7 @@ SaveDeviceContext (
break;
}
}
- EndAddress = (UINT64) OrMask;
+ EndAddress = (UINT64)(intptr_t)OrMask;
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
index 5eda346..460955e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c
@@ -232,7 +232,7 @@ GetPstateGatherDataAddressAtPost (
AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(AddressValue);
+ *Ptr = (UINT64 *)(intptr_t)(AddressValue);
return AGESA_SUCCESS;
}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
index 173044c..96e6c7f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h
@@ -375,7 +375,11 @@ typedef struct {
#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
#define APIC_EXT_BRDCST_MASK 0x000E0000ul
#define APIC_ENABLE_BIT 0x00000800ul
+
+#ifndef LOCAL_APIC_ADDR
#define LOCAL_APIC_ADDR 0xFEE00000ul
+#endif
+
#define INT_CMD_REG_LO 0x300
#define INT_CMD_REG_HI 0x310
#define REMOTE_MSG_REG 0x380
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index 63f255b..b93f4b6 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -350,7 +350,7 @@ MemNInitNBDataTN (
NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb;
NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
NBPtr->HtMemMapInit = MemNHtMemMapInitTN;
- NBPtr->SyncAddrMapToAllNodes = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
+ NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingTN;
NBPtr->AfterDqsTraining = MemNAfterDQSTrainingTN;
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
index e203fd0..13900cd 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c
@@ -514,13 +514,13 @@ MemNInsDlyCompareTestPatternNb (
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*/
-BOOLEAN
+VOID
MemNTrainingFlowUnb (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
- return TRUE;
+ return;
}
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
index 6174c98..98a78f1 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h
@@ -1417,7 +1417,7 @@ GetTrainDlyFromHeapNb (
IN DRBN Drbn
);
-BOOLEAN
+VOID
MemNTrainingFlowUnb (
IN OUT MEM_NB_BLOCK *NBPtr
);
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