[coreboot] New patch to review for coreboot: 0ab3fec exynos5: add GPIO port enums

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2602

-gerrit

commit 0ab3fec064562b446c232d37de158a69d646182c
Author: David Hendricks <dhendrix at chromium.org>
Date:   Wed Mar 6 20:11:20 2013 -0800

    exynos5: add GPIO port enums
    
    This adds an enum for GPIO ports on the Exynos5. To make them
    useful, they are assigned the absolute MMIO address where a
    s5p_gpio_bank struct can point to.
    
    Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/cpu/samsung/exynos5-common/gpio.h | 68 +++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/src/cpu/samsung/exynos5-common/gpio.h b/src/cpu/samsung/exynos5-common/gpio.h
index 0de53f6..0e4afc5 100644
--- a/src/cpu/samsung/exynos5-common/gpio.h
+++ b/src/cpu/samsung/exynos5-common/gpio.h
@@ -214,4 +214,72 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 #define EXYNOS_GPIO_DRV_4X	0x3
 #define EXYNOS_GPIO_DRV_FAST	0x0
 #define EXYNOS_GPIO_DRV_SLOW	0x1
+
+#define EXYNOS5_GPIO_BASE0	0x11400000
+#define EXYNOS5_GPIO_BASE1	0x13400000
+#define EXYNOS5_GPIO_BASE2	0x10d10000
+#define EXYNOS5_GPIO_BASE3	0x03860000
+
+enum exynos5_gpio_port {
+	/*
+	 * Ordered by base address + offset.
+	 * ETC registers are special, thus not included.
+	 */
+
+	/* base == EXYNOS_GPIO_BASE0 */
+	EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000,
+	EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020,
+	EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040,
+
+	EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060,
+	EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080,
+	EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0,
+	EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0,
+
+	EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0,
+	EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100,
+	EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120,
+	EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140,
+
+	EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160,
+	EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180,
+
+	EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0,
+	EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0,
+	EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0,
+	EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200,
+	EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220,
+	EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240,
+	EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260,
+
+	EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00,
+	EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20,
+	EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40,
+	EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60,
+
+	/* base == EXYNOS_GPIO_BASE1 */
+	EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000,
+	EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020,
+
+	EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040,
+	EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060,
+
+	EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080,
+	EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0,
+	EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0,
+
+	EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0,
+	EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100,
+
+	/* base == EXYNOS_GPIO_BASE2 */
+	EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000,
+	EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020,
+	EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060,
+	EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080,
+	EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0,
+
+	/* base == EXYNOS_GPIO_BASE3 */
+	EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000,
+};
+
 #endif