[coreboot] New patch to review for coreboot: 26e77e4 haswell: notes and updates.
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Mon Mar 11 22:39:40 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2631
-gerrit
commit 26e77e4526fa419129db60e2536abe852b6bd172
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Nov 29 17:21:51 2012 -0600
haswell: notes and updates.
Add a FIXME about checking a MCHBAR register that isn't setup yet.
Also, remove revision updating because I can't find anything in the
docs that suggest this is required for haswell.
Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/intel/graysreef/romstage.c | 4 ++++
src/northbridge/intel/haswell/early_init.c | 15 ---------------
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c
index 9fc5dd6..1fb45d8 100644
--- a/src/mainboard/intel/graysreef/romstage.c
+++ b/src/mainboard/intel/graysreef/romstage.c
@@ -193,6 +193,10 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
+ /*
+ * FIXME: MCHBAR isn't setup yet. It's setup in
+ * haswell_early_initialization().
+ */
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 4d17474..505fbf1 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -139,21 +139,6 @@ static void haswell_setup_graphics(void)
void haswell_early_initialization(int chipset_type)
{
- u32 capid0_a;
- u8 reg8;
-
- /* Device ID Override Enable should be done very early */
- capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
- if (capid0_a & (1 << 10)) {
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
- reg8 &= ~7; /* Clear 2:0 */
-
- if (chipset_type == HASWELL_MOBILE)
- reg8 |= 1; /* Set bit 0 */
-
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
- }
-
/* Setup all BARs required for early PCIe and raminit */
haswell_setup_bars();
More information about the coreboot
mailing list