[coreboot] New patch to review for coreboot: db83cd5 lynxpoint: Add Kconfig entry for Low Power chipset

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2645

-gerrit

commit db83cd507a0a21ed7d142b0a05234d1c2b981a85
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Dec 17 11:11:26 2012 -0800

    lynxpoint: Add Kconfig entry for Low Power chipset
    
    There are enough subtle differences that it is useful to have
    a Kconfig entry to differentiate the ULT/LP chipet from the
    desktop/mobile versions.
    
    Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/lynxpoint/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index e1d0e35..6f5bfe2 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -32,6 +32,12 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
 
+config INTEL_LYNXPOINT_LP
+	bool
+	default n
+	help
+	  Set this option to y for Lynxpont LP (Haswell ULT).
+
 config EHCI_BAR
 	hex
 	default 0xfef00000