[coreboot] New patch to review for coreboot: e0ba95f haswell: move call site of save_mrc_data()

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2756

-gerrit

commit e0ba95f5f99992cb6d80075c09844f629c921466
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Feb 7 00:51:18 2013 -0600

    haswell: move call site of save_mrc_data()
    
    The save_mrc_data() was previously called conditionally
    in the raminit code. The save_mrc_data() function was called
    in the non-S3 wake paths. However, the common romstage_common()
    code was checking cbmem initialization things on s3 wake. Between
    the two callers cbmem_initialize() was being called twice in the
    non-s3 wake paths.  Moreover, saving of the mrc data was not allowed
    when CONFIG_EARLY_CBMEM_INIT wasn't enabled.
    
    Therefore, move the save_mrc_data() to romstage_common. It already has
    the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT
    requirement from save_mrc_data() as well as the call to cbmem_initialize().
    
    Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/intel/haswell/romstage.c        | 4 ++++
 src/northbridge/intel/haswell/raminit.c | 9 +--------
 src/northbridge/intel/haswell/raminit.h | 2 ++
 3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 8b0e2cc..3ce04e2 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -230,6 +230,10 @@ void romstage_common(const struct romstage_params *params)
 						     - HIGH_MEMORY_SIZE));
 #endif
 
+	/* Save data returned from MRC on non-S3 resumes. */
+	if (boot_mode != 2)
+		save_mrc_data(params->pei_data);
+
 #if CONFIG_HAVE_ACPI_RESUME
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 8a38e76..1439200 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -38,14 +38,12 @@
 #define recovery_mode_enabled(x) 0
 #endif
 
-static void save_mrc_data(struct pei_data *pei_data)
+void save_mrc_data(struct pei_data *pei_data)
 {
-#if CONFIG_EARLY_CBMEM_INIT
 	struct mrc_data_container *mrcdata;
 	int output_len = ALIGN(pei_data->mrc_output_len, 16);
 
 	/* Save the MRC S3 restore data to cbmem */
-	cbmem_initialize();
 	mrcdata = cbmem_add
 		(CBMEM_ID_MRCDATA,
 		 output_len + sizeof(struct mrc_data_container));
@@ -66,7 +64,6 @@ static void save_mrc_data(struct pei_data *pei_data)
 
 	mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
 						    mrcdata->mrc_data_size);
-#endif
 }
 
 static void prepare_mrc_cache(struct pei_data *pei_data)
@@ -204,10 +201,6 @@ void sdram_initialize(struct pei_data *pei_data)
 		(version >> 8) & 0xff, version & 0xff);
 
 	report_memory_config();
-
-	/* S3 resume: don't save scrambler seed or MRC data */
-	if (pei_data->boot_mode != 2)
-		save_mrc_data(pei_data);
 }
 
 struct cbmem_entry *get_cbmem_toc(void)
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index f94dea8..46be570 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -25,5 +25,7 @@
 void sdram_initialize(struct pei_data *pei_data);
 unsigned long get_top_of_ram(void);
 int fixup_haswell_errata(void);
+/* save_mrc_data() must be called after cbmem has been initialized. */
+void save_mrc_data(struct pei_data *pei_data);
 
 #endif				/* RAMINIT_H */