[coreboot] Patch merged into coreboot/master: 7af2069 haswell: enable caching before SMM initialization

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 7af20698f69bbf10c4f18aa4fcc35ae7cf8cb866
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Jan 14 14:54:41 2013 -0600

    haswell: enable caching before SMM initialization
    
    The SMM handler resides in the TSEG region which is far above
    CONFIG_RAM_TOP (which is the highest cacheable address) before
    MTRRs are setup. This means that calling initialize_cpus() before
    performing MTRR setup on the BSP means the SMM handler is copied
    using uncacheable accesses.
    
    Improve the SMM handler setup path by enabling performing MTRR setup on
    for the BSP before the call to initialize_cpus(). In order to do this
    the haswell_init() function was split into 2 paths: BSP & AP paths.
    There is a cpu_common_init() that both call to perform similar
    functionality. The BSP path in haswell_init() then starts the APs using
    intel_cores_init(). The AP path in haswell_init() loads microcode and
    sets up MTRRs.
    
    This split will be leveraged for future support of bringing up APs in
    parallel as well as adhering to the Haswell MP initialization
    requirements.
    
    Change-Id: Id8e17af149e68d708f3d4765e38b1c61f7ebb470
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Fri Mar 15 23:13:28 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Mon Mar 18 17:10:17 2013, giving +2
See http://review.coreboot.org/2746 for details.

-gerrit