[coreboot] New patch to review for coreboot: c3c2432 lynxpoint: update MBP give up routine

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2808

-gerrit

commit c3c24326b1f2aa26ae3698ec724155e92de89aa6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Feb 25 10:51:52 2013 -0600

    lynxpoint: update MBP give up routine
    
    I'm not sure if I screwed this up originally or the Intel docs changed
    (I didn't bother to go back and check). According to ME BWG 1.1.0 the give
    up bit is in the host general status #2 register.
    
    Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/me.h     | 2 --
 src/southbridge/intel/lynxpoint/me_9.x.c | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index ecd12e4..a305822 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -201,8 +201,6 @@ struct me_hfs2 {
 #define PCI_ME_H_GS2		0x70
 #define   PCI_ME_MBP_GIVE_UP	0x01
 
-#define PCI_ME_H_GS3		0x74
-
 #define PCI_ME_HERES		0xbc
 #define  PCI_ME_EXT_SHA1	0x00
 #define  PCI_ME_EXT_SHA256	0x02
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 63b5205..2e790fc 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -804,7 +804,7 @@ static void intel_me_mbp_give_up(device_t dev)
 	struct mei_csr csr;
 
 	reg32 = PCI_ME_MBP_GIVE_UP;
-	pci_write_config32(dev, PCI_ME_H_GS3, reg32);
+	pci_write_config32(dev, PCI_ME_H_GS2, reg32);
 	read_host_csr(&csr);
 	csr.reset = 1;
 	csr.interrupt_generate = 1;