[coreboot] Tyan s2912-E reset loop, Please help

[Marc Jones]

On Tue, Sep 10, 2013 at 9:07 PM, Mark Mc <markymcd13 at gmail.com> wrote:
> Thank you Kyösti, there was no need to change MAX_CPUS as I had selected
> S2912 Fam10 (Thunder n3600R) so it is already set to 12 CPUS, I did change
> what else you told me to so that I could get more output to the serial
> console. I think I am getting closer to identifying the problem which is
> that the MCP55 (Southbridge) needs a warm reset to continue after POST: 0x3a
> however in this case it cannot I am currently studying the
> /src/mainboard/tyan/s2912_fam10/romstage.c to try and identify what is going
> wrong any suggestions are appreciated.
>
> My coreboot log now looks like this:
> -----------------------------------------------------------------------------------------------------------------------------------------
>
> coreboot-4.0-4671-g25dd247 Mon Sep  9 23:54:49 BST 2013 starting...
> BSP Family_Model: 00100f80
> *sysinfo range: [000c4000,000c5fa0]
> bsp_apicid = 00
> cpu_init_detectedx = 00000000
> microcode: rev id not found. Skipping microcode patch!
> POST: 0x33
> cpuSetAMDMSR  done
> POST: 0x34
> Enter amd_ht_init()
> AMD_CB_ManualBUIDSwapList()
> AMD_CB_EventNotify()
>  event class: 05
>  event: 2006
>  data:  04  00  02  ff
> Exit amd_ht_init()
> POST: 0x35
> cpuSetAMDPCI 00 done
> Prep FID/VID Node:00
>   F3x80: e600e681
>   F3x84: 80e641e6
>   F3xD4: c3310f27
>   F3xD8: 03000215
>   F3xDC: 00006428
> POST: 0x36
> core0 started:
> start_other_cores()
> init node: 00  cores: 05
> Start other core - nodeid: 00  cores: 05
> POST: 0x37
> started ap apicid: * AP 01started
> * AP 02started
> * AP 03started
> * AP 04started
> * AP 05started
>
> POST: 0x38
>
> Begin FIDVID MSR 0xc0010071 0x38a400c4 0x38044c40
> POST: 0x39
> FIDVID on BSP, APIC_id: 00
> BSP fid = 0
> Wait for AP stage 1: ap_apicid = 1
>     readback = 1000001
>     common_fid(packed) = 0
> Wait for AP stage 1: ap_apicid = 2
>     readback = 2000001
>     common_fid(packed) = 0
> Wait for AP stage 1: ap_apicid = 3
>     readback = 3000001
>     common_fid(packed) = 0
> Wait for AP stage 1: ap_apicid = 4
>     readback = 4000001
>     common_fid(packed) = 0
> Wait for AP stage 1: ap_apicid = 5
>     readback = 5000001
>     common_fid(packed) = 0
> common_fid = 0
> POST: 0x3a
> End FIDVIDMSR 0xc0010071 0x38a400c4 0x38044c40
> mcp55_num:01
> POST: 0x30
>
>
>
> INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---
>
> Issuing SOFT_RESET...
> ---------------------------------------------------------------------------------------------------------------------------------------------
> Cheers
> Mark
>

After the soft reset, it should got through romstage again, but skip
the clock init (fid/vid) and then do the memory init. It might have a
problem with detecting the warm reset.

Marc




>
>
> On Tue, Sep 10, 2013 at 4:54 AM, Kyösti Mälkki <kyosti.malkki at gmail.com>
> wrote:
>>
>> On Tue, 2013-09-10 at 02:01 +0100, Mark Mc wrote:
>> > Hi, I finally got coreboot compiled correctly and I am getting
>> > somewhere as my console output shows:
>> >
>> > coreboot-4.0-4671-g25dd247 Mon Sep  9 23:54:49 BST 2013 starting...
>> > BSP Family_Model: 00100f80
>> > *sysinfo range: [000c4000,000c5fa0]
>> > bsp_apicid = 00
>> > cpu_init_detectedx = 00000000
>> > microcode: rev id not found. Skipping microcode patch!
>> > POST: 0x33
>> > cpuSetAMDMSR  done
>> > POST: 0x34
>> > Enter amd_ht_init()
>> > AMD_CB_ManualBUIDSwapList()
>> > AMD_CB_EventNotify()
>> >  event class: 05
>> >  event: 2006
>> >  data:  04  00  02  ff
>> > Exit amd_ht_init()
>> > POST: 0x35
>> > cpuSetAMDPCI 00 done
>> > Prep FID/VID Node:00
>> >   F3x80: e600e681
>> >   F3x84: 80e641e6
>> >   F3xD4: c3310f27
>> >   F3xD8: 03000215
>> >   F3xDC: 00006428
>> > POST: 0x36
>> > core0 started:
>> > start_other_cores()
>> > init node: 00  cores: 05
>> > Start other core - nodeid: 00  cores: 05
>> > POST: 0x37
>> > started ap apicid: * AP 01started
>> > * AP 02started
>> > * AP 03started
>> > * AP 04started
>> > * AP 05started
>> >
>>
>> > INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---
>> > Issuing SOFT_RESET...
>> >
>> >
>> > However it just keeps looping like this, any guidance would be really
>> > appreciated, so far I have tried booting with just 1 dimm (4GB),1 CPU
>> > (opteron 2419) and no PCI-E cards, both stable and master seabios
>> > payloads but so far absolutely no difference.
>>
>>
>> First increase MAX_CPUS in src/mainboard/tyan/2912/Kconfig from 4 to 12.
>>
>> If that alone does not work, try change SERIAL_CPU_INIT=yes in same
>> file. Additionally in menuconfig under consoles, try with
>> SQUELCH_EARLY_SMP=no.
>>
>> Last two changes should not be required, just something to try as they
>> will slow down the boot sequence and give more output on serial console.
>>
>> Remember that after modifying any Kconfig file, you need a clean build:
>>   make clean && make oldconfig && make
>>
>>
>> Regards,
>>   Kyösti
>>
>
>
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