[coreboot] Trouble with coreboot for Roda RK9 (SOLVED)

[Nico Huber]

Am 14.02.2014 14:23, schrieb Vladimir 'φ-coder/phcoder' Serbinenko:
> On 14.02.2014 13:38, Dmitry Bagryanskiy wrote:
>> //Enable Com3
>> pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c02e1);
>> //Enable Com4
>> pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x001c03e1);
> GEN*_DEC should not be set to com* ports. Instead there are dedicated
> bits for enabling decode of serial port ranges. Consult southbridge
> documentation.
There are only dedicated settings for two COM ports. Looks like Dmitry
wants to enable a 3rd and 4th port.

Nico

-- 
M. Sc. Nico Huber
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