[coreboot] C720 swapparoo

[Aaron Durbin]

On Wed, Jan 29, 2014 at 4:44 PM, John Lewis <jlewis at johnlewis.ie> wrote:
> On 29/01/14 22:27, Aaron Durbin wrote:
>>
>> On Wed, Jan 29, 2014 at 4:25 PM, Aaron Durbin <adurbin at google.com> wrote:
>>>
>>> On Wed, Jan 29, 2014 at 4:16 PM, John Lewis <jlewis at johnlewis.ie> wrote:
>>>>
>>>> On 29/01/14 22:03, Aaron Durbin wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> This is where we reach the crux of the matter - In the stock/shellball
>>>>>> firmware, extracting BOOT_STUB doesn't yield a file which cbfstool in
>>>>>> upstream coreboot or CrOS coreboot can decipher. Looking at the file
>>>>>> in
>>>>>> hexedit it appears to be almost identical to a CBFS that is
>>>>>> recognised,
>>>>>> but
>>>>>> that's it. I have managed to extract the SVGA binary from the CBFS in
>>>>>> the
>>>>>> RW_LEGACY slot, and I've made an educated guess as to where the
>>>>>> system-agent
>>>>>> begins and ends in the unrecognised CBFS (section beginning "LARCHIVE
>>>>>> mrc.bin" or similar with the binary itself following, surrounded by
>>>>>> FF's)
>>>>>> copying and pasting it to a file. I would like to know if I am correct
>>>>>> in
>>>>>> my
>>>>>> assumptions about extracting that file manually and what size it
>>>>>> should
>>>>>> be,
>>>>>> in bytes?
>>>>>>
>>>>>
>>>>> That's interesting. It is just a regular 'ol cbfs. The images that
>>>>> shipped with your device is an 8MiB SPI. First 2MiB Duncan covered.
>>>>> The next 5 have nothing to do w/ coreboot proper -- all the extra
>>>>> vboot firmware bits. The last 1MiB is the cbfs.
>>>>>
>>>>
>>>> Okay, well I extracted the attached file using:
>>>>
>>>> eval `./fmap_decode bios.bin | grep BOOT_STUB`
>>>> dd if=c720.rom ibs=$((area_offset)) skip=1 | dd bs=$((area_size))
>>>> iflag=fullblock of=c720-coreboot.bin
>>>>
>>>> and:
>>>>
>>>> ../coreboot/build/cbfstool c720-coreboot.bin print
>>>>
>>>> produces:
>>>>
>>>> c720-coreboot.bin:
>>>> 1024 kB, bootblocksize 3144, romsize 8388608, offset 0x700000
>>>> alignment: 64 bytes
>>>>
>>>> Name                           Offset     Type         Size
>>>>
>>>> zippo.
>>>>
>>>
>>> Try cherry-picking this one:
>>> https://chrome-internal-review.googlesource.com/153037
>>
>>
>> Ugh. If only my copy/past worked. Try this one instead:
>> http://review.coreboot.org/#/c/4771/
>>
>
> Okay. I ran:
>
> git fetch http://review.coreboot.org/coreboot refs/changes/71/4771/1 && git
> checkout FETCH_HEAD
>
> then ran make, which updated the binary, but still no change in reading the
> file.
>
> I also compiled and ran the cbfstool in ./util in case that was somehow
> different, but same result.

I did this w/ the ChromeOS coreboot:

$ dd if=/dev/zero of=spi.bin bs=1M count=7
$ cat spi.bin c720-coreboot.bin > c720-coreboot-8MiB.bin
$ cbfstool c720-coreboot-8MiB.bin  print
c720-coreboot-8MiB.bin: 8192 kB, bootblocksize 3144, romsize 8388608,
offset 0x700000
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
cmos_layout.bin                0x700000   cmos_layout  1164
pci8086,0406.rom               0x7004c0   optionrom    65536
cpu_microcode_blob.bin         0x710500   microcode    41024
config                         0x71a5c0   raw          5541
fallback/vboot                 0x71bbc0   stage        15081
(empty)                        0x71f700   null         2136
fallback/romstage              0x71ff80   stage        42497
fallback/coreboot_ram          0x72a600   stage        91421
fallback/payload               0x740b80   payload      54921
u-boot.dtb                     0x74e280   (unknown)    7923
(empty)                        0x7501c0   null         327128
mrc.bin                        0x79ffc0   (unknown)    190180
(empty)                        0x7ce700   null         120984
spd.bin                        0x7ebfc0   (unknown)    1792
(empty)                        0x7ec700   null         76888

The file you use with cbfstool needs to match the header rom size. In
this case it is 8MiB.

Hope that helps.

-Aaron