[coreboot] Acer Chromebook 15 debug

John Lewis jlewis at johnlewis.ie
Sun Aug 30 18:43:58 CET 2015


Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the 
Broadwell Chromebooks, so I'm trying to build a working ROM with 
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B 
to give him a hand. Luckily USB debug works with this, so here is what 
I'm getting. What could I do next?

Incidentally, if I flash back my backup, it goes into recovery mode now 
every time I boot (flags are 0x489), I've tried pulling the battery to 
no avail. If anyone has a trick to get around that, I'd appreciate it, 
as the Acer is my main machine.

-⁠John.

coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015 
starting...

PM1_STS:   8910

PM1_EN:    0000

PM1_CNT:   00000000

TCO_STS:   0000 0000

GPE0_STS:  1ef82df0 187d4fdf 0005f240 00000000

GPE0_EN:   00000000 00000000 00000000 00000000

GEN_PMCON: 0200 2024 520b

Previous Sleep State: S5

CPU: Intel(R) Core(TM) i3-⁠5005U CPU @ 2.00GHz

CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001d

CPU: AES supported, TXT NOT supported, VT supported

MCH: device id 1604 (rev 09) is Broadwell F0

PCH: device id 9cc5 (rev 03) is Broadwell U Base

IGD: device id 1616 (rev 09) is Broadwell U GT2

CPU: frequency set to 2000 MHz

SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)

SPD: module type is DDR3

SPD: module part is HMT425S6AFR6A-⁠PB

SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb

SPD: device width 16 bits, bus width 64 bits

SPD: module size is 2048 MB (per channel)

Boot Count incremented to 8

ME: FW Partition Table      : OK

ME: Bringup Loader Failure  : NO

ME: Firmware Init Complete  : NO

ME: Manufacturing Mode      : NO

ME: Boot Options Present    : NO

ME: Update In Progress      : NO

ME: Current Working State   : Normal

ME: Current Operation State : Bring up

ME: Current Operation Mode  : Normal

ME: Error Code              : No Error

ME: Progress Phase          : BUP Phase

ME: Power Management Event  : Pseudo-⁠global reset

ME: Progress Phase State    : Waiting for DID BIOS message

ME: HSIO Version            : 8705 (CRC 0xfbc2)

No FMAP found at ffe10000.

FMAP: area RW_MRC_CACHE not found

No MRC cache found.

Starting Memory Reference Code

Initializing Policy

Installing common PPI

MRC: Starting...

Initializing Memory

MRC: Done.

MRC Version 2.6.0 Build 0

memcfg DDR3 clock 1600 MHz

memcfg channel assignment: A: 0, B  1, C  2

memcfg channel[0] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

memcfg channel[1] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

CBMEM: root @ 7cfff000 254 entries.

MRC data at ff7d0d9c 6246 bytes

Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)

create cbmem for dimm information



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