[coreboot] AGESA PI for Olivehill+
Wim Vervoorn
wvervoorn at eltan.com
Thu May 7 15:37:59 CEST 2015
Hello Wolfgang,
It is correct that you can't use this right away but the memory
configurations can be made. We have done this for several FT3B SoC based
boards.
We can do this for your board as well. Please contact me off-line if you
are interested.
Best Regards,
Wim Vervoorn
Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands
T : +31-(0)73-594 46 64
E : wvervoorn at eltan.com
W : http://www.eltan.com
"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE
INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY
PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE
IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY
EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."
From: coreboot [mailto:coreboot-bounces at coreboot.org] On Behalf Of
Wolfgang Kamp - datakamp
Sent: Thursday, May 07, 2015 3:19 PM
To: coreboot at coreboot.org
Subject: [coreboot] AGESA PI for Olivehill+
Hi Bruce,
is it right that the AGESA Pi binary for AMD Olivehill+ board is not
usable for custom board implementations of FT3B GSOC?
For example, if we use memory down design in star topology, AGESA will
fail to initialize DDR3.
Regards,
Wolfgang
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150507/f0d80d4b/attachment.html>
More information about the coreboot
mailing list