[coreboot] PC Engines APU2 support

[Piotr Król]

Hi all,
I'm working on support for PC Engines APU2 (AMD GX-412TC) board and I
finally manage to boot Voyage Linux and run memtest86+. There some
limitations and concerns that I have and hope you can advise how to
proceed.

1. Platform doesn't show anything on UART after power off. It works fine
when going through reset after flashing new firmware. It seems to do
something because LEDs light up. Any idea what can be wrong or how to
approach that ?

2. Platform boots only with AGESA <= 1.0.0.3. With newer version (>=
1.0.0.4) it hangs right after passing control to Linux (GRUB seems to
work fine). Binary from master (1.0.0.A) reboots in the same place when
it pass control or start testing memory. Anyone saw similar behavior ?
If yes what is the approach to debug that ? Or maybe there known fixes
for that ?

3. APU2 got only UART interface and to make it accept input character I
had to port some changes from out of tree SeaBIOS. I managed to merge it
with upstream version and it seems to work for APU2. Some of those
changes are very specific to APU2. Code is here:
https://github.com/pcengines/seabios/commits/apu2-support

At this point, for testers (if any), I changed Makefiles to point to
gihub repo, but wonder if pushing those changes make sense before
merging APU2 support ?

4. I also had to modify memtest86plus because it hanged on code looking
for SPD. This platform do not use memory modules, just chips soldered on
board. At this point there is SPD_DISABLE define that disable SPD
reading. I'm not sure if this is correct approach and if this should be
pushed for review before proving it work ?
https://github.com/pcengines/memtest86plus/commits/apu2

My changes to coreboot are under review here:
https://review.coreboot.org/#/c/14138/

Any help appreciated.

-- 
Best Regards,
Piotr Król
Embedded Systems Consultant
http://3mdeb.com | @3mdeb_com