[coreboot] Discussion about dynamic PCI MMIO size on x86

[Nico Huber]

On 06.06.2016 23:40, Kyösti Mälkki wrote:
> On Mon, Jun 6, 2016 at 10:36 PM, ron minnich <rminnich at gmail.com> wrote:
>> I'm getting the sense here that reasonably modern CPUs can easily handle the
>> 2G hole. From what I've seen, it would not cause trouble for older CPUs
>> because they're most likely to be in small systems that are not likely to
>> have more than 2G memory anyway (I'm thinking of the vortex).
>>
> 
> Not that I would particularly care, but was i945 able to reclaim
> memory from below 4GiB to above 4GiB? There used to be a fair amount
> of Lenovo T60/X60(s) users.
I don't think we should use the 2GiB limit for all x86 platforms. It's
more a question for those platforms that are actively maintained and
at least support PAE, IMO.

Regarding i945, I had a look at the code and there is a TOM register
that's programmed to the total amount of DRAM. But sadly it's undocu-
mented (at my level of NDA) and coreboot doesn't seem to advertise
memory above 4GiB (I haven't tried it yet though).

Nico