[coreboot] Rowhammer DRAM Refresh

[Philipp Stanner]

K, thank you so far! I hoped there was an easier solution like a #define 
in a header somewhere.

However it's the code I've gone through so far is already interesting as 
coreboot often seems to use a refresh rate of ~16ms what's 4x of the 
rate some vendors use.

// P.


On 20.03.2017 13:34, Arthur Heymans wrote:
> Philipp Stanner <stanner at posteo.de> writes:
>
>> Hi,
>>
>> where (which code file) does coreboot set the DRAM-refresh-rate and
>> how easy is it for me to change it?
> That would be in raminit, which is platform specific. So it depends on
> readability of that code whether it's easy to find or not.
>
> Not sure of this is possible with raminits like FSP or MRC.bin provided
> in binary only.
>
>> A higher refresh rate will decrease the performance but increase the
>> protection against Rowhammer.
>>
>> // Philipp
>
> Some example of how to achieve this on Intel 945 northbridge:
>
> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
> index b5cce9c429..36dd601fb2 100644
> --- a/src/northbridge/intel/i945/raminit.c
> +++ b/src/northbridge/intel/i945/raminit.c
> @@ -811,32 +811,8 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
>   {
>   	int i;
>   
> -	sysinfo->refresh = 0;
> +	sysinfo->refresh = 1;
>   
> -	for (i = 0; i < 2*DIMM_SOCKETS; i++) {
> -		int refresh;
> -
> -		if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
> -			continue;
> -
> -		refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i),
> -					SPD_REFRESH) & ~(1 << 7);
> -
> -		/* 15.6us */
> -		if (!refresh)
> -			continue;
> -
> -		/* Refresh is slower than 15.6us, use 15.6us */
> -		if (refresh > 2)
> -			continue;
> -
> -		if (refresh == 2) {
> -			sysinfo->refresh = 1;
> -			break;
> -		}
> -
> -		die("DDR-II module has unsupported refresh value\n");
> -	}
>   	printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
>   }
>   
>   
>