/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/variants.h>
#include <soc/gpio.h>


/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {

	/* GPP_A */
	/* GPP_A00: 	ESPI_IO0_AIC */
	/*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
	/* GPP_A01: 	ESPI_IO1_AIC */
	/*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
	/* GPP_A02: 	ESPI_IO2_AIC */
	/*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
	/* GPP_A03: 	ESPI_IO3_AIC */
	/*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
	/* GPP_A04: 	ESPI_CS0_AIC_N */
	/*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
	/* GPP_A05: 	ESPI_CLK_AIC */
	/*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
	/* GPP_A06: 	ESPI_RST_AIC_N */
	/*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
	/* GPP_A07: 	SECURE_CAM_SW_R */
	PAD_CFG_GPI_TRIG_OWN(GPP_A07, NONE, PLTRST, LEVEL, ACPI),
	/* GPP_A08: 	X1_PCIE_SLOT_PWR_EN */
	PAD_CFG_GPO(GPP_A08, 1, DEEP),
	/* GPP_A09: 	M.2_WWAN_FCP_OFF_N */
	PAD_CFG_GPO(GPP_A09, 1, PLTRST),
	/* GPP_A10: 	WLAN_RST_N */
	PAD_CFG_GPO(GPP_A10, 1, PLTRST),
	/* GPP_A11: 	SOC_M2_GEN4_SSD3_RESET_N */
	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
	/* GPP_A13: 	PM_SLP_S0_N_GPP_CNTRL */
	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
	/* GPP_A14: 	ESPI_ALERT3_AIC_N */
	PAD_NC(GPP_A14, NONE),
	/* GPP_A15: 	BT_RF_KILL_N */
	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
	/* GPP_A16: 	Not used */
	PAD_NC(GPP_A16, NONE),
	/* GPP_A17: 	ESPI_CS3_AIC_N */
	PAD_NC(GPP_A17, NONE),

	/* GPP_B */
	/* GPP_B00: 	MOD_TCSS0_PD_PMC_SCL */
	PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
	/* GPP_B01: 	MOD_TCSS0_PD_PMC_SDA */
	PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
	/* GPP_B02: 	ISH_I3C0_SDA_SNSR_HDR_R */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF1),
	/* GPP_B03: 	ISH_I3C0_SCL_SNSR_HDR_R */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF1),
	/* GPP_B04: 	ISH_GP_0_SNSR_HDR */
	PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
	/* GPP_B05: 	ISH_GP_1_SNSR_HDR */
	PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
	/* GPP_B06: 	ISH_GP_2_SNSR_HDR */
	PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
	/* GPP_B07: 	ISH_GP_3_SNSR_HDR */
	PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
	/* GPP_B08: 	ISH_GP_4_SNSR_HDR */
	PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
	/* GPP_B09: FPS_RST_N; not used */
	PAD_NC(GPP_B09, NONE),
	/* GPP_B10: 	SOC_M2_GEN4_SSD3_PWREN */
	PAD_CFG_GPO(GPP_B10, 1, DEEP),
	/* GPP_B11: 	SOC_PDB_CTRL */
	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
	/* GPP_B12: 	PM_SLP_S0_N */
	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
	/* GPP_B13: 	PLT_RST_N */
	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
	/* GPP_B14: 	DDSP_HDMI_HPD4 */
	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
	/* GPP_B15: 	MOD_TCSS_USB_TYP_A_OC3_N */
	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
	/* GPP_B17: 	MOD_TCSS0_EDP_VDD_EN */
	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
	/* GPP_B18: 	ISH_I2C2_SDA_SNSR_HDR */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
	/* GPP_B19: 	ISH_I2C2_SCL_SNSR_HDR */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
	/* GPP_B20: 	M.2_WWAN_RST_N */
	PAD_CFG_GPO(GPP_B20, 1, PLTRST),
	/* GPP_B21: 	TCP_RETIMER_FORCE_PWR */
	PAD_CFG_GPO(GPP_B21, 0, DEEP),
	/* GPP_B22: 	ISH_GP_5_SNSR_HDR */
	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
	/* GPP_B23: 	ISH_GP_6_SNSR_HDR */
	PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
	/* GPP_B24: 	ESPI_ALERT0_AIC_N */
	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),
	/* GPP_B25: 	UFS_RST_N */
	PAD_CFG_GPO(GPP_B25, 1, PLTRST),

	/* GPP_C */
	/* GPP_C03: 	TCP_LAN_SML0_SCL_R */
	PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
	/* GPP_C04: 	TCP_LAN_SML0_SDA_R */
	PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
	/* GPP_C05: 	CRD1_PWREN */
	PAD_CFG_GPO(GPP_C05, 0, DEEP),
	/* GPP_C06: 	WIFI_WAKE_N */
	PAD_CFG_GPI_SCI_LOW(GPP_C06, NONE, DEEP, LEVEL),
	/* GPP_C07: 	X1_SLOT_WAKE_N */
	PAD_CFG_GPI_SCI_LOW(GPP_C07, NONE, DEEP, LEVEL),
	/* GPP_C08: 	CRD2_PWREN */
	PAD_CFG_GPO(GPP_C08, 0, DEEP),
	/* GPP_C09: 	SOC_CLKREQ0_GEN5_SSD2_N */
	PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
	/* GPP_C10: 	CLKREQ1_X1_GEN4_DT_CEM_SLOT_N */
	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
	/* GPP_C11: 	CLKREQ2_X1_GEN4_M2_WLAN_N */
	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
	/* GPP_C12: 	CLKREQ3_X1_GEN4_M2_WWAN_N */
	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
	/* GPP_C13: 	CLKREQ4_X4_GEN4_M2_SSD3_N */
	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
	/* GPP_C14: 	CLKREQ5_X1_GEN1_GBE_LAN_N */
	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
	/* GPP_C15: 	SOC_PCIE_LNK_DOWN */
	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF3),
	/* GPP_C16: 	MOD_TCSS0_LS_TX_DDC_SCL */
	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
	/* GPP_C17: 	MOD_TCSS0_LS_RX_DDC_SDA */
	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
	/* GPP_C18: 	MOD_TCSS1_LS_TX_DDC_SCL */
	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
	/* GPP_C19: 	MOD_TCSS1_LS_RX_DDC_SDA */
	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
	/* GPP_C20: 	MOD_TCSS2_LS_TX_DDC_SCL */
	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
	/* GPP_C21: 	MOD_TCSS2_LS_RX_DDC_SDA */
	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
	/* GPP_C22: 	GPP_C22_DDP4_HDMI_CTRLCLK */
	PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
	/* GPP_C23: 	GPP_C23_DDP4_HDMI_CTRLDATA */
	PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),

	/* GPP_D */
	/* GPP_D00: 	IMGCLKOUT_1 */
	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
	/* GPP_D01: FPMCU_PWREN */
	PAD_CFG_GPO(GPP_D01, 1, DEEP),
	/* GPP_D02: SOC_WP_OD */
	PAD_CFG_GPI(GPP_D02, NONE, DEEP),
	/* GPP_D03: 	GPP_D3_PCH_IOE_MODE_EN */
	PAD_NC(GPP_D03, NONE),
	/* GPP_D04: 	IMGCLKOUT_0 */
	PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
	/* GPP_D05: 	ISH_SPI_CS_N_SNSR_HDR */
	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF1),
	/* GPP_D06: 	ISH_SPI_CLK_SNSR_HDR */
	PAD_CFG_NF(GPP_D06, NONE, DEEP, NF1),
	/* GPP_D07: 	ISH_SPI_MISO_SNSR_HDR */
	PAD_CFG_NF(GPP_D07, NONE, DEEP, NF1),
	/* GPP_D08: 	ISH_SPI_MOSI_SNSR_HDR */
	PAD_CFG_NF(GPP_D08, NONE, DEEP, NF1),
	/* GPP_D09: 	PEG_SLOT_RST_N */
	PAD_CFG_GPO(GPP_D09, 1, PLTRST),
	/* GPP_D10: 	HDA_BCLK_I2S0_SCLK_HDR */
	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
	/* GPP_D11: 	HDA_SYNC_I2S0_SFRM_HDR */
	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
	/* GPP_D12: 	HDA_SDO_I2S0_TXD_HDR */
	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
	/* GPP_D13: 	HDA_SDI0_I2S0_RXD_HDR */
	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
	/* GPP_D16: 	HDA_RST_N_HDR */
	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
	/* GPP_D17: 	HDA_SDI1_HDR */
	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
	/* GPP_D18: 	CLKREQ6_X8_GEN5_DT_CEM_SLOT_N */
	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
	/* GPP_D20: 	CLKREQ7_X4_GEN5_M2_SSD_N */
	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
	/* GPP_D21: 	GPP_D21_UFS_REFCLK */
	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
	/* GPP_D22: 	M.2_WWAN_DISABLE_N */
	PAD_CFG_GPO(GPP_D22, 1, PLTRST),
	/* GPP_D23: 	WIFI_RF_KILL_N */
	PAD_CFG_GPO(GPP_D23, 1, DEEP),

	/* GPP_E */
	/* GPP_E01: 	VDDQ_DVFSQ_SEL_N */
	PAD_CFG_NF(GPP_E01, NONE, DEEP, NF1),
	/* GPP_E02: 	PEG_SLOT_WAKE_N */
	PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
	/* GPP_E03: 	SOC_M2_GEN5_SSD2_RESET_N */
	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
	/* GPP_E04: 	SOC_M2_GEN5_SSD2_PWREN */
	PAD_CFG_GPO(GPP_E04, 1, DEEP),
	/* GPP_E05: 	M.2_WWAN_PERST_GPIO_N */
	PAD_CFG_GPO(GPP_E05, 1, PLTRST),
	/* GPP_E06: 	GPP_E6 */
	PAD_NC(GPP_E06, NONE),
	/* GPP_E07: 	SOC_M2_GEN5_SSD1_PWREN */
	PAD_CFG_GPO(GPP_E07, 1, DEEP),
	/* GPP_E08: 	M2_GEN5_SSD_RESET_N */
	PAD_CFG_GPO(GPP_E08, 1, PLTRST),
	/* GPP_E09: 	USB32_TYPEA_CONN1_OC0_N */
	PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
	/* GPP_E10: 	CRD1_RST_N */
	PAD_CFG_GPO(GPP_E10, 1, PLTRST),
	/* GPP_E11: 	THC0_SPI_CLK_GSPI_CLK_R */
	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
	/* GPP_E12: 	THC0_I2C_SCL_TCH_PNL */
	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
	/* GPP_E13: 	THC0_I2C_SDA_TCH_PNL */
	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
	/* GPP_E14: 	THC0_SPI_IO_2_TCH_PNL_R */
	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
	/* GPP_E15: 	THC0_SPI_IO_3_TCH_PNL_R */
	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
	/* GPP_E16: 	THC0_SPI_RST_N_TCH_PNL1 */
	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF3),
	/* GPP_E17: 	THC0_SPI_CS0_N_TCH_PNL1 */
	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
	/* GPP_E18: 	THC0_SPI_INT_N_TCH_PNL1 */
	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
	/* GPP_E19: 	CODEC_GPIO_EN */
	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
	/* GPP_E20: 	FPMCU_FW_UPDATE */
	PAD_CFG_GPI(GPP_E20, NONE, PLTRST),
	/* GPP_E21: 	I2C_PMC_PD_INT_N */
	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
	/* GPP_E22: 	TCH_PNL1_PWR_EN */
	PAD_CFG_GPO(GPP_E22, 1, DEEP),

	/* GPP_F */
	/* GPP_F00: 	M.2_CNV_BRI_DT_BT_UART2_RTS_N */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
	/* GPP_F01: 	M.2_CNV_BRI_RSP_BT_UART2_RXD */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
	/* GPP_F02: 	M.2_CNV_RGI_DT_BT_UART2_TXD */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
	/* GPP_F03: 	M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
	/* GPP_F04: 	CNV_RF_RESET_R_N */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
	/* GPP_F05: 	CRF_CLKREQ_R */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
	/* GPP_F07: 	IMGCLKOUT_2 */
	PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
	/* GPP_F08: 	ISH_GP_7A_SNSR_HDR_R */
	PAD_CFG_NF(GPP_F08, NONE, DEEP, NF8),
	/* GPP_F09: 	ISH_INT_GP11_CVS */
	PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4),
	/* GPP_F11: 	CRD2_RST_N */
	PAD_CFG_GPO(GPP_F11, 1, PLTRST),
	/* GPP_F12: 	THC_I2C1_SCL_TCH_PAD */
	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
	/* GPP_F13: 	THC_I2C1_SDA_TCH_PAD */
	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
	/* GPP_F14: EC_SOC_INT_ODL */
	PAD_CFG_GPI_APIC_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
	/* GPP_F15: 	WWAN_WAKE_GPIO_N */
	PAD_CFG_GPI_SCI_LOW(GPP_F15, NONE, DEEP, LEVEL),
	/* GPP_F16:     SPI_TPM_INT_N */
	PAD_CFG_GPI_APIC_LOCK(GPP_F16, NONE, LEVEL, INVERT, LOCK_CONFIG),
	/* GPP_F17: 	CODEC_INT_N */
	PAD_CFG_GPI_SCI_LOW(GPP_F17, NONE, DEEP, LEVEL),
	/* GPP_F18: 	TCH_PAD_INT_N */
	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
	/* GPP_F19: 	GPP_PRIVACY_LED_CAM2 */
	PAD_CFG_GPO(GPP_F19, 0, PLTRST),
	/* GPP_F22: 	X1_DT_PCIE_RST_N */
	PAD_CFG_GPO(GPP_F22, 1, PLTRST),
	/* GPP_F23: 	SMC_LID_LS */
	PAD_CFG_GPI(GPP_F23, NONE, DEEP),

	/* GPP_H */
	/* GPP_H00: 	GPP_PRIVACY_LED_CAM1 */
	PAD_CFG_GPO(GPP_H00, 0, PLTRST),
	/* GPP_H01: 	CRD_CAM_STROBE */
	PAD_CFG_GPO(GPP_H01, 0, PLTRST),
	/* GPP_H02: 	DEBUG_TRACE_PNP */
	PAD_CFG_GPO(GPP_H02, 1, PLTRST),
	/* GPP_H03: 	Not used */
	PAD_NC(GPP_H03, NONE),
	/* GPP_H04: 	I2C2_SCL_I3C2_SDA_TTK */
	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
	/* GPP_H05: 	I2C2_SCL_I3C2_SCL_TTK */
	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
	/* GPP_H06: 	I2C3_SDA_PSS */
	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
	/* GPP_H07: 	I2C3_SCL_PSS */
	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
	/* GPP_H08: 	BUF_RXD */
	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
	/* GPP_H09: 	BUF_TXD */
	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
	/* GPP_H10: 	BUF_RTS_N */
	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
	/* GPP_H11: 	BUF_CTS_N */
	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
	/* GPP_H13: 	CPU_C10_GATE_N_R */
	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
	/* GPP_H14: 	ISH_I2C1_ISH_I3C1_SDA_SNSR_HDR */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF3),
	/* GPP_H15: 	ISH_I2C1_ISH_I3C1_SCL_SNSR_HDR */
	PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF3),
	/* GPP_H16: 	MIC_MUTE_R */
	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
	/* GPP_H17: 	MIC_MUTE_LED_R */
	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
	/* GPP_H19: 	I2C0_I3C0_SDA_CAM2_FLSH_CVS */
	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
	/* GPP_H20: 	I2C0_I3C0_SCL_CAM2_FLSH_CVS */
	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
	/* GPP_H21: 	I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
	/* GPP_H22: 	I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),

	/* GPP_S */
	/* GPP_S00: 	SNDW3_CLK_CODEC */
	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
	/* GPP_S01: 	SNDW3_DATA0_CODEC */
	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
	/* GPP_S02: 	SNDW3_DATA1_CODEC */
	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
	/* GPP_S03: 	SNDW3_DATA2_CODEC */
	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
	/* GPP_S04: 	GPP_S4_SNDW2_CLK_DMIC_CLK_A_0_R */
	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
	/* GPP_S05: 	DMIC0_DATA_SNDW2_DATA0_R */
	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
	/* GPP_S06: 	DMIC1_CLK_SNDW1_CLK_SNDW2_DATA1_R */
	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
	/* GPP_S07: 	DMIC1_DATA_SNDW1_DATA0_SNDW2_DATA2_R */
	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),

	/* GPP_V */
	/* GPP_V00: 	PM_BATLOW_N */
	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
	/* GPP_V01: 	BC_ACOK_MCP */
	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
	/* GPP_V02: 	GPP_V2_SOC_WAKE_N */
	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
	/* GPP_V03: 	PWRBTN_MCP_N */
	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
	/* GPP_V04: 	PM_SLP_S3_N */
	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
	/* GPP_V05: 	PM_SLP_S4_N */
	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
	/* GPP_V06: 	PM_SLP_A_N */
	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
	/* GPP_V07: 	NC */
	PAD_NC(GPP_V07, NONE),
	/* GPP_V08: 	UFS_RDV_RESET_N */
	PAD_CFG_GPO(GPP_V08, 1, PLTRST),
	/* GPP_V09: 	PM_SLP_S5_N */
	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
	/* GPP_V10: 	LANPHYPC_R_N */
	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
	/* GPP_V11: 	PM_SLP_LAN_N */
	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
	/* GPP_V12: 	WAKE_N */
	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
	/* GPP_V13: 	GPP_V13_CATERR_N */
	PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
	/* GPP_V14: 	GPP_V14_FORCEPR_N */
	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
	/* GPP_V15: 	GPP_V15_THERMTRIP_N */
	PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
	/* GPP_V16: 	CSE_EARLY_SW */
	PAD_NC(GPP_V16, NONE),
	/* GPP_V17: 	Not used */
	PAD_NC(GPP_V17, NONE),
};

/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
	/* GPP_H04:     SOC_I2C_GSC_SDA */
	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
	/* GPP_H05:     SOC_I2C_GSC_SCL */
	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
	/* GPP_H08:     UART0_BUF_RXD */
	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
	/* GPP_H09:     UART0_BUF_TXD */
	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
	/* GPP_H06: I2C3_SDA_PSS */
	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
	/* GPP_H07: I2C3_SCL_PSS */
	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
	/* GPP_F16: SPI_TPM_INT_N */
	PAD_CFG_GPI_APIC(GPP_F16, NONE, PLTRST, LEVEL, INVERT),
	/* GPP_B10:     SOC_M2_GEN4_SSD3_PWREN */
	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
	/* GPP_E04:     SOC_M2_GEN5_SSD2_PWREN */
	PAD_CFG_GPO(GPP_E04, 0, PLTRST),
	/* GPP_E07:     SOC_M2_GEN5_SSD1_PWREN */
	PAD_CFG_GPO(GPP_E07, 0, PLTRST),
};

/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
	/* GPP_C00:     GPP_C0_SMBCLK */
	PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
	/* GPP_C01:     GPP_C1_SMBDATA */
	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
};

const struct pad_config *variant_gpio_table(size_t *num)
{
	*num = ARRAY_SIZE(gpio_table);
	return gpio_table;
}

const struct pad_config *variant_early_gpio_table(size_t *num)
{
	*num = ARRAY_SIZE(early_gpio_table);
	return early_gpio_table;
}

/* Create the stub for romstage gpio, typically use for power sequence */
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
	*num = ARRAY_SIZE(romstage_gpio_table);
	return romstage_gpio_table;
}
