/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _COMMONLIB_MEMORY_INFO_H_
#define _COMMONLIB_MEMORY_INFO_H_

#include <stdint.h>

#define DIMM_INFO_SERIAL_SIZE		4
#define DIMM_INFO_PART_NUMBER_SIZE	33
#define DIMM_INFO_TOTAL			64

/**
 * If this table is filled and put in CBMEM,
 * then these info in CBMEM will be used to generate smbios type 17 table
 *
 * Values are specified according to the JEDEC SPD Standard.
 */
struct dimm_info {
	/*
	 * Size of the module in MiB.
	 */
	uint32_t dimm_size;
	/*
	 * SMBIOS (not SPD) device type.
	 *
	 * See the smbios.h smbios_memory_type enum.
	 */
	uint16_t ddr_type;
	/*
	 * ddr_frequency is deprecated.
	 * Use max_speed_mts and configured_speed_mts instead.
	 */
	uint16_t ddr_frequency;
	uint8_t rank_per_dimm;
	/*
	 * Socket-ID
	 */
	uint8_t soc_num;
	/*
	 * Memory-Controller-ID
	 */
	uint8_t ctrlr_num;
	/*
	 * Channel-ID
	 */
	uint8_t channel_num;
	/*
	 * DIMM-ID
	 */
	uint8_t dimm_num;
	uint8_t bank_locator;
	/*
	 * SPD serial number.
	 */
	uint8_t serial[DIMM_INFO_SERIAL_SIZE];
	/*
	 * The last byte is '\0' for the end of string
	 *
	 * Must contain only printable ASCII.
	 */
	uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
	/*
	 * SPD Manufacturer ID
	 */
	uint16_t mod_id;
	/*
	 * SPD Module Type.
	 *
	 * See spd.h for valid values.
	 *
	 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
	 */
	uint8_t mod_type;
	/*
	 * SMBIOS Type 17 Type Detail field:
	 *
	 * Bit 0 Reserved, set to 0
	 * Bit 1 Other
	 * Bit 2 Unknown
	 * Bit 3 Fast-paged
	 * Bit 4 Static column
	 * Bit 5 Pseudo-static
	 * Bit 6 RAMBUS
	 * Bit 7 Synchronous
	 * Bit 8 CMOS
	 * Bit 9 EDO
	 * Bit 10 Window DRAM
	 * Bit 11 Cache DRAM
	 * Bit 12 Non-volatile
	 * Bit 13 Registered (Buffered)
	 * Bit 14 Unbuffered (Unregistered)
	 * Bit 15 LRDIMM
	 */
	uint16_t type_detail;
	/*
	 * SPD bus width.
	 *
	 * Bits 0 - 2 encode the primary bus width:
	 *   0b000 = 8 bit width
	 *   0b001 = 16 bit width
	 *   0b010 = 32 bit width
	 *   0b011 = 64 bit width
	 *
	 * Bits 3 - 4 encode the extension bits (ECC):
	 *   0b00 = 0 extension bits
	 *   0b01 = 8 bit of ECC
	 *
	 * e.g.,
	 *   64 bit bus with 8 bits of ECC (72 bits total): 0b1011
	 *   64 bit bus with 0 bits of ECC (64 bits total): 0b0011
	 *
	 * See the smbios.h smbios_memory_bus_width enum.
	 */
	uint8_t bus_width;
	/*
	 * Voltage Level
	 */
	uint16_t vdd_voltage;
	uint16_t vdd_min_voltage;
	uint16_t vdd_max_voltage;
	/*
	 * Max speed in MT/s
	 * If the value is 0, ddr_frequency should be used instead.
	 */
	uint16_t max_speed_mts;
	/*
	 * Configured speed in MT/s
	 * If the value is 0, ddr_frequency should be used instead.
	 */
	uint16_t configured_speed_mts;
} __packed;

struct memory_info {
	/*
	 * SMBIOS error correction type.
	 * See the smbios.h smbios_memory_array_ecc enum.
	 */
	uint8_t ecc_type;
	/* Maximum capacity the DRAM controller/mainboard supports */
	uint32_t max_capacity_mib;
	/* Maximum number of DIMMs the DRAM controller/mainboard supports */
	uint16_t number_of_devices;

	/* active DIMM configuration */
	uint8_t dimm_cnt;
	struct dimm_info dimm[DIMM_INFO_TOTAL];
} __packed;

union bus_width_struct {
	uint8_t raw_data;
	struct {
		uint8_t primary_bus_width_per_subchan : 3; // Bits 0-2: Primary bus width per sub-channel
		uint8_t bus_width_ext_per_subchannel : 2; // Bits 3-4: Bus width Extension per sub-channel
		uint8_t number_of_subchannel_per_dimm : 3; // Bits 5-7: Number of sub-channels per dimm
	} bits;
} __packed;

#endif /* _COMMONLIB_MEMORY_INFO_H_ */
