/** @file

  Platform Configuration C Struct Header File.

  Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
  SPDX-License-Identifier: BSD-2-Clause-Patent

  This file is automatically generated. Please do NOT modify !!!

**/

#ifndef __FSPS_UPD_H__
#define __FSPS_UPD_H__

#include <FspUpd.h>

#pragma pack(1)

typedef struct {

/**  PCIe Controller 0
  Enable / Disable PCI Express controller 0
  $EN_DIS
**/
  UINT8                       EnablePcie0;

/**  PCIe Controller 1
  Enable / Disable PCI Express controller 1
  $EN_DIS
**/
  UINT8                       EnablePcie1;

/**  Embedded Multi-Media Controller (eMMC)
  Enable / Disable Embedded Multi-Media controller
  $EN_DIS
**/
  UINT8                       EnableEmmc;

/**  LAN Controllers
  Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
  0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
  UINT8                       EnableGbE;

/**  PCIe Root Port 0 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort0DeEmphasis;

/**  PCIe Root Port 1 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort1DeEmphasis;

/**  PCIe Root Port 2 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort2DeEmphasis;

/**  PCIe Root Port 3 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort3DeEmphasis;

/**  PCIe Root Port 4 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort4DeEmphasis;

/**  PCIe Root Port 5 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort5DeEmphasis;

/**  PCIe Root Port 6 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort6DeEmphasis;

/**  PCIe Root Port 7 DeEmphasis
  Desired DeEmphasis level for PCIE root port
  0:6dB, 1:3.5dB
**/
  UINT8                       PcieRootPort7DeEmphasis;

/**  PCIe Root Port 0 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort0Aspm;

/**  PCIe Root Port 1 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort1Aspm;

/**  PCIe Root Port 2 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort2Aspm;

/**  PCIe Root Port 3 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort3Aspm;

/**  PCIe Root Port 4 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort4Aspm;

/**  PCIe Root Port 5 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort5Aspm;

/**  PCIe Root Port 6 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort6Aspm;

/**  PCIe Root Port 7 ASPM Support
  This option can disable ASPM support in PCIe root port. 'Auto' keeps hardware default.
  0:Disable, 4:Auto
**/
  UINT8                       PcieRootPort7Aspm;

/**  PCIe Root Port 0 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort0CtoValue;

/**  PCIe Root Port 1 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort1CtoValue;

/**  PCIe Root Port 2 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort2CtoValue;

/**  PCIe Root Port 3 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort3CtoValue;

/**  PCIe Root Port 4 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort4CtoValue;

/**  PCIe Root Port 5 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort5CtoValue;

/**  PCIe Root Port 6 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort6CtoValue;

/**  PCIe Root Port 7 Completion Timeout Value
  Enable / disable the PCIe Completion Timeout in Device Control2 register
  0:50us to 50ms, 1:50us to 100us, 2:1ms to 10ms, 5:16ms to 55ms, 6:65ms to 210ms,
  9:260ms to 900ms, 10:1s to 3.5s, 15:Disable
**/
  UINT8                       PcieRootPort7CtoValue;

/**  PCIe Root Port 0 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort0SLOTHPSUP;

/**  PCIe Root Port 1 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort1SLOTHPSUP;

/**  PCIe Root Port 2 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort2SLOTHPSUP;

/**  PCIe Root Port 3 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort3SLOTHPSUP;

/**  PCIe Root Port 4 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort4SLOTHPSUP;

/**  PCIe Root Port 5 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort5SLOTHPSUP;

/**  PCIe Root Port 6 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort6SLOTHPSUP;

/**  PCIe Root Port 7 Surprise Hot Plug Capable
  This option specifies if the link is considered Surprise Hot Plug capable.
  0:Disable, 1:Enable
**/
  UINT8                       PcieRootPort7SLOTHPSUP;

/**  PCH Protect Range Limit
  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
  limit comparison.
**/
  UINT16                      PchProtectedRangeLimit[5];

/**  PCH Protect Range Base
  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
  UINT16                      PchProtectedRangeBase[5];

/**  PCH Protect Range Base
  Read is blocked by hardware. Each byte represents a ReadProtectionEnable for respective Ranges.
**/
  UINT8                       PchReadProtectionEnable[5];

/**  PCH Flash Protection Ranges Write Enable
  Write or erase is blocked by hardware. Each byte represents a WriteProtectionEnable
  for respective Ranges.
**/
  UINT8                       PchWriteProtectionEnable[5];

/**  PchAdrEn
  PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
  0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
**/
  UINT8                       PchAdrEn;

/**  Bios Interface Unlock
  Enable(0x1)/Disable(0x0) Bios Interface Unlock.
  $EN_DIS
**/
  UINT8                       BiosInterface;

/**  BIOS Lock
  Enable(0x1)/Disable(0x0) the IBL BIOS Lock Enable feature. Required to be enabled
  to ensure SMM protection of flash.
  $EN_DIS
**/
  UINT8                       PchBiosLock;

/**  Enable Timed GPIO0
  Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
  as extension of Hammock Harbor time synchronization
  $EN_DIS
**/
  UINT8                       EnableTimedGpio0;

/**  Enable Timed GPIO1
  Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
  as extension of Hammock Harbor time synchronization
  $EN_DIS
**/
  UINT8                       EnableTimedGpio1;

/**  GPIO IRQ Route
  Route all GPIOs to one of the IRQ. Default = 0xE : IRQ14, 0xF : IRQ15
**/
  UINT8                       PchGpioIrqRoute;

/**  FSP smm init enable
  Enable / Disable FSP smm init
  $EN_DIS
**/
  UINT8                       FspSmmInitEn;

/**  C2C3TT
  Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
  0: Default, Bit[11:0] : C2 to C3 Transition Timer
**/
  UINT8                       CpuPmC2c3tt;

/**  Processor Enable Monitor MWAIT
  Enable(Default) or Disable Processor Monitor MWAIT
  $EN_DIS
**/
  UINT8                       CpuPmMonitorMWait;

/**  Processor TurboMode Function
  Enable(Default) or Disable Processor TurboMode Function
  $EN_DIS
**/
  UINT8                       CpuPmTurboMode;

/**  Hardware P-States
  Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
  Native Mode:Hardware chooses a P-state based on OS guidance\n
  Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
  0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
**/
  UINT8                       CpuPmProcessorHWPMEnable;

/**  HardwarePM Interrupt
  Enable or Disable (Default) Hardware PM Interrupt
  $EN_DIS
**/
  UINT8                       CpuPmProcessorHWPMInterrupt;

/**  EPP Profile
  Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
  Power, 255: Power
  0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
**/
  UINT8                       CpuPmProcessorEPPProfile;

/**  Boot Performance Mode
  Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
  1: Max Efficiency
  0: Max Performance (Default), 1: Max Efficiency
**/
  UINT8                       CpuPmBootPstate;

/**  Power Performance Tuning
  Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
  2: PECI Controls EPB
  0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
**/
  UINT8                       CpuPmPwrPerfTuning;

/**  AvxIccpLevel
  AVX ICCP pre-grant level, 1- 128 Heavy , 2- 256 Light , 3- 256 Heavy , 4- 512 Light
  , 5- 512 Heavy , 6- AMX
  1:128 Heavy , 2:256 Light , 3:256 Heavy , 4:512 Light , 5:512 Heavy , 6:AMX
**/
  UINT8                       AvxIccpLevel;

/**  AvxLicensePreGrant
  AVX License Pre-Grant Override, 0- Disable(Default) , 1- Enable
  $EN_DIS
**/
  UINT8                       AvxLicensePreGrant;

/**  Workload Configuration
  This allows optimization for the workload characterization. <b>0: Balanced (Default)</b>,
  2: I/O sensitive
  0: Balanced, 2: I/O sensitive
**/
  UINT8                       WorkLdConfig;

/**  FSPS Upd settings support
  : FSPS Upd settings support
  $EN_DIS
**/
  UINT8                       FspsUpdSupport;

/** N/A
  Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
**/
  EFI_PHYSICAL_ADDRESS        SecurityCctVarStorageMetadataNodePtr;

/** N/A
**/
  UINT8                       ReservedSiliconInitUpd[16];

} FSPS_CONFIG;


typedef struct {

/** N/A
**/
  FSP_UPD_HEADER              FspUpdHeader;

/** N/A
**/
  FSPS_ARCH2_UPD              FspsArchUpd;

/** N/A
**/
  FSPS_CONFIG                 FspsConfig;

/** N/A
**/
  UINT16                      UpdTerminator;

} FSPS_UPD;

#pragma pack()

#endif
