/** @file

Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
  list of conditions and the following disclaimer in the documentation and/or
  other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
  be used to endorse or promote products derived from this software without
  specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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  This file is automatically generated. Please do NOT modify !!!

**/

#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__

#include <FspUpd.h>

#pragma pack(1)


///
/// Azalia Header structure
///
typedef struct {
  UINT16 VendorId;           ///< Codec Vendor ID
  UINT16 DeviceId;           ///< Codec Device ID
  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
} AZALIA_HEADER;

///
/// Audio Azalia Verb Table structure
///
typedef struct {
  AZALIA_HEADER Header;      ///< AZALIA PCH header
  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
} AUDIO_AZALIA_VERB_TABLE;

///
/// Refer to the definition of PCH_INT_PIN
///
typedef enum {
  SiPchNoInt,        ///< No Interrupt Pin
  SiPchIntA,
  SiPchIntB,
  SiPchIntC,
  SiPchIntD
} SI_PCH_INT_PIN;
///
/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
///
typedef struct {
  UINT8        Device;                  ///< Device number
  UINT8        Function;                ///< Device function
  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
  UINT8        Irq;                     ///< IRQ to be set for device.
} SI_PCH_DEVICE_INTERRUPT_CONFIG;

#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices


/** Fsp S Configuration
**/
typedef struct {

/** Offset 0x0040 - BgpdtHash[6]
  BgpdtHash values
**/
  UINT64                      BgpdtHash[6];

/** Offset 0x0070 - BiosGuardAttr
  BiosGuardAttr default values
**/
  UINT32                      BiosGuardAttr;

/** Offset 0x0074
**/
  UINT8                       FspsUpdRsvd0[4];

/** Offset 0x0078 - BiosGuardModulePtr
  BiosGuardModulePtr default values
**/
  UINT64                      BiosGuardModulePtr;

/** Offset 0x0080 - EcProvisionEav
  EcProvisionEav function pointer. \n
  @code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8
  *ReturnValue); @endcode
**/
  UINT64                      EcProvisionEav;

/** Offset 0x0088 - EcBiosGuardCmdLock
  EcBiosGuardCmdLock function pointer. \n
  @code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode
**/
  UINT64                      EcBiosGuardCmdLock;

/** Offset 0x0090 - PCH eSPI Host and Device BME enabled
  PCH eSPI Host and Device BME enabled
  $EN_DIS
**/
  UINT8                       PchEspiBmeHostDeviceEnabled;

/** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL)
  Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
  addresseses from range 0x0 - 0x7FF
  $EN_DIS
**/
  UINT8                       PchEspiLockLinkConfiguration;

/** Offset 0x0092 - Enable Host C10 reporting through eSPI
  Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
  $EN_DIS
**/
  UINT8                       PchEspiHostC10ReportEnable;

/** Offset 0x0093 - Espi Lgmr Memory Range decode
  This option enables or disables espi lgmr
  $EN_DIS
**/
  UINT8                       PchEspiLgmrEnable;

/** Offset 0x0094 - PCH eSPI PmHAE
  This option enables or disables espi lgmr
  $EN_DIS
**/
  UINT8                       PchEspiPmHAE;

/** Offset 0x0095 - PCH eSPI HideNonFatalErrors
  This option enables or disables espi lgmr
  $EN_DIS
**/
  UINT8                       PchEspiHideNonFatalErrors;

/** Offset 0x0096 - PCH eSPI NmiEnableCs1
  Set this bit to enable eSPI NMI VW events to be processed by the SOC
  $EN_DIS
**/
  UINT8                       PchEspiNmiEnableCs1;

/** Offset 0x0097
**/
  UINT8                       FspsUpdRsvd1;

/** Offset 0x0098 - CpuBistData
  Pointer CPU BIST Data
**/
  UINT64                      CpuBistData;

/** Offset 0x00A0 - CpuMpPpi
  <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
  If not NULL, FSP will use the boot loader's implementation of multiprocessing.
  See section 5.1.4 of the FSP Integration Guide for more details.
**/
  UINT64                      CpuMpPpi;

/** Offset 0x00A8 - AC Split Lock
  Enable/Disable #AC check on split lock. <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       AcSplitLock;

/** Offset 0x00A9 - GP Fault UC Lock
  Enable/Disable GP Fault check on UC lock. <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       GpfaultUcLock;

/** Offset 0x00AA - IFU enable/disable
  Enable or Disable Instruction Fetch Unit(IFU). When enabled, Instructions will be
  prefetch to the cache.
  $EN_DIS
**/
  UINT8                       IfuEnable;

/** Offset 0x00AB - TccMode enable/disable
  DEPRECATED.Enable will activate TCC Mode and disable will deactivate TCC Mode .This
  is temporary to skip some of the TCC related register access in Non-RT SKU's
  $EN_DIS
**/
  UINT8                       TccMode;

/** Offset 0x00AC - Enable Gt CLOS
  0(Default)=Disable, 1=Enable
  $EN_DIS
**/
  UINT8                       GtClosEnable;

/** Offset 0x00AD - Enable L2 Qos Enumerate
  0(Default)=Disable, 1=Enable
  $EN_DIS
**/
  UINT8                       L2QosEnumerationEn;

/** Offset 0x00AE
**/
  UINT8                       EmbReserved4FspsUpd[1];

/** Offset 0x00AF
**/
  UINT8                       EmbReserved0FspsUpd[2];

/** Offset 0x00B1 - Enable/Disable CrashLog
  Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
  $EN_DIS
**/
  UINT8                       CpuCrashLogEnable;

/** Offset 0x00B2
**/
  UINT8                       FspsUpdRsvd2[3];

/** Offset 0x00B5
**/
  UINT8                       UnusedUpdSpace0[3];

/** Offset 0x00B8 - StreamTracer Mode
  Disable: Disable StreamTracer, Advanced Tracing: StreamTracer size 512MB - Recommended
  when all groups in high verbosity are traced in 'red', Auto: StreamTracer size
  8MB - Recommended when using up to 8 groups red or up to 16 groups in green in
  med verbosity, User input: Allow User to enter a size in the range of 64KB-512MB
  0: Disable (Default), 524288: Advanced Tracing , 8192: Auto , 3: User input
**/
  UINT32                      StreamTracerMode;

/** Offset 0x00BC
**/
  UINT8                       UnusedUpdSpace1[4];

/** Offset 0x00C0 - MicrocodeRegionBase
  Memory Base of Microcode Updates
**/
  UINT64                      MicrocodeRegionBase;

/** Offset 0x00C8 - MicrocodeRegionSize
  Size of Microcode Updates
**/
  UINT64                      MicrocodeRegionSize;

/** Offset 0x00D0 - Enable or Disable TXT
  Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
  Execution Technology. Changes require a full power cycle to take effect. <b>0:
  Disable</b>, 1: Enable.
  $EN_DIS
**/
  UINT8                       TxtEnable;

/** Offset 0x00D1 - PpinSupport to view Protected Processor Inventory Number
  PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
  off this feature. When 'PPIN Enable Mode' is selected, this shows second option
  where feature can be enabled based on EOM (End of Manufacturing) flag or it is
  always enabled
  0: Disable, 1: Enable, 2: Auto
**/
  UINT8                       PpinSupport;

/** Offset 0x00D2 - Advanced Encryption Standard (AES) feature
  Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
  $EN_DIS
**/
  UINT8                       AesEnable;

/** Offset 0x00D3 - AvxDisable
  Enable/Disable the AVX and AVX2 Instructions
  0: Enable, 1: Disable
**/
  UINT8                       AvxDisable;

/** Offset 0x00D4 - X2ApicEnable
  Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled',
  'VT-d' option must be 'Enabled'.
  $EN_DIS
**/
  UINT8                       X2ApicEnable;

/** Offset 0x00D5 - P-state ratios for max 16 version of custom P-state table
  P-state ratios for max 16 version of custom P-state table. This table is used for
  OS versions limited to a max of 16 P-States. If the first entry of this table is
  0, or if Number of Entries is 16 or less, then this table will be ignored, and
  up to the top 16 values of the StateRatio table will be used instead. Valid Range
  of each entry is 0 to 0x7F
**/
  UINT8                       StateRatioMax16[16];

/** Offset 0x00E5 - Enable or Disable Intel SpeedStep Technology
  Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       Eist;

/** Offset 0x00E6 - Enable or Disable Energy Efficient P-state
  Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
  to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
  for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
  MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is
  supported. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       EnergyEfficientPState;

/** Offset 0x00E7 - Enable or Disable Energy Efficient Turbo
  Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
  lower the turbo frequency to increase efficiency. Recommended only to disable in
  overclocking situations where turbo frequency must remain constant. Otherwise,
  leave enabled. <b>0: Disable</b>; 1: Enable
  $EN_DIS
**/
  UINT8                       EnergyEfficientTurbo;

/** Offset 0x00E8 - Enable or Disable T states
  Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       TStates;

/** Offset 0x00E9 - Enable or Disable Thermal Reporting
  Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
  $EN_DIS
**/
  UINT8                       EnableAllThermalFunctions;

/** Offset 0x00EA - Enable or Disable CPU power states (C-states)
  Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
  100% utilized. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       Cx;

/** Offset 0x00EB - Configure C-State Configuration Lock
  Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
  $EN_DIS
**/
  UINT8                       PmgCstCfgCtrlLock;

/** Offset 0x00EC - Enable or Disable Package Cstate Demotion
  Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       PkgCStateDemotion;

/** Offset 0x00ED - Enable or Disable Package Cstate UnDemotion
  Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       PkgCStateUnDemotion;

/** Offset 0x00EE - Enable or Disable CState-Pre wake
  Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       CStatePreWake;

/** Offset 0x00EF - Enable or Disable TimedMwait Support.
  Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
  $EN_DIS
**/
  UINT8                       TimedMwait;

/** Offset 0x00F0 - Set the Max Pkg Cstate
  Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
  Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
  C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
  CPU Default, <b>255 - Auto</b>
**/
  UINT8                       PkgCStateLimit;

/** Offset 0x00F1 - ForcePr Demotion Algorithm configuration
  ForcePr Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
  0: Disable, 1: Enable
**/
  UINT8                       ForcePrDemotion;

/** Offset 0x00F2 - VrAlert Demotion Algorithm configuration
  VrAlert Demotion Algorithm configuration. 0: Disable;<b> 1: Enable</b>
  0: Disable, 1: Enable
**/
  UINT8                       VrAlertDemotion;

/** Offset 0x00F3 - Interrupt Redirection Mode Select
  Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
  Round robin; 2: Hash vector; 7: No change.
**/
  UINT8                       PpmIrmSetting;

/** Offset 0x00F4 - Turbo Mode
  Enable/Disable processor Turbo Mode. 0:disable, <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       TurboMode;

/** Offset 0x00F5 - Power Floor PCIe Gen Downgrade
  SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled).  0:
  Disable: Reduction in PCIe gen speed will not be used by SoC., <b>1: Enable </b>
  $EN_DIS
**/
  UINT8                       PowerFloorPcieGenDowngrade;

/** Offset 0x00F6 - P-state ratios for custom P-state table
  P-state ratios for custom P-state table. NumberOfEntries has valid range between
  0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
  are configurable. Valid Range of each entry is 0 to 0x7F
**/
  UINT8                       StateRatio[40];

/** Offset 0x011E - Custom Ratio State Entries
  The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
  ratio table. Sets the number of custom P-states. At least 2 states must be present
**/
  UINT8                       NumberOfEntries;

/** Offset 0x011F - Max P-State Ratio
  Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
**/
  UINT8                       MaxRatio;

/** Offset 0x0120 - Boot frequency
  Select the performance state that the BIOS will set starting from reset vector.
  0: Maximum battery performance. 1: Maximum non-turbo performance. <b>2: Turbo performance </b>
  0:0, 1:1, 2:2
**/
  UINT8                       BootFrequency;

/** Offset 0x0121 - Turbo settings Lock
  Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
  MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
  </b> 1: Enable
  $EN_DIS
**/
  UINT8                       TurboPowerLimitLock;

/** Offset 0x0122 - FastMsrHwpReq
  0: Disable; <b> 1: Enable;</b>
  $EN_DIS
**/
  UINT8                       EnableFastMsrHwpReq;

/** Offset 0x0123 - Turbo Ratio Limit Ratio array
  Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max
  is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio
  Limit Ratio0 must be greater than or equal all other ratio values. If this value
  is invalid, thn set all other active cores to minimum. Otherwise, align the Ratio
  Limit to 0. Please check each active cores. Ratio[1~7]: This Turbo Ratio Limit
  Ratio1 must be <= to Turbo Ratio Limit Ratio0~6.
**/
  UINT8                       TurboRatioLimitRatio[8];

/** Offset 0x012B - Turbo Ratio Limit Num Core array
  Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio
  is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored.
**/
  UINT8                       TurboRatioLimitNumCore[8];

/** Offset 0x0133 - ATOM Turbo Ratio Limit Ratio array
  Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective
  of the core extension mode), the core range is defined in E-core Turbo Ratio Limit
  CoreCount0-7.
**/
  UINT8                       AtomTurboRatioLimitRatio[8];

/** Offset 0x013B - ATOM Turbo Ratio Limit Num Core array
  Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo
  ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry
  is ignored.
**/
  UINT8                       AtomTurboRatioLimitNumCore[8];

/** Offset 0x0143 - Race To Halt
  Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
  in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
  Enable</b>
  $EN_DIS
**/
  UINT8                       RaceToHalt;

/** Offset 0x0144 - Enable or Disable C1 Cstate Demotion
  Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       C1StateAutoDemotion;

/** Offset 0x0145 - Enable or Disable C1 Cstate UnDemotion
  Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       C1StateUnDemotion;

/** Offset 0x0146 - Minimum Ring ratio limit override
  Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
  ratio limit
**/
  UINT8                       MinRingRatioLimit;

/** Offset 0x0147 - Maximum Ring ratio limit override
  Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
  ratio limit
**/
  UINT8                       MaxRingRatioLimit;

/** Offset 0x0148 - Resource Priority Feature
  Enable/Disable Resource Priority Feature. Enable/Disable; 0: Disable, <b>1: Enable </b>
  $EN_DIS
**/
  UINT8                       EnableRp;

/** Offset 0x0149 - Enable or Disable HWP
  Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
  CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
  Enable;</b>
  $EN_DIS
**/
  UINT8                       Hwp;

/** Offset 0x014A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
  Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       HwpInterruptControl;

/** Offset 0x014B - Enable or Disable HwP Autonomous Per Core P State OS control
  Disable Autonomous PCPS Autonomous will request the same value for all cores all
  the time. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       EnableHwpAutoPerCorePstate;

/** Offset 0x014C - Enable or Disable HwP Autonomous EPP Grouping
  Enable EPP grouping Autonomous will request the same values for all cores with same
  EPP. Disable EPP grouping autonomous will not necessarily request same values for
  all cores with same EPP. 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       EnableHwpAutoEppGrouping;

/** Offset 0x014D - Dynamic Efficiency Control
  Enable or Disable SoC to control energy efficiency targets autonomously, regardless
  of EPP, EPB and other SW inputs. 0: Disable; </b>1: Enable <b>
  $EN_DIS
**/
  UINT8                       EnableDynamicEfficiencyControl;

/** Offset 0x014E - Misc Power Management MSR Lock
  Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, <b>1:
  Enable </b>
  $EN_DIS
**/
  UINT8                       HwpLock;

/** Offset 0x014F - Power Floor Managment for SOC
  Option to disable Power Floor Managment for SOC. Disabling this might effectively
  raise power floor of the SoC and may lead to stability issues. 0: Disable, <b>1:
  Enable </b>
  $EN_DIS
**/
  UINT8                       PowerFloorManagement;

/** Offset 0x0150 - Power Floor Disaplay Disconnect
  SoC can disconnect secondary/external display to lower SoC floor power (Default
  disabled).  0: Disable: Display disconnect will not be used by SoC., </b>1: Enable <b>
  $EN_DIS
**/
  UINT8                       PowerFloorDisplayDisconnect;

/** Offset 0x0151 - Memory size per thread allocated for Processor Trace
  Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
  and size in bytes per thread, from 4KB to 128MB.\n
  <b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
  0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M
**/
  UINT8                       ProcessorTraceMemSize;

/** Offset 0x0152 - Enable or Disable MLC Streamer Prefetcher
  Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
  $EN_DIS
**/
  UINT8                       MlcStreamerPrefetcher;

/** Offset 0x0153 - Enable or Disable MLC Spatial Prefetcher
  Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       MlcSpatialPrefetcher;

/** Offset 0x0154 - Enable or Disable Monitor /MWAIT instructions
  Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
  should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
  $EN_DIS
**/
  UINT8                       MonitorMwaitEnable;

/** Offset 0x0155 - Enable or Disable initialization of machine check registers
  Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
  $EN_DIS
**/
  UINT8                       MachineCheckEnable;

/** Offset 0x0156 - Control on Processor Trace output scheme
  Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
  0: Single Range Output, 1: ToPA Output
**/
  UINT8                       ProcessorTraceOutputScheme;

/** Offset 0x0157 - Enable or Disable Processor Trace feature
  Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       ProcessorTraceEnable;

/** Offset 0x0158 - Processor trace enabled for Bsp only or all cores
  Processor trace enabled for Bsp only or all cores; <b>0: all cores</b>; 1: Bsp only.
  0: all cores, 1: Bsp only
**/
  UINT8                       ProcessorTraceBspOnly;

/** Offset 0x0159 - Enable/Disable processor trace Timing Packet
  Enable/Disable collocting processor trace performance (CYC, TSC); <b>0: Disable</b>;
  1: Enable.
  $EN_DIS
**/
  UINT8                       ProcessorTraceTimingPacket;

/** Offset 0x015A - Enable or Disable Three Strike Counter
  Enable (default): Three Strike counter will be incremented. Disable: Prevents Three
  Strike counter from incrementing; 0: Disable; <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       ThreeStrikeCounter;

/** Offset 0x015B - UFS enable/disable
  Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
  0 and (0,1) to enable controller 1
  $EN_DIS
**/
  UINT8                       UfsEnable[2];

/** Offset 0x015D - UFS Inline Encryption enable/disable
  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
  to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
  for controller 1
  $EN_DIS
**/
  UINT8                       UfsInlineEncryption[2];

/** Offset 0x015F - UFS Connection Status
  UFS Connection Status, One byte for each Controller - (1,0) to UFS connected to
  controller 0 and (0,1) to UFS connected to controller 1
  $EN_DIS
**/
  UINT8                       UfsDeviceConnected[2];

/** Offset 0x0161 - Enable/Disable PCIe tunneling for USB4
  Enable/Disable PCIe tunneling for USB4, default is enable
  $EN_DIS
**/
  UINT8                       ITbtPcieTunnelingForUsb4;

/** Offset 0x0162
**/
  UINT8                       FspsUpdRsvd3[2];

/** Offset 0x0164 - ITBTForcePowerOn Timeout value
  ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
  100 = 100 ms.
**/
  UINT16                      ITbtForcePowerOnTimeoutInMs;

/** Offset 0x0166 - ITbtConnectTopology Timeout value
  ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
  is 0-10000. 100 = 100 ms.
**/
  UINT16                      ITbtConnectTopologyTimeoutInMs;

/** Offset 0x0168 - ITBT DMA LTR
  TCSS DMA1, DMA2 LTR value
**/
  UINT16                      ITbtDmaLtr[2];

/** Offset 0x016C - ITbt Usb4CmMode value
  ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
**/
  UINT8                       Usb4CmMode;

/** Offset 0x016D
**/
  UINT8                       FspsUpdRsvd4[11];

/** Offset 0x0178 - FSPS Validation
  Point to FSPS Validation configuration structure
**/
  UINT64                      FspsValidationPtr;

/** Offset 0x0180 - IEH Mode
  Integrated Error Handler Mode, 0: Bypass, 1: Enable
  0: Bypass, 1:Enable
**/
  UINT8                       IehMode;

/** Offset 0x0181 - PSF Tcc
  Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency
  by disable some psf power management features, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PsfTccEnable;

/** Offset 0x0182 - Fusa Configuration
  Fusa (Functional Safety) Enable Fusa Feature, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaConfigEnable;

/** Offset 0x0183 - Opio Recentering Ctrl
  Opio Recentering Disabling for Pcie Latency Improvement, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       OpioRecenter;

/** Offset 0x0184 - Fusa Run Start Up Array BIST for Module 0
  Enabling this will execute startup array test for Module 0 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunStartupArrayBistMod0;

/** Offset 0x0185 - Fusa Run Start Up Array BIST for Module 1
  Enabling this will execute startup array test for Module 1 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunStartupArrayBistMod1;

/** Offset 0x0186 - Fusa Run Start Up Scan BIST for Module 0
  Enabling this will execute startup scan test for module 0 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunStartupScanBistMod0;

/** Offset 0x0187 - Fusa Run Start Up Scan BIST for Module 1
  Enabling this will execute startup scan test for module 1 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunStartupScanBistMod1;

/** Offset 0x0188 - Fusa Run Periodic Array BIST for Module 0
  Enabling this will execute periodic array test for module 0 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunPeriodicArrayBistMod0;

/** Offset 0x0189 - Fusa Run Periodic Array BIST for Module 1
  Enabling this will execute periodic array test for module 1 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunPeriodicArrayBistMod1;

/** Offset 0x018A - Fusa Run Periodic Scan BIST for Module 0
  Enabling this will execute periodic scan test for module 0 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunPeriodicScanBistMod0;

/** Offset 0x018B - Fusa Run Periodic Scan BIST for Module 1
  Enabling this will execute periodic scan test for module 1 during boot, 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       FusaRunPeriodicScanBistMod1;

/** Offset 0x018C
**/
  UINT8                       FusaReserved2FspsUpd[15];

/** Offset 0x019B
**/
  UINT8                       UnusedUpdSpace2;

/** Offset 0x019C - Fusa Startup Pattern File Base Address
  Fusa (Functional Safety) Startup Pattern File Base Address
**/
  UINT32                      FusaStartupPatternAddr;

/** Offset 0x01A0 - Fusa Periodic Pattern File Base Address
  Fusa (Functional Safety) Periodic Pattern File Base Address
**/
  UINT32                      FusaPeriodicPatternAddr;

/** Offset 0x01A4 - RTC BIOS Interface Lock
  Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
  $EN_DIS
**/
  UINT8                       RtcBiosInterfaceLock;

/** Offset 0x01A5 - RTC Cmos Memory Lock
  Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
  and and lower 128-byte bank of RTC RAM.
  $EN_DIS
**/
  UINT8                       RtcMemoryLock;

/** Offset 0x01A6 - AMT Switch
  Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
  $EN_DIS
**/
  UINT8                       AmtEnabled;

/** Offset 0x01A7 - SOL Switch
  Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
  Setting is invalid if AmtEnabled is 0.
  $EN_DIS
**/
  UINT8                       AmtSolEnabled;

/** Offset 0x01A8 - WatchDog Timer Switch
  Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
  is invalid if AmtEnabled is 0.
  $EN_DIS
**/
  UINT8                       WatchDogEnabled;

/** Offset 0x01A9
**/
  UINT8                       UnusedUpdSpace3;

/** Offset 0x01AA - OS Timer
  16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
  UINT16                      WatchDogTimerOs;

/** Offset 0x01AC - BIOS Timer
  16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
  UINT16                      WatchDogTimerBios;

/** Offset 0x01AE - Iax Switch
  Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality.
  $EN_DIS
**/
  UINT8                       IaxEnable;

/** Offset 0x01AF
**/
  UINT8                       FspsUpdRsvd5;

/** Offset 0x01B0 - ISH GP GPIO Pin Muxing
  Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
**/
  UINT32                      IshGpGpioPinMuxing[12];

/** Offset 0x01E0 - ISH UART Rx Pin Muxing
  Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
**/
  UINT32                      IshUartRxPinMuxing[3];

/** Offset 0x01EC - ISH UART Tx Pin Muxing
  Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
**/
  UINT32                      IshUartTxPinMuxing[3];

/** Offset 0x01F8 - ISH UART Rts Pin Muxing
  Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
**/
  UINT32                      IshUartRtsPinMuxing[3];

/** Offset 0x0204 - ISH UART Rts Pin Muxing
  Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
**/
  UINT32                      IshUartCtsPinMuxing[3];

/** Offset 0x0210 - ISH I2C SDA Pin Muxing
  Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
**/
  UINT32                      IshI2cSdaPinMuxing[3];

/** Offset 0x021C - ISH I2C SCL Pin Muxing
  Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
**/
  UINT32                      IshI2cSclPinMuxing[3];

/** Offset 0x0228 - ISH SPI MOSI Pin Muxing
  Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
**/
  UINT32                      IshSpiMosiPinMuxing[2];

/** Offset 0x0230 - ISH SPI MISO Pin Muxing
  Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
**/
  UINT32                      IshSpiMisoPinMuxing[2];

/** Offset 0x0238 - ISH SPI CLK Pin Muxing
  Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
**/
  UINT32                      IshSpiClkPinMuxing[2];

/** Offset 0x0240 - ISH SPI CS#N Pin Muxing
  Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible
  values. N-SPI number, 0-1.
**/
  UINT32                      IshSpiCsPinMuxing[4];

/** Offset 0x0250 - ISH GP GPIO Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
  respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
  0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31
**/
  UINT8                       IshGpGpioPadTermination[12];

/** Offset 0x025C - ISH UART Rx Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
  respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
  Rx, and so on.
**/
  UINT8                       IshUartRxPadTermination[3];

/** Offset 0x025F - ISH UART Tx Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
  respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
  Tx, and so on.
**/
  UINT8                       IshUartTxPadTermination[3];

/** Offset 0x0262 - ISH UART Rts Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
  respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
  Rts, and so on.
**/
  UINT8                       IshUartRtsPadTermination[3];

/** Offset 0x0265 - ISH UART Rts Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
  respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
  Cts, and so on.
**/
  UINT8                       IshUartCtsPadTermination[3];

/** Offset 0x0268 - ISH I2C SDA Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
  and so on.
**/
  UINT8                       IshI2cSdaPadTermination[3];

/** Offset 0x026B - ISH I2C SCL Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
  and so on.
**/
  UINT8                       IshI2cSclPadTermination[3];

/** Offset 0x026E - ISH SPI MOSI Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
  respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
  Mosi, and so on.
**/
  UINT8                       IshSpiMosiPadTermination[2];

/** Offset 0x0270 - ISH SPI MISO Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
  respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
  Miso, and so on.
**/
  UINT8                       IshSpiMisoPadTermination[2];

/** Offset 0x0272 - ISH SPI CLK Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
  respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
  and so on.
**/
  UINT8                       IshSpiClkPadTermination[2];

/** Offset 0x0274 - ISH SPI CS#N Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
  respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
  Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3
**/
  UINT8                       IshSpiCsPadTermination[4];

/** Offset 0x0278 - Enable PCH ISH SPI Cs#N pins assigned
  Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
  number: 0-1
**/
  UINT8                       PchIshSpiCsEnable[4];

/** Offset 0x027C - Enable PCH ISH SPI Cs0 pins assigned
  Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshSpiCs0Enable[1];

/** Offset 0x027D - Enable PCH ISH SPI pins assigned
  Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshSpiEnable[1];

/** Offset 0x027E - Enable PCH ISH UART pins assigned
  Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshUartEnable[2];

/** Offset 0x0280 - Enable PCH ISH I2C pins assigned
  Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshI2cEnable[3];

/** Offset 0x0283 - Enable PCH ISH GP pins assigned
  Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshGpEnable[12];

/** Offset 0x028F - PCH ISH PDT Unlock Msg
  0: False; 1: True.
  $EN_DIS
**/
  UINT8                       PchIshPdtUnlock;

/** Offset 0x0290 - PCH ISH MSI Interrupts
  0: False; 1: True.
  $EN_DIS
**/
  UINT8                       PchIshMsiInterrupt;

/** Offset 0x0291 - End of Post message
  Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
  EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
  0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
  UINT8                       EndOfPostMessage;

/** Offset 0x0292 - D0I3 Setting for HECI Disable
  Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
  HECI devices
  $EN_DIS
**/
  UINT8                       DisableD0I3SettingForHeci;

/** Offset 0x0293 - Mctp Broadcast Cycle
  Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       MctpBroadcastCycle;

/** Offset 0x0294 - ME Unconfig on RTC clear
  0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
  2: Cmos is clear, status unkonwn. 3: Reserved
  0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
  is clear, 3: Reserved
**/
  UINT8                       MeUnconfigOnRtcClear;

/** Offset 0x0295 - CSE Data Resilience Support
  0: Disable CSE Data Resilience Support. <b>1: Enable CSE Data Resilience Support.</b>
  2: Enable CSE Data Resilience but defer to DXE.
  $EN_DIS
**/
  UINT8                       CseDataResilience;

/** Offset 0x0296 - PSE EOM Flow Control
  0: Disable PSE EOM Flow. <b>1: Enable PSE EOM Flow.</b>
  $EN_DIS
**/
  UINT8                       PseEomFlowEnable;

/** Offset 0x0297 - ISH I3C SDA Pin Muxing
  Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values.
**/
  UINT8                       IshI3cSdaPinMuxing[8];

/** Offset 0x029F - ISH I3C SCL Pin Muxing
  Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values.
**/
  UINT8                       IshI3cSclPinMuxing[8];

/** Offset 0x02A7 - ISH I3C SDA Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
  respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
  and so on.
**/
  UINT8                       IshI3cSdaPadTermination[2];

/** Offset 0x02A9 - ISH I3C SCL Pad termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
  respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
  and so on.
**/
  UINT8                       IshI3cSclPadTermination[2];

/** Offset 0x02AB - Enable PCH ISH I3C pins assigned
  Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
  UINT8                       PchIshI3cEnable[2];

/** Offset 0x02AD
**/
  UINT8                       FspsUpdRsvd6[3];

/** Offset 0x02B0 - Power button debounce configuration
  Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
  be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
**/
  UINT32                      PmcPowerButtonDebounce;

/** Offset 0x02B4 - PCH USB2 PHY Power Gating enable
  1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
  Sus Well PG
  $EN_DIS
**/
  UINT8                       PmcUsb2PhySusPgEnable;

/** Offset 0x02B5 - VRAlert# Pin
  When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
  to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
  $EN_DIS
**/
  UINT8                       PchPmVrAlert;

/** Offset 0x02B6 - ModPHY SUS Power Domain Dynamic Gating
  Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
  PCH-H. 0: disable, 1: enable
  $EN_DIS
**/
  UINT8                       PmcModPhySusPgEnable;

/** Offset 0x02B7 - V1p05-PHY supply external FET control
  Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
  supply. 0: disable, 1: enable
  $EN_DIS
**/
  UINT8                       PmcV1p05PhyExtFetControlEn;

/** Offset 0x02B8 - V1p05-IS supply external FET control
  Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
  supply. 0: disable, 1: enable
  $EN_DIS
**/
  UINT8                       PmcV1p05IsExtFetControlEn;

/** Offset 0x02B9 - PCH Pm PME_B0_S5_DIS
  When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
  $EN_DIS
**/
  UINT8                       PchPmPmeB0S5Dis;

/** Offset 0x02BA - PCH Pm Wol Enable Override
  Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
  $EN_DIS
**/
  UINT8                       PchPmWolEnableOverride;

/** Offset 0x02BB - PCH Pm WoW lan Enable
  Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
  $EN_DIS
**/
  UINT8                       PchPmWoWlanEnable;

/** Offset 0x02BC - PCH Pm Slp S3 Min Assert
  SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
  UINT8                       PchPmSlpS3MinAssert;

/** Offset 0x02BD - PCH Pm Slp S4 Min Assert
  SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
  UINT8                       PchPmSlpS4MinAssert;

/** Offset 0x02BE - PCH Pm Slp Sus Min Assert
  SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
  UINT8                       PchPmSlpSusMinAssert;

/** Offset 0x02BF - PCH Pm Slp A Min Assert
  SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
  UINT8                       PchPmSlpAMinAssert;

/** Offset 0x02C0 - PCH Pm Slp Strch Sus Up
  Enable SLP_X Stretching After SUS Well Power Up.
  $EN_DIS
**/
  UINT8                       PchPmSlpStrchSusUp;

/** Offset 0x02C1 - PCH Pm Slp Lan Low Dc
  Enable/Disable SLP_LAN# Low on DC Power.
  $EN_DIS
**/
  UINT8                       PchPmSlpLanLowDc;

/** Offset 0x02C2 - PCH Pm Pwr Btn Override Period
  PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
  UINT8                       PchPmPwrBtnOverridePeriod;

/** Offset 0x02C3 - PCH Pm Disable Native Power Button
  Power button native mode disable.
  $EN_DIS
**/
  UINT8                       PchPmDisableNativePowerButton;

/** Offset 0x02C4 - PCH Pm ME_WAKE_STS
  Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
  $EN_DIS
**/
  UINT8                       PchPmMeWakeSts;

/** Offset 0x02C5 - PCH Pm WOL_OVR_WK_STS
  Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
  $EN_DIS
**/
  UINT8                       PchPmWolOvrWkSts;

/** Offset 0x02C6 - PCH Pm Reset Power Cycle Duration
  Could be customized in the unit of second. Please refer to EDS for all support settings.
  0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
  UINT8                       PchPmPwrCycDur;

/** Offset 0x02C7 - PCH Pm Pcie Pll Ssc
  Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
  BIOS override.
**/
  UINT8                       PchPmPciePllSsc;

/** Offset 0x02C8 - Enable TCO timer.
  When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
  huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
  emulation must be enabled, and WDAT table must not be exposed to the OS.
  $EN_DIS
**/
  UINT8                       EnableTcoTimer;

/** Offset 0x02C9 - Enable Timed GPIO0
  Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
  as extension of Hammock Harbor time synchronization.
  $EN_DIS
**/
  UINT8                       EnableTimedGpio0;

/** Offset 0x02CA - Enable Timed GPIO 1.
  When FALSE, it disables Timed GPIO 1.
  $EN_DIS
**/
  UINT8                       EnableTimedGpio1;

/** Offset 0x02CB
**/
  UINT8                       EmbReserved3FspsUpd[2];

/** Offset 0x02CD - Enable PS_ON.
  PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
  target that will be required by the California Energy Commission (CEC). When FALSE,
  PS_ON is to be disabled.
  $EN_DIS
**/
  UINT8                       PsOnEnable;

/** Offset 0x02CE - Pmc Cpu C10 Gate Pin Enable
  Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
  and VccSTG rails instead of SLP_S0# pin.
  $EN_DIS
**/
  UINT8                       PmcCpuC10GatePinEnable;

/** Offset 0x02CF - OS IDLE Mode Enable
  Enable/Disable OS Idle Mode
  $EN_DIS
**/
  UINT8                       PmcOsIdleEnable;

/** Offset 0x02D0 - S0ix Auto-Demotion
  Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
  $EN_DIS
**/
  UINT8                       PchS0ixAutoDemotion;

/** Offset 0x02D1 - Latch Events C10 Exit
  When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
  captured on C10 exit (instead of C10 entry which is default)
  $EN_DIS
**/
  UINT8                       PchPmLatchEventsC10Exit;

/** Offset 0x02D2 - PCH Energy Reporting
  Disable/Enable PCH to CPU energy report feature.
  $EN_DIS
**/
  UINT8                       PchPmDisableEnergyReport;

/** Offset 0x02D3 - Low Power Mode Enable/Disable config mask
  Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
  to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
  LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
  UINT8                       PmcLpmS0ixSubStateEnableMask;

/** Offset 0x02D4 - PCH PMC ER Debug mode
  Disable/Enable Energy Reporting Debug Mode.
  $EN_DIS
**/
  UINT8                       PchPmErDebugMode;

/** Offset 0x02D5 - PMC C10 dynamic threshold dajustment enable
  Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
  $EN_DIS
**/
  UINT8                       PmcC10DynamicThresholdAdjustment;

/** Offset 0x02D6 - Enable LOCKDOWN BIOS LOCK
  Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
  protection.
  $EN_DIS
**/
  UINT8                       PchLockDownBiosLock;

/** Offset 0x02D7 - Enable LOCKDOWN SMI
  Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
  $EN_DIS
**/
  UINT8                       PchLockDownGlobalSmi;

/** Offset 0x02D8 - Enable LOCKDOWN BIOS Interface
  Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
  $EN_DIS
**/
  UINT8                       PchLockDownBiosInterface;

/** Offset 0x02D9 - Unlock all GPIO pads
  Force all GPIO pads to be unlocked for debug purpose.
  $EN_DIS
**/
  UINT8                       PchUnlockGpioPads;

/** Offset 0x02DA - PCH Flash Protection Ranges Write Enble
  Write or erase is blocked by hardware.
**/
  UINT8                       PchWriteProtectionEnable[5];

/** Offset 0x02DF - PCH Flash Protection Ranges Read Enble
  Read is blocked by hardware.
**/
  UINT8                       PchReadProtectionEnable[5];

/** Offset 0x02E4 - PCH Protect Range Limit
  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
  limit comparison.
**/
  UINT16                      PchProtectedRangeLimit[5];

/** Offset 0x02EE - PCH Protect Range Base
  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
  UINT16                      PchProtectedRangeBase[5];

/** Offset 0x02F8 - PCIe PTM enable/disable
  Enable/disable Precision Time Measurement for PCIE Root Ports.
**/
  UINT8                       PciePtm[28];

/** Offset 0x0314 - PCH PCIe root port connection type
  0: built-in device, 1:slot
**/
  UINT8                       PcieRpSlotImplemented[28];

/** Offset 0x0330 - PCIE RP Access Control Services Extended Capability
  Enable/Disable PCIE RP Access Control Services Extended Capability
**/
  UINT8                       PcieRpAcsEnabled[28];

/** Offset 0x034C - PCIE RP Clock Power Management
  Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
  can still be controlled by L1 PM substates mechanism
**/
  UINT8                       PcieRpEnableCpm[28];

/** Offset 0x0368 - PCIE RP Detect Timeout Ms
  The number of milliseconds within 0~65535 in reference code will wait for link to
  exit Detect state for enabled ports before assuming there is no device and potentially
  disabling the port.
**/
  UINT16                      PcieRpDetectTimeoutMs[24];

/** Offset 0x0398 - Enable PCIE RP HotPlug
  Indicate whether the root port is hot plug available.
**/
  UINT8                       PcieRpHotPlug[28];

/** Offset 0x03B4 - Enable PCIE RP Pm Sci
  Indicate whether the root port power manager SCI is enabled.
**/
  UINT8                       PcieRpPmSci[28];

/** Offset 0x03D0 - Enable PCIE RP Transmitter Half Swing
  Indicate whether the Transmitter Half Swing is enabled.
**/
  UINT8                       PcieRpTransmitterHalfSwing[28];

/** Offset 0x03EC - Enable PCIE RP Clk Req Detect
  Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
  UINT8                       PcieRpClkReqDetect[28];

/** Offset 0x0408 - PCIE RP Advanced Error Report
  Indicate whether the Advanced Error Reporting is enabled.
**/
  UINT8                       PcieRpAdvancedErrorReporting[28];

/** Offset 0x0424 - PCIE RP Unsupported Request Report
  Indicate whether the Unsupported Request Report is enabled.
**/
  UINT8                       PcieRpUnsupportedRequestReport[28];

/** Offset 0x0440 - PCIE RP Fatal Error Report
  Indicate whether the Fatal Error Report is enabled.
**/
  UINT8                       PcieRpFatalErrorReport[28];

/** Offset 0x045C - PCIE RP No Fatal Error Report
  Indicate whether the No Fatal Error Report is enabled.
**/
  UINT8                       PcieRpNoFatalErrorReport[28];

/** Offset 0x0478 - PCIE RP Correctable Error Report
  Indicate whether the Correctable Error Report is enabled.
**/
  UINT8                       PcieRpCorrectableErrorReport[28];

/** Offset 0x0494 - PCIE RP System Error On Fatal Error
  Indicate whether the System Error on Fatal Error is enabled.
**/
  UINT8                       PcieRpSystemErrorOnFatalError[28];

/** Offset 0x04B0 - PCIE RP System Error On Non Fatal Error
  Indicate whether the System Error on Non Fatal Error is enabled.
**/
  UINT8                       PcieRpSystemErrorOnNonFatalError[28];

/** Offset 0x04CC - PCIE RP System Error On Correctable Error
  Indicate whether the System Error on Correctable Error is enabled.
**/
  UINT8                       PcieRpSystemErrorOnCorrectableError[28];

/** Offset 0x04E8 - PCIE RP Max Payload
  Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
  UINT8                       PcieRpMaxPayload[28];

/** Offset 0x0504 - PCIE RP Pcie Speed
  Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
  PCIE_SPEED).
**/
  UINT8                       PcieRpPcieSpeed[28];

/** Offset 0x0520 - PCIE RP Physical Slot Number
  Indicates the slot number for the root port. Default is the value as root port index.
**/
  UINT8                       PcieRpPhysicalSlotNumber[28];

/** Offset 0x053C - PCIE RP Completion Timeout
  The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
**/
  UINT8                       PcieRpCompletionTimeout[28];

/** Offset 0x0558 - PCIE RP Aspm
  The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
  PchPcieAspmAutoConfig.
**/
  UINT8                       PcieRpAspm[28];

/** Offset 0x0574 - HostL0sTxDis
  Disable Host L0 transmission state
  $EN_DIS
**/
  UINT8                       HostL0sTxDis[28];

/** Offset 0x0590 - PCIE RP L1 Substates
  The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
  Default is PchPcieL1SubstatesL1_1_2.
**/
  UINT8                       PcieRpL1Substates[28];

/** Offset 0x05AC - PCIE RP Ltr Enable
  Latency Tolerance Reporting Mechanism.
**/
  UINT8                       PcieRpLtrEnable[28];

/** Offset 0x05C8 - PCIE RP Ltr Config Lock
  0: Disable; 1: Enable.
**/
  UINT8                       PcieRpLtrConfigLock[28];

/** Offset 0x05E4 - PCIE RP override default settings for EQ
  Choose PCIe EQ method
  $EN_DIS
**/
  UINT8                       PcieEqOverrideDefault[12];

/** Offset 0x05F0 - PCIE RP choose EQ method
  Choose PCIe EQ method
  0: HardwareEq, 1: FixedEq
**/
  UINT8                       PcieGen3EqMethod[12];

/** Offset 0x05FC - PCIE RP choose EQ mode
  Choose PCIe EQ mode
  0: PresetEq, 1: CoefficientEq
**/
  UINT8                       PcieGen3EqMode[12];

/** Offset 0x0608 - PCIE RP EQ local transmitter override
  Enable/Disable local transmitter override
  $EN_DIS
**/
  UINT8                       PcieGen3EqLocalTxOverrideEn[12];

/** Offset 0x0614 - PCI RP number of valid list entries
  Select number of presets or coefficients depending on the mode
**/
  UINT8                       PcieGen3EqPh3NoOfPresetOrCoeff[12];

/** Offset 0x0620 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor0List[12];

/** Offset 0x062C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor0List[12];

/** Offset 0x0638 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor1List[12];

/** Offset 0x0644 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor1List[12];

/** Offset 0x0650 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor2List[12];

/** Offset 0x065C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor2List[12];

/** Offset 0x0668 - PCIR RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor3List[12];

/** Offset 0x0674 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor3List[12];

/** Offset 0x0680 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor4List[12];

/** Offset 0x068C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor4List[12];

/** Offset 0x0698 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor5List[12];

/** Offset 0x06A4 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor5List[12];

/** Offset 0x06B0 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor6List[12];

/** Offset 0x06BC - PCIe post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor6List[12];

/** Offset 0x06C8 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor7List[12];

/** Offset 0x06D4 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor7List[12];

/** Offset 0x06E0 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor8List[12];

/** Offset 0x06EC - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor8List[12];

/** Offset 0x06F8 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PreCursor9List[12];

/** Offset 0x0704 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3PostCursor9List[12];

/** Offset 0x0710 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset0List[12];

/** Offset 0x071C - PCIe preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset1List[12];

/** Offset 0x0728 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset2List[12];

/** Offset 0x0734 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset3List[12];

/** Offset 0x0740 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset4List[12];

/** Offset 0x074C - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset5List[12];

/** Offset 0x0758 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset6List[12];

/** Offset 0x0764 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset7List[12];

/** Offset 0x0770 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset8List[12];

/** Offset 0x077C - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset9List[12];

/** Offset 0x0788 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen3EqPh3Preset10List[12];

/** Offset 0x0794 - PCIe EQ phase 1 downstream transmitter port preset
  Allows to select the downstream port preset value that will be used during phase
  1 of equalization
**/
  UINT8                       PcieGen3EqPh1DpTxPreset[12];

/** Offset 0x07A0 - PCIE RP EQ phase 1 upstream tranmitter port preset
  Allows to select the upstream port preset value that will be used during phase 1
  of equalization
**/
  UINT8                       PcieGen3EqPh1UpTxPreset[12];

/** Offset 0x07AC - PCIE RP EQ phase 2 local transmitter override preset
  Allows to select the value of the preset used during phase 2 local transmitter override
**/
  UINT8                       PcieGen3EqPh2LocalTxOverridePreset[12];

/** Offset 0x07B8 - PCIE RP choose EQ method
  Choose PCIe EQ method
  0: HardwareEq, 1: FixedEq
**/
  UINT8                       PcieGen4EqMethod[12];

/** Offset 0x07C4 - PCIE RP choose EQ mode
  Choose PCIe EQ mode
  0: PresetEq, 1: CoefficientEq
**/
  UINT8                       PcieGen4EqMode[12];

/** Offset 0x07D0 - PCIE RP EQ local transmitter override
  Enable/Disable local transmitter override
  $EN_DIS
**/
  UINT8                       PcieGen4EqLocalTxOverrideEn[12];

/** Offset 0x07DC - PCI RP number of valid list entries
  Select number of presets or coefficients depending on the mode
**/
  UINT8                       PcieGen4EqPh3NoOfPresetOrCoeff[12];

/** Offset 0x07E8 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor0List[12];

/** Offset 0x07F4 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor0List[12];

/** Offset 0x0800 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor1List[12];

/** Offset 0x080C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor1List[12];

/** Offset 0x0818 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor2List[12];

/** Offset 0x0824 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor2List[12];

/** Offset 0x0830 - PCIR RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor3List[12];

/** Offset 0x083C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor3List[12];

/** Offset 0x0848 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor4List[12];

/** Offset 0x0854 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor4List[12];

/** Offset 0x0860 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor5List[12];

/** Offset 0x086C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor5List[12];

/** Offset 0x0878 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor6List[12];

/** Offset 0x0884 - PCIe post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor6List[12];

/** Offset 0x0890 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor7List[12];

/** Offset 0x089C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor7List[12];

/** Offset 0x08A8 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor8List[12];

/** Offset 0x08B4 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor8List[12];

/** Offset 0x08C0 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PreCursor9List[12];

/** Offset 0x08CC - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3PostCursor9List[12];

/** Offset 0x08D8 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset0List[12];

/** Offset 0x08E4 - PCIe preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset1List[12];

/** Offset 0x08F0 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset2List[12];

/** Offset 0x08FC - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset3List[12];

/** Offset 0x0908 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset4List[12];

/** Offset 0x0914 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset5List[12];

/** Offset 0x0920 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset6List[12];

/** Offset 0x092C - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset7List[12];

/** Offset 0x0938 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset8List[12];

/** Offset 0x0944 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset9List[12];

/** Offset 0x0950 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen4EqPh3Preset10List[12];

/** Offset 0x095C - PCIe EQ phase 1 downstream transmitter port preset
  Allows to select the downstream port preset value that will be used during phase
  1 of equalization
**/
  UINT8                       PcieGen4EqPh1DpTxPreset[12];

/** Offset 0x0968 - PCIE RP EQ phase 1 upstream tranmitter port preset
  Allows to select the upstream port preset value that will be used during phase 1
  of equalization
**/
  UINT8                       PcieGen4EqPh1UpTxPreset[12];

/** Offset 0x0974 - PCIE RP EQ phase 2 local transmitter override preset
  Allows to select the value of the preset used during phase 2 local transmitter override
**/
  UINT8                       PcieGen4EqPh2LocalTxOverridePreset[12];

/** Offset 0x0980 - PCIE RP choose EQ method
  Choose PCIe EQ method
  0: HardwareEq, 1: FixedEq
**/
  UINT8                       PcieGen5EqMethod[12];

/** Offset 0x098C - PCIE RP choose EQ mode
  Choose PCIe EQ mode
  0: PresetEq, 1: CoefficientEq
**/
  UINT8                       PcieGen5EqMode[12];

/** Offset 0x0998 - PCIE RP EQ local transmitter override
  Enable/Disable local transmitter override
  $EN_DIS
**/
  UINT8                       PcieGen5EqLocalTxOverrideEn[12];

/** Offset 0x09A4 - PCI RP number of valid list entries
  Select number of presets or coefficients depending on the mode
**/
  UINT8                       PcieGen5EqPh3NoOfPresetOrCoeff[12];

/** Offset 0x09B0 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor0List[12];

/** Offset 0x09BC - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor0List[12];

/** Offset 0x09C8 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor1List[12];

/** Offset 0x09D4 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor1List[12];

/** Offset 0x09E0 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor2List[12];

/** Offset 0x09EC - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor2List[12];

/** Offset 0x09F8 - PCIR RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor3List[12];

/** Offset 0x0A04 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor3List[12];

/** Offset 0x0A10 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor4List[12];

/** Offset 0x0A1C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor4List[12];

/** Offset 0x0A28 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor5List[12];

/** Offset 0x0A34 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor5List[12];

/** Offset 0x0A40 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor6List[12];

/** Offset 0x0A4C - PCIe post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor6List[12];

/** Offset 0x0A58 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor7List[12];

/** Offset 0x0A64 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor7List[12];

/** Offset 0x0A70 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor8List[12];

/** Offset 0x0A7C - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor8List[12];

/** Offset 0x0A88 - PCIE RP pre-cursor coefficient list
  Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PreCursor9List[12];

/** Offset 0x0A94 - PCIE RP post-cursor coefficient list
  Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3PostCursor9List[12];

/** Offset 0x0AA0 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset0List[12];

/** Offset 0x0AAC - PCIe preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset1List[12];

/** Offset 0x0AB8 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset2List[12];

/** Offset 0x0AC4 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset3List[12];

/** Offset 0x0AD0 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset4List[12];

/** Offset 0x0ADC - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset5List[12];

/** Offset 0x0AE8 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset6List[12];

/** Offset 0x0AF4 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset7List[12];

/** Offset 0x0B00 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset8List[12];

/** Offset 0x0B0C - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset9List[12];

/** Offset 0x0B18 - PCIE RP preset list
  Provide a list of presets to be used during phase 3 EQ
**/
  UINT8                       PcieGen5EqPh3Preset10List[12];

/** Offset 0x0B24 - PCIe EQ phase 1 downstream transmitter port preset
  Allows to select the downstream port preset value that will be used during phase
  1 of equalization
**/
  UINT8                       PcieGen5EqPh1DpTxPreset[12];

/** Offset 0x0B30 - PCIE RP EQ phase 1 upstream tranmitter port preset
  Allows to select the upstream port preset value that will be used during phase 1
  of equalization
**/
  UINT8                       PcieGen5EqPh1UpTxPreset[12];

/** Offset 0x0B3C - PCIE RP EQ phase 2 local transmitter override preset
  Allows to select the value of the preset used during phase 2 local transmitter override
**/
  UINT8                       PcieGen5EqPh2LocalTxOverridePreset[12];

/** Offset 0x0B48 - Phase3 RP Gen3 EQ enable
  Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen3EqPh3Bypass[12];

/** Offset 0x0B54 - Phase3 RP Gen4 EQ enable
  Phase3 Gen4 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen4EqPh3Bypass[12];

/** Offset 0x0B60 - Phase3 RP Gen5 EQ enable
  Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen5EqPh3Bypass[12];

/** Offset 0x0B6C - Phase2-3 RP Gen3 EQ enable
  Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
  Enable Phase2-3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen3EqPh23Bypass[12];

/** Offset 0x0B78 - Phase2-3 RP Gen4 EQ enable
  Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
  Enable Phase2-3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen4EqPh23Bypass[12];

/** Offset 0x0B84 - Phase2-3 RP Gen5 EQ enable
  Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
  Enable Phase2-3
  0:Disable, 1:Enable, 2:Auto
**/
  UINT8                       PcieRpGen5EqPh23Bypass[12];

/** Offset 0x0B90 - PCET Timer
  Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default
  is 0x0(2ms)
**/
  UINT8                       PcieGen3PcetTimer[12];

/** Offset 0x0B9C - Gen4 PCET Timer
  Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default
  is 0x0(2ms)
**/
  UINT8                       PcieGen4PcetTimer[12];

/** Offset 0x0BA8 - Gen5 PCET Timer
  Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default
  is 0x0(2ms)
**/
  UINT8                       PcieGen5PcetTimer[12];

/** Offset 0x0BB4 - TS Lock Timer for Gen3
  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock
  Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0
**/
  UINT8                       PcieGen3TsLockTimer[12];

/** Offset 0x0BC0 - PTS Lock Timer for Gen4
  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock
  Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0
**/
  UINT8                       PcieGen4TsLockTimer[12];

/** Offset 0x0BCC - PTS Lock Timer for Gen5
  Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock
  Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0
**/
  UINT8                       PcieGen5TsLockTimer[12];

/** Offset 0x0BD8 - PCIE Secure Register Lock
  Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
  load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
  $EN_DIS
**/
  UINT8                       PcieSetSecuredRegisterLock;

/** Offset 0x0BD9 - Enable/Disable ASPM Optionality Compliance
  Enable/Disable ASPM Optionality Compliance.
**/
  UINT8                       PcieRpTestAspmOc[12];

/** Offset 0x0BE5 - PCIE RP Enable Peer Memory Write
  This member describes whether Peer Memory Writes are enabled on the platform.
  $EN_DIS
**/
  UINT8                       PcieEnablePeerMemoryWrite[12];

/** Offset 0x0BF1 - Assertion on Link Down GPIOs
  GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
  GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
  0:Disable, 1:Enable
**/
  UINT8                       PcieRpLinkDownGpios[12];

/** Offset 0x0BFD - PCIE Compliance Test Mode
  Compliance Test Mode shall be enabled when using Compliance Load Board.
  $EN_DIS
**/
  UINT8                       PcieComplianceTestMode;

/** Offset 0x0BFE - PCIE Rp Function Swap
  Allows BIOS to use root port function number swapping when root port of function
  0 is disabled.
  $EN_DIS
**/
  UINT8                       PcieRpFunctionSwap;

/** Offset 0x0BFF - PCIe RootPort Clock Gating
  Describes whether the PCI Express Clock Gating for each root port is enabled by
  platform modules. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PcieClockGating[12];

/** Offset 0x0C0B - PCIe RootPort Power Gating
  Describes whether the PCI Express Power Gating for each root port is enabled by
  platform modules. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PciePowerGating[12];

/** Offset 0x0C17 - PCIe RootPort VISA Clock Gating
  Describes whether the PCI Express VISA Clock Gating. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PcieVisaClockGating[12];

/** Offset 0x0C23 - PCIe RootPort AutoPower Gating
  Describes the Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PcieAutoPowerGating[12];

/** Offset 0x0C2F - PCIe RootPort PHY AutoPower Gating
  Describes the PHY Auto Power Gating for per controller. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PciePhyAutoPowerGating;

/** Offset 0x0C30 - FOMS Control Policy
  Choose the Foms Control Policy, <b>Default = 0 </b>
  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
**/
  UINT8                       PcieFomsCp[12];

/** Offset 0x0C3C - EqPhBypass Control Policy
  PCIe Equalization Phase Enable Control, <b>Disabled</b>       (0x0) : Disable Phase
  (Default), Enabled (0x1) : Enable Phase
  0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
**/
  UINT8                       PcieEqPhBypass[12];

/** Offset 0x0C48 - PCIE RP Ltr Max Snoop Latency
  Latency Tolerance Reporting, Max Snoop Latency.
**/
  UINT16                      PcieRpLtrMaxSnoopLatency[24];

/** Offset 0x0C78 - PCIE RP Ltr Max No Snoop Latency
  Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
  UINT16                      PcieRpLtrMaxNoSnoopLatency[24];

/** Offset 0x0CA8 - PCIE RP Snoop Latency Override Mode
  Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
  UINT8                       PcieRpSnoopLatencyOverrideMode[28];

/** Offset 0x0CC4 - PCIE RP Snoop Latency Override Multiplier
  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
  UINT8                       PcieRpSnoopLatencyOverrideMultiplier[28];

/** Offset 0x0CE0 - PCIE RP Snoop Latency Override Value
  Latency Tolerance Reporting, Snoop Latency Override Value.
**/
  UINT16                      PcieRpSnoopLatencyOverrideValue[24];

/** Offset 0x0D10 - PCIE RP Non Snoop Latency Override Mode
  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
  UINT8                       PcieRpNonSnoopLatencyOverrideMode[28];

/** Offset 0x0D2C - PCIE RP Non Snoop Latency Override Multiplier
  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
  UINT8                       PcieRpNonSnoopLatencyOverrideMultiplier[28];

/** Offset 0x0D48 - PCIE RP Non Snoop Latency Override Value
  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
  UINT16                      PcieRpNonSnoopLatencyOverrideValue[24];

/** Offset 0x0D78 - PCIE RP Slot Power Limit Scale
  Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
  UINT8                       PcieRpSlotPowerLimitScale[28];

/** Offset 0x0D94 - PCIE RP Slot Power Limit Value
  Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
  UINT16                      PcieRpSlotPowerLimitValue[24];

/** Offset 0x0DC4 - PCIE RP Enable Port8xh Decode
  This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
  1: Enable.
  $EN_DIS
**/
  UINT8                       PcieEnablePort8xhDecode;

/** Offset 0x0DC5 - PCIE Port8xh Decode Port Index
  The Index of PCIe Port that is selected for Port8xh Decode (1 Based).
**/
  UINT8                       PchPciePort8xhDecodePortIndex;

/** Offset 0x0DC6 - PCIE RP LTR Override Spec Compliant
  Override LTR based on Ep capability.
**/
  UINT8                       PcieRpLtrOverrideSpecCompliant[28];

/** Offset 0x0DE2 - PCIe AER _OSC Setting
  Enable/Disable Global PCIe Advanced Error Reporting
  0:Disable, 1:Enable
**/
  UINT8                       GlobalPcieAer;

/** Offset 0x0DE3 - PCIe TBT Performance Boost Bitmap
  Bitmap of TBT performance boost enabled PCIe controllers to which discrete TBT controllers
  connect. Bit0: PXPA, Bit1: PXPB, Bit2: PXPC, Bit3: PXPD, Bit4: PXPE
**/
  UINT8                       PcieTbtPerfBoost;

/** Offset 0x0DE4 - Serial IO SPI CLK Pin Muxing
  Select SerialIo LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK*
  for possible values.
**/
  UINT32                      SerialIoLpssSpiClkPinMux[7];

/** Offset 0x0E00 - Serial IO SPI CS Pin Muxing
  Select SerialIo  LPSS SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS*
  for possible values.
**/
  UINT32                      SerialIoLpssSpiCsPinMux[14];

/** Offset 0x0E38 - SPIn Device Mode
  Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
  modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden
**/
  UINT8                       SerialIoLpssSpiMode[7];

/** Offset 0x0E3F
**/
  UINT8                       FspsUpdRsvd8;

/** Offset 0x0E40 - LPSS SPI MOSI Pin Muxing
  Select LPSS SPI MOSI pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MOSI* for possible values.
**/
  UINT32                      SerialIoLpssSpiMosiPinMux[7];

/** Offset 0x0E5C - LPSS SPI MISO Pin Muxing
  Select Lpss SPI MISO pin muxing. Refer to GPIO_*_MUXING_LPSS_SPIx_MISO* for possible values.
**/
  UINT32                      SerialIoLpssSpiMisoPinMux[7];

/** Offset 0x0E78 - SPI<N> Chip Select Polarity
  Sets polarity for each chip Select. Available options: 0:LpssSpiCsActiveLow, 1:LpssSpiCsActiveHigh
**/
  UINT8                       SerialIoLpssSpiCsPolarity[14];

/** Offset 0x0E86 - SPI<N> Chip Select Enable
  0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled
**/
  UINT8                       SerialIoLpssSpiCsEnable[14];

/** Offset 0x0E94 - SPIn Default Chip Select Mode HW/SW
  Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
  SPI1, ... Available options: 0:HW, 1:SW
**/
  UINT8                       SerialIoLpssSpiCsMode[7];

/** Offset 0x0E9B - SPIn Default Chip Select State Low/High
  Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
  Available options: 0:Low, 1:High
**/
  UINT8                       SerialIoLpssSpiCsState[7];

/** Offset 0x0EA2 - UARTn Device Mode
  Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
  modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
  4:SerialIoUartSkipInit
**/
  UINT8                       SerialIoUartMode[7];

/** Offset 0x0EA9
**/
  UINT8                       FspsUpdRsvd9[3];

/** Offset 0x0EAC - Default BaudRate for each Serial IO UART
  Set default BaudRate Supported from 0 - default to 6000000
**/
  UINT32                      SerialIoUartBaudRate[7];

/** Offset 0x0EC8 - Default ParityType for each Serial IO UART
  Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
  UINT8                       SerialIoUartParity[7];

/** Offset 0x0ECF - Default DataBits for each Serial IO UART
  Set default word length. 0: Default, 5,6,7,8
**/
  UINT8                       SerialIoUartDataBits[7];

/** Offset 0x0ED6 - Default StopBits for each Serial IO UART
  Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
  TwoStopBits
**/
  UINT8                       SerialIoUartStopBits[7];

/** Offset 0x0EDD - Power Gating mode for each Serial IO UART that works in COM mode
  Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
**/
  UINT8                       SerialIoUartPowerGating[7];

/** Offset 0x0EE4 - Enable Dma for each Serial IO UART that supports it
  Set DMA/PIO mode. 0: Disabled, 1: Enabled
**/
  UINT8                       SerialIoUartDmaEnable[7];

/** Offset 0x0EEB - Enables UART hardware flow control, CTS and RTS lines
  Enables UART hardware flow control, CTS and RTS lines.
**/
  UINT8                       SerialIoUartAutoFlow[7];

/** Offset 0x0EF2
**/
  UINT8                       FspsUpdRsvd10[2];

/** Offset 0x0EF4 - SerialIoUartRtsPinMuxPolicy
  Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
  for possible values.
**/
  UINT32                      SerialIoUartRtsPinMuxPolicy[7];

/** Offset 0x0F10 - SerialIoUartRxPinMuxPolicy
  Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
  possible values.
**/
  UINT32                      SerialIoUartRxPinMuxPolicy[7];

/** Offset 0x0F2C - SerialIoUartTxPinMuxPolicy
  Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
  possible values.
**/
  UINT32                      SerialIoUartTxPinMuxPolicy[7];

/** Offset 0x0F48 - Serial IO UART DBG2 table
  Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
  1: Enable.
**/
  UINT8                       SerialIoUartDbg2[7];

/** Offset 0x0F4F - Serial IO UART PG DBG2 table
  Enable or disable Serial Io UART PG DBG2 table, default is Disable; <b>0: Disable;</b>
  1: Enable.
**/
  UINT8                       SerialIoUartPgDbg2[7];

/** Offset 0x0F56 - I2Cn Device Mode
  Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
  modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
**/
  UINT8                       SerialIoI2cMode[8];

/** Offset 0x0F5E
**/
  UINT8                       FspsUpdRsvd11[2];

/** Offset 0x0F60 - Serial IO I2C SDA Pin Muxing
  Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
  possible values.
**/
  UINT32                      PchSerialIoI2cSdaPinMux[8];

/** Offset 0x0F80 - Serial IO I2C SCL Pin Muxing
  Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
  possible values.
**/
  UINT32                      PchSerialIoI2cSclPinMux[8];

/** Offset 0x0FA0 - PCH SerialIo I2C Pads Termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
  respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
**/
  UINT8                       PchSerialIoI2cPadsTermination[8];

/** Offset 0x0FA8 - I3C Device Mode
  Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
  2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
**/
  UINT8                       SerialIoI3cMode[3];

/** Offset 0x0FAB
**/
  UINT8                       FspsUpdRsvd12;

/** Offset 0x0FAC - Serial IO I3C SDA Pin Muxing
  Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for
  possible values.
**/
  UINT32                      SerialIoI3cSdaPinMux[3];

/** Offset 0x0FB8 - Serial IO I3C SDA Pad Termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
  UINT8                       SerialIoI3cSdaPadTermination[3];

/** Offset 0x0FBB
**/
  UINT8                       FspsUpdRsvd13;

/** Offset 0x0FBC - Serial IO I3C SCL Pin Muxing
  Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for
  possible values.
**/
  UINT32                      SerialIoI3cSclPinMux[3];

/** Offset 0x0FC8 - Serial IO I3C SCL Pad Termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
  UINT8                       SerialIoI3cSclPadTermination[3];

/** Offset 0x0FCB
**/
  UINT8                       FspsUpdRsvd14;

/** Offset 0x0FCC - Serial IO I3C SCL FB Pin Muxing
  Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB*
  for possible values.
**/
  UINT32                      SerialIoI3cSclFbPinMux[3];

/** Offset 0x0FD8 - Serial IO I3C SCL FB Pad Termination
  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
  respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
  UINT8                       SerialIoI3cSclFbPadTermination[3];

/** Offset 0x0FDB - Enable VMD controller
  Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
  $EN_DIS
**/
  UINT8                       VmdEnable;

/** Offset 0x0FDC - Enable VMD Global Mapping
  Enable/disable to VMD controller.0: Disable(Default); 1: Enable
  $EN_DIS
**/
  UINT8                       VmdGlobalMapping;

/** Offset 0x0FDD - Map port under VMD
  Map/UnMap port under VMD
  $EN_DIS
**/
  UINT8                       VmdPort[31];

/** Offset 0x0FFC - VMD Port Bus
  VMD Root port bus number.
**/
  UINT8                       VmdPortBus[31];

/** Offset 0x101B - VMD Port Device
  VMD Root port device number.
**/
  UINT8                       VmdPortDev[31];

/** Offset 0x103A - VMD Port Func
  VMD Root port function number.
**/
  UINT8                       VmdPortFunc[31];

/** Offset 0x1059
**/
  UINT8                       FspsUpdRsvd37[7];

/** Offset 0x1060 - VMD Variable
  VMD Variable Pointer.
**/
  UINT64                      VmdVariablePtr;

/** Offset 0x1068 - Temporary CfgBar address for VMD
  VMD Variable Pointer.
**/
  UINT32                      VmdCfgBarBase;

/** Offset 0x106C - Temporary MemBar1 address for VMD
  VMD Variable Pointer.
**/
  UINT32                      VmdMemBar1Base;

/** Offset 0x1070 - Temporary MemBar2 address for VMD
  VMD Variable Pointer.
**/
  UINT32                      VmdMemBar2Base;

/** Offset 0x1074 - Enable D3 Hot in TCSS
  This policy will enable/disable D3 hot support in IOM
  $EN_DIS
**/
  UINT8                       D3HotEnable;

/** Offset 0x1075 - TCSS TBT Performance Boost Bitmap
  Bitmap of TBT performance boost enabled TCSS PCIe root ports. Bit0: TCSS port0,
  Bit1: TCSS port1, Bit2: TCSS port2, Bit3: TCSS port3
**/
  UINT8                       TcssTbtPerfBoost;

/** Offset 0x1076
**/
  UINT8                       FspsUpdRsvd15[2];

/** Offset 0x1078 - TypeC port GPIO setting
  GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
  in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl
  = LunarLake)
**/
  UINT32                      IomTypeCPortPadCfg[12];

/** Offset 0x10A8 - CPU USB3 Port Over Current Pin
  Describe the specific over current pin number of USBC Port N.
**/
  UINT8                       CpuUsb3OverCurrentPin[10];

/** Offset 0x10B2 - CPU USB3 Port Over Current Pin
  Describe the specific over current pin number of USBC Port N.
**/
  UINT8                       CpuUsb3OverCurrentPinType[10];

/** Offset 0x10BC - Enable D3 Cold in TCSS
  This policy will enable/disable D3 cold support in IOM
  $EN_DIS
**/
  UINT8                       D3ColdEnable;

/** Offset 0x10BD - TC State in TCSS
  This TC C-State Limit in IOM
**/
  UINT8                       TcCstateLimit;

/** Offset 0x10BE - TC Notify Igd
  Tc Notify Igd
**/
  UINT8                       TcNotifyIgd;

/** Offset 0x10BF - TCSS CPU USB PDO Programming
  Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
  for programming during later phase. 1: enable, 0: disable
  $EN_DIS
**/
  UINT8                       TcssCpuUsbPdoProgramming;

/** Offset 0x10C0 - Enable/Disable PMC-PD Solution
  This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
  $EN_DIS
**/
  UINT8                       PmcPdEnable;

/** Offset 0x10C1
**/
  UINT8                       FspsUpdRsvd16;

/** Offset 0x10C2 - TCSS Aux Orientation Override Enable
  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
  UINT16                      TcssAuxOri;

/** Offset 0x10C4 - TCSS HSL Orientation Override Enable
  Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
  UINT16                      TcssHslOri;

/** Offset 0x10C6 - TCSS USB Port Enable
  Bits 0, 1, ... max Type C port control enables
**/
  UINT8                       UsbTcPortEn;

/** Offset 0x10C7 - VCCST request for IOM
  This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
  $EN_DIS
**/
  UINT8                       VccSt;

/** Offset 0x10C8 - Enable/Disable PTM
  This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
  $EN_DIS
**/
  UINT8                       PtmEnabled[4];

/** Offset 0x10CC - PCIE RP Ltr Enable
  Latency Tolerance Reporting Mechanism.
**/
  UINT8                       SaPcieItbtRpLtrEnable[4];

/** Offset 0x10D0 - PCIE RP Snoop Latency Override Mode
  Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
  UINT8                       SaPcieItbtRpSnoopLatencyOverrideMode[4];

/** Offset 0x10D4 - PCIE RP Snoop Latency Override Multiplier
  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
  UINT8                       SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];

/** Offset 0x10D8 - PCIE RP Snoop Latency Override Value
  Latency Tolerance Reporting, Snoop Latency Override Value.
**/
  UINT16                      SaPcieItbtRpSnoopLatencyOverrideValue[4];

/** Offset 0x10E0 - PCIE RP Non Snoop Latency Override Mode
  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
  UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMode[4];

/** Offset 0x10E4 - PCIE RP Non Snoop Latency Override Multiplier
  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
  UINT8                       SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];

/** Offset 0x10E8 - PCIE RP Non Snoop Latency Override Value
  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
  UINT16                      SaPcieItbtRpNonSnoopLatencyOverrideValue[4];

/** Offset 0x10F0 - Force LTR Override
  Force LTR Override.
**/
  UINT8                       SaPcieItbtRpForceLtrOverride[4];

/** Offset 0x10F4 - PCIE RP Ltr Config Lock
  0: Disable; 1: Enable.
**/
  UINT8                       SaPcieItbtRpLtrConfigLock[4];

/** Offset 0x10F8 - Type C Port x Convert to TypeA
  Enable / Disable(default) Type C Port x Convert to TypeA
  $EN_DIS
**/
  UINT8                       EnableTcssCovTypeA[4];

/** Offset 0x10FC - Touch Host Controller Assignment
  Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
**/
  UINT8                       ThcAssignment[2];

/** Offset 0x10FE - Touch Host Controller Interrupt Pin Mux
  Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
  for possible values.
**/
  UINT8                       ThcInterruptPinMuxing[8];

/** Offset 0x1106 - Touch Host Controller Mode
  Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
**/
  UINT8                       ThcMode[2];

/** Offset 0x1108 - Touch Host Controller Wake On Touch
  Based on this setting vGPIO for given THC will be in native mode, and additional
  _CRS for wake will be exposed in ACPI
**/
  UINT8                       ThcWakeOnTouch[2];

/** Offset 0x110A
**/
  UINT8                       UnusedUpdSpace4[2];

/** Offset 0x110C - Touch Host Controller Active Ltr
  Expose Active Ltr for OS driver to set
**/
  UINT32                      ThcActiveLtr[2];

/** Offset 0x1114 - Touch Host Controller Idle Ltr
  Expose Idle Ltr for OS driver to set
**/
  UINT32                      ThcIdleLtr[2];

/** Offset 0x111C - Touch Host Controller Timestamp timer behavior in D0i2
  Timestamp timer behavior in D0i2. 1 = Timer resets to 0 when entering D0i2 0 = Timer
  is paused instead of reset to 0 when entering D0i2
**/
  UINT8                       TimestampTimerMode[2];

/** Offset 0x111E
**/
  UINT8                       FspsUpdRsvd17[2];

/** Offset 0x1120 - Touch Host Controller Display Frame Sync Period
  Period of the emulated display frame sync [ms] The minimum period is 2ms, maximum
  period is 100ms
**/
  UINT32                      DisplayFrameSyncPeriod[2];

/** Offset 0x1128 - Touch Host Controller ResetPad
  ResetPad
**/
  UINT32                      ThcResetPad[2];

/** Offset 0x1130 - Touch Host Controller ResetPad Trigger
  Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
**/
  UINT32                      ThcResetPadTrigger[2];

/** Offset 0x1138 - Touch Host Controller DYSync
  Based on this setting GPIO for given THC will be in native mode
**/
  UINT8                       ThcDsyncPad[2];

/** Offset 0x113A
**/
  UINT8                       FspsUpdRsvd18[2];

/** Offset 0x113C - Touch Host Controller Hid Over Spi Connection Speed
  Hid Over Spi Connection Speed - SPI Frequency
**/
  UINT32                      ThcHidSpiConnectionSpeed[2];

/** Offset 0x1144 - Touch Host Controller Hid Over Spi Limit PacketSize
  When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
  packet size for SPI Read and Write 0x0- Max Soc Packet Size,  0x11 - 64 Bytes
**/
  UINT32                      ThcHidSpiLimitPacketSize[2];

/** Offset 0x114C - Touch Host Controller Hid Over Spi Limit PacketSize
  Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
  and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
  1-65535 (0xFFFF) - up to 655350 us
**/
  UINT32                      ThcPerformanceLimitation[2];

/** Offset 0x1154 - Touch Host Controller Hid Over Spi Input Report Header Address
  Hid Over Spi Input Report Header Address
**/
  UINT32                      ThcHidSpiInputReportHeaderAddress[2];

/** Offset 0x115C - Touch Host Controller Hid Over Spi Input Report Body Address
  Hid Over Spi Input Report Body Address
**/
  UINT32                      ThcHidSpiInputReportBodyAddress[2];

/** Offset 0x1164 - Touch Host Controller Hid Over Spi Output Report Address
  Hid Over Spi Output Report Address
**/
  UINT32                      ThcHidSpiOutputReportAddress[2];

/** Offset 0x116C - Touch Host Controller Hid Over Spi Read Opcode
  Hid Over Spi Read Opcode
**/
  UINT32                      ThcHidSpiReadOpcode[2];

/** Offset 0x1174 - Touch Host Controller Hid Over Spi Write Opcode
  Hid Over Spi Write Opcode
**/
  UINT32                      ThcHidSpiWriteOpcode[2];

/** Offset 0x117C - Touch Host Controller Hid Over Spi Flags
  Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
**/
  UINT32                      ThcHidSpiFlags[2];

/** Offset 0x1184 - Touch Host Controller Reset Sequencing Delay [ms]
  Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
**/
  UINT16                      ThcResetSequencingDelay[2];

/** Offset 0x1188 - Touch Host Controller Hid Over I2c Device Address
  Hid Over I2c Device Address
**/
  UINT32                      ThcHidI2cDeviceAddress[2];

/** Offset 0x1190 - Touch Host Controller Hid Over I2c Connection Speed
  Hid Over I2c Connection Speed [Hz]
**/
  UINT32                      ThcHidI2cConnectionSpeed[2];

/** Offset 0x1198 - Touch Host Controller Hid Over I2c Addressing Mode
  Hid Over I2c Addressing Mode - 0x1: The connection uses 10-bit addressing. 0x0:
  The connection uses 7-bit addressing.
**/
  UINT8                       ThcHidI2cAddressingMode[2];

/** Offset 0x119A
**/
  UINT8                       FspsUpdRsvd19[2];

/** Offset 0x119C - Touch Host Controller Hid Over I2c Device Descriptor Address
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cDeviceDescriptorAddress[2];

/** Offset 0x11A4 - Touch Host Controller Hid Over I2c Serial Clock Line High Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cStandardModeSerialClockLineHighPeriod[2];

/** Offset 0x11AC - Touch Host Controller Hid Over I2c Standard Mode Serial Clock Line Low Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cStandardModeSerialClockLineLowPeriod[2];

/** Offset 0x11B4 - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Transmit Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cStandardModeSerialDataLineTransmitHoldPeriod[2];

/** Offset 0x11BC - Touch Host Controller Hid Over I2c Standard Mode Serial Data Line Receive Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cStandardModeSerialDataLineReceiveHoldPeriod[2];

/** Offset 0x11C4 - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line High Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModeSerialClockLineHighPeriod[2];

/** Offset 0x11CC - Touch Host Controller Hid Over I2c Fast Mode Serial Clock Line Low Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModeSerialClockLineLowPeriod[2];

/** Offset 0x11D4 - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Transmit Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModeSerialDataLineTransmitHoldPeriod[2];

/** Offset 0x11DC - Touch Host Controller Hid Over I2c Fast Mode Serial Data Line Receive Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModeSerialDataLineReceiveHoldPeriod[2];

/** Offset 0x11E4 - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In Std Mode Fast Mode And Fast Mode Plus
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cMaxSuppressedSpikesSMFMFMP[2];

/** Offset 0x11EC - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line High Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModePlusSerialClockLineHighPeriod[2];

/** Offset 0x11F4 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Clock Line Low Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModePlusSerialClockLineLowPeriod[2];

/** Offset 0x11FC - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Transmit Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModePlusSerialDataLineTransmitHoldPeriod[2];

/** Offset 0x1204 - Touch Host Controller Hid Over I2c Fast Mode Plus Serial Data Line Receive Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cFastModePlusSerialDataLineReceiveHoldPeriod[2];

/** Offset 0x120C - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line High Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineHighPeriod[2];

/** Offset 0x1214 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Clock Line Low Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cHighSpeedModePlusSerialClockLineLowPeriod[2];

/** Offset 0x121C - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Transmit Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineTransmitHoldPeriod[2];

/** Offset 0x1224 - Touch Host Controller Hid Over I2c High Speed Mode Plus Serial Data Line Receive Hold Period
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cHighSpeedModePlusSerialDataLineReceiveHoldPeriod[2];

/** Offset 0x122C - Touch Host Controller Hid Over I2c Maximum Length Of Suppressed Spikes In High Speed Mode
  Hid Over I2c Device Descriptor Address
**/
  UINT32                      ThcHidI2cMaximumLengthOfSuppressedSpikesInHighSpeedMode[2];

/** Offset 0x1234 - THC Wake On Touch GPIO resource Edge or Level
  Definition of GPIO resource configuration of Edge or Level
**/
  UINT8                       ThcWotEdgeLevel[2];

/** Offset 0x1236 - THC Wake On Touch GPIO resource of Active Level
  Definition of GPIO resource configuration of Active Level
**/
  UINT8                       ThcWotActiveLevel[2];

/** Offset 0x1238 - THC Wake On Touch GPIO resource of pin configuration
  Definition of GPIO resource configuration of pin configuration
**/
  UINT8                       ThcWotPinConfig[2];

/** Offset 0x123A - THC customized SubSytem ID for Port
  Definition of GPIO resource configuration of pin configuration
**/
  UINT16                      ThcCustomizedSsid[2];

/** Offset 0x123E - THC Sets Customized SubSytem Vendor ID for Port
  Definition of GPIO resource configuration of pin configuration
**/
  UINT16                      ThcCustomizedSvid[2];

/** Offset 0x1242
**/
  UINT8                       FspsUpdRsvd38[2];

/** Offset 0x1244 - USB 3.1 Speed Selection
  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
**/
  UINT32                      Usb31PortSpeed;

/** Offset 0x1248 - Touch Host Controller Hid Over I2c Maximum Frame Size Enable
  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
**/
  UINT8                       ThcHidI2cMaxFrameSize[2];

/** Offset 0x124A - Touch Host Controller Hid Over I2c Maximum Frame Size Value
  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
**/
  UINT16                      ThcHidI2cMaxFrameSizeValue[2];

/** Offset 0x124E - Touch Host Controller Hid Over I2c Interrupt Delay Enable
  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
**/
  UINT8                       ThcHidI2cIntDelay[2];

/** Offset 0x1250 - Touch Host Controller Hid Over I2c Interrupt Delay Value
  Choose USB 3.1 Port Speed Selection. Each bit represents a port. 1: Gen1, 0: Gen2
**/
  UINT16                      ThcHidI2cIntDelayValue[2];

/** Offset 0x1254 - PchPostMemRsvd
  Reserved for PCH Post-Mem
  $EN_DIS
**/
  UINT8                       PchPostMemRsvd[9];

/** Offset 0x125D - PCHHOT# pin
  Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
  $EN_DIS
**/
  UINT8                       PchHotEnable;

/** Offset 0x125E - Thermal Throttling Custimized T0Level Value
  Custimized T0Level value.
**/
  UINT16                      PchT0Level;

/** Offset 0x1260 - Thermal Throttling Custimized T1Level Value
  Custimized T1Level value.
**/
  UINT16                      PchT1Level;

/** Offset 0x1262 - Thermal Throttling Custimized T2Level Value
  Custimized T2Level value.
**/
  UINT16                      PchT2Level;

/** Offset 0x1264 - Enable The Thermal Throttle
  Enable the thermal throttle function.
  $EN_DIS
**/
  UINT8                       PchTTEnable;

/** Offset 0x1265 - PMSync State 13
  When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
  at least T2 state.
  $EN_DIS
**/
  UINT8                       PchTTState13Enable;

/** Offset 0x1266 - Thermal Throttle Lock
  Thermal Throttle Lock.
  $EN_DIS
**/
  UINT8                       PchTTLock;

/** Offset 0x1267 - Thermal Throttling Suggested Setting
  Thermal Throttling Suggested Setting.
  $EN_DIS
**/
  UINT8                       TTSuggestedSetting;

/** Offset 0x1268 - Thermal Device Temperature
  Decides the temperature.
**/
  UINT16                      PchTemperatureHotLevel;

/** Offset 0x126A - Enable PCH TSN
  Enable/disable TSN on the PCH.
  $EN_DIS
**/
  UINT8                       PchTsnEnable[4];

/** Offset 0x126E
**/
  UINT16                      FspsUpdRsvd20;

/** Offset 0x1270 - PCH TSN MAC Address High Bits
  Set TSN MAC Address High.
**/
  UINT32                      PchTsn1MacAddressHigh;

/** Offset 0x1274 - PCH TSN MAC Address Low Bits
  Set TSN MAC Address Low.
**/
  UINT32                      PchTsn1MacAddressLow;

/** Offset 0x1278 - PCH TSN2 MAC Address High Bits
  Set TSN2 MAC Address High.
**/
  UINT32                      PchTsn2MacAddressHigh;

/** Offset 0x127C - PCH TSN2 MAC Address Low Bits
  Set TSN2 MAC Address Low.
**/
  UINT32                      PchTsn2MacAddressLow;

/** Offset 0x1280 - PCH TSN3 MAC Address High Bits
  Set TSN3 MAC Address High.
**/
  UINT32                      PchTsn3MacAddressHigh;

/** Offset 0x1284 - PCH TSN3 MAC Address Low Bits
  Set TSN3 MAC Address Low.
**/
  UINT32                      PchTsn3MacAddressLow;

/** Offset 0x1288 - PCH TSN4 MAC Address High Bits
  Set TSN4 MAC Address High.
**/
  UINT32                      PchTsn4MacAddressHigh;

/** Offset 0x128C - PCH TSN MAC4 Address Low Bits
  Set TSN MAC4 Address Low.
**/
  UINT32                      PchTsn4MacAddressLow;

/** Offset 0x1290 - Enable USB2 ports
  Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
  port1, and so on.
**/
  UINT8                       PortUsb20Enable[16];

/** Offset 0x12A0 - Enable USB2 SW Device Mode
  Enable/disable SW device mode per USB2 ports. One byte for each port, byte0 for
  port0, byte1 for port1, and so on.
**/
  UINT8                       PortUsb20SwDeviceModeEnable[16];

/** Offset 0x12B0 - USB3 compatible port
  For the USB2 port, whether it also can be used as USB3 port. 0: no; 1: yes.
**/
  UINT8                       Usb3CompatiblePort[16];

/** Offset 0x12C0 - USB3 port number of compatible port
  USB3 port number if the USB2 port can be used as USB3. 0: port1; 1: port2; 2: port3.
  Usb3CompatiblePort=1 is  the premise.
**/
  UINT8                       Usb3CompatiblePortNum[16];

/** Offset 0x12D0 - Multi-VC for PCIE RP Mask
  Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each port, bit0 for port1, bit1 for port2, and so on.
**/
  UINT8                       PchPcieRpMultiVcEnabled[28];

/** Offset 0x12EC - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PchPcieVc1TcMap[28];

/** Offset 0x1308 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc1Map[28];

/** Offset 0x1324 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc2Map[28];

/** Offset 0x1340 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc3Map[28];

/** Offset 0x135C - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc4Map[28];

/** Offset 0x1378 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc5Map[28];

/** Offset 0x1394 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc6Map[28];

/** Offset 0x13B0 - Multi-VC for PCIE RP VC1 TC Mapping
  Map Virtual Channel1 to Traffic Class for PCIE Root Ports. 0: disable, 1: enable.
  One bit for each TC, bit0 for TC1, bit1 for TC2, and so on.
**/
  UINT8                       PcieRootPortMvcTc7Map[28];

/** Offset 0x13CC - Enable USB3 ports
  Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
  port1, and so on.
**/
  UINT8                       PortUsb30Enable[10];

/** Offset 0x13D6 - USB 3.1 Speed Selection
  Choose USB 3.1 Speed Selection. 1: Gen1, 0: Gen2
  $EN_DIS
**/
  UINT8                       PortUsb31Speed;

/** Offset 0x13D7 - Enable xDCI controller
  Enable/disable to xDCI controller.
  $EN_DIS
**/
  UINT8                       XdciEnable;

/** Offset 0x13D8 - USB PDO Programming
  Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
  during later phase. 1: enable, 0: disable
  $EN_DIS
**/
  UINT8                       UsbPdoProgramming;

/** Offset 0x13D9 - USB Audio Offload enable
  Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
  $EN_DIS
**/
  UINT8                       PchXhciUaolEnable;

/** Offset 0x13DA - PCH USB OverCurrent mapping enable
  1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
  mapping allow for NOA usage of OC pins
  $EN_DIS
**/
  UINT8                       PchUsbOverCurrentEnable;

/** Offset 0x13DB - USB2 Port Over Current Pin
  Describe the specific over current pin number of USB 2.0 Port N.
**/
  UINT8                       Usb2OverCurrentPin[16];

/** Offset 0x13EB - USB3 Port Over Current Pin
  Describe the specific over current pin number of USB 3.0 Port N.
**/
  UINT8                       Usb3OverCurrentPin[10];

/** Offset 0x13F5 - USB3 Port Over Current Pin
  Describe the specific over current pin type of USB 2.0 USB 3.0 Port N.
**/
  UINT8                       UsbOverCurrentPinType[16];

/** Offset 0x1405 - Enable xHCI LTR override
  Enables override of recommended LTR values for xHCI
  $EN_DIS
**/
  UINT8                       PchUsbLtrOverrideEnable;

/** Offset 0x1406 - USB DWB enable
  Enable/Disable USB DWB. 0: disabled, 1: enabled (default)
  $EN_DIS
**/
  UINT8                       PchXhciDwbEnable;

/** Offset 0x1407
**/
  UINT8                       FspsUpdRsvd21[2];

/** Offset 0x1409
**/
  UINT8                       UnusedUpdSpace5[3];

/** Offset 0x140C - xHCI High Idle Time LTR override
  Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
  UINT32                      PchUsbLtrHighIdleTimeOverride;

/** Offset 0x1410 - xHCI Medium Idle Time LTR override
  Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
  UINT32                      PchUsbLtrMediumIdleTimeOverride;

/** Offset 0x1414 - xHCI Low Idle Time LTR override
  Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
  UINT32                      PchUsbLtrLowIdleTimeOverride;

/** Offset 0x1418 - USB2 Port Reset Message Enable
  0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
  be enable for USB2 Port those are paired with CPU XHCI Port
**/
  UINT8                       PortResetMessageEnable[16];

/** Offset 0x1428 - PCH USB OverCurrent mapping lock enable
  If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
  that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
  $EN_DIS
**/
  UINT8                       PchXhciOcLock;

/** Offset 0x1429 - USB Per Port HS Preemphasis Bias
  USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
**/
  UINT8                       Usb2PhyPetxiset[16];

/** Offset 0x1439 - USB Per Port HS Transmitter Bias
  USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
**/
  UINT8                       Usb2PhyTxiset[16];

/** Offset 0x1449 - USB Per Port HS Transmitter Emphasis
  USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
  10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
**/
  UINT8                       Usb2PhyPredeemp[16];

/** Offset 0x1459 - USB Per Port Half Bit Pre-emphasis
  USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
  One byte for each port.
**/
  UINT8                       Usb2PhyPehalfbit[16];

/** Offset 0x1469 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
  Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
  in arrary can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxDeEmphEnable[10];

/** Offset 0x1473 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
  USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
  <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
**/
  UINT8                       Usb3HsioTxDeEmph[10];

/** Offset 0x147D - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
  Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
  in arrary can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxDownscaleAmpEnable[10];

/** Offset 0x1487 - USB 3.0 TX Output Downscale Amplitude Adjustment
  USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
  = 00h</b>. One byte for each port.
**/
  UINT8                       Usb3HsioTxDownscaleAmp[10];

/** Offset 0x1491
**/
  UINT8                       PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];

/** Offset 0x149B
**/
  UINT8                       PchUsb3HsioFilterSelNEnable[10];

/** Offset 0x14A5
**/
  UINT8                       PchUsb3HsioFilterSelPEnable[10];

/** Offset 0x14AF
**/
  UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];

/** Offset 0x14B9
**/
  UINT8                       PchUsb3HsioCtrlAdaptOffsetCfg[10];

/** Offset 0x14C3
**/
  UINT8                       PchUsb3HsioOlfpsCfgPullUpDwnRes[10];

/** Offset 0x14CD
**/
  UINT8                       PchUsb3HsioFilterSelN[10];

/** Offset 0x14D7
**/
  UINT8                       PchUsb3HsioFilterSelP[10];

/** Offset 0x14E1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
  value in array can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate3UniqTranEnable[10];

/** Offset 0x14EB - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
  USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
  = 4Ch</b>. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate3UniqTran[10];

/** Offset 0x14F5 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
  value in array can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate2UniqTranEnable[10];

/** Offset 0x14FF - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
  USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
  <b>Default = 4Ch</b>. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate2UniqTran[10];

/** Offset 0x1509 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
  value in array can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate1UniqTranEnable[10];

/** Offset 0x1513 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
  USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
  <b>Default = 4Ch</b>. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate1UniqTran[10];

/** Offset 0x151D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
  Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
  value in array can be between 0-1. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate0UniqTranEnable[10];

/** Offset 0x1527 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
  USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
  <b>Default = 4Ch</b>. One byte for each port.
**/
  UINT8                       Usb3HsioTxRate0UniqTran[10];

/** Offset 0x1531 - PCIe Fia Programming
  Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
  $EN_DIS
**/
  UINT8                       PcieFiaProgramming;

/** Offset 0x1532 - Enable SSE Device
  Test, 0: POR, 1: enable, 2: disable, Enable/Disable SSE/SSE++ Devices from PCI config space
  $EN_DIS
**/
  UINT8                       SseCommunication;

/** Offset 0x1533 - MePostMemRestrictedRsvd
  Reserved for ME Post-Mem Restricted
  $EN_DIS
**/
  UINT8                       MePostMemRestrictedRsvd[2];

/** Offset 0x1535 - Enable/Disable NPU Device
  Enable(Default): Enable NPU Device, Disable: Disable NPU Device
  $EN_DIS
**/
  UINT8                       NpuEnable;

/** Offset 0x1536 - Enable LAN
  Enable/disable LAN controller.
  $EN_DIS
**/
  UINT8                       PchLanEnable;

/** Offset 0x1537 - Enable PCH Lan LTR capabilty of PCH internal LAN
  0: Disable; 1: Enable.
  $EN_DIS
**/
  UINT8                       PchLanLtrEnable;

/** Offset 0x1538 - PCH Lan WOL Fast Support
  Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
  $EN_DIS
**/
  UINT8                       PchLanWOLFastSupport;

/** Offset 0x1539 - Skip Ssid Programming.
  When set to TRUE, silicon code will not do any SSID programming and platform code
  needs to handle that by itself properly.
  $EN_DIS
**/
  UINT8                       SiSkipSsidProgramming;

/** Offset 0x153A - Change Default SVID
  Change the default SVID used in FSP to programming internal devices. This is only
  valid when SkipSsidProgramming is FALSE.
**/
  UINT16                      SiCustomizedSvid;

/** Offset 0x153C - Change Default SSID
  Change the default SSID used in FSP to programming internal devices. This is only
  valid when SkipSsidProgramming is FALSE.
**/
  UINT16                      SiCustomizedSsid;

/** Offset 0x153E - CAN Configurations
  Enable/Disable CAN Controllers.0: Disable, <b>1: Enable</b>
  $EN_DIS
**/
  UINT8                       PchCanEnable[2];

/** Offset 0x1540
**/
  UINT8                       FspsUpdRsvd22[4];

/** Offset 0x1544
**/
  UINT8                       UnusedUpdSpace6[4];

/** Offset 0x1548 - SVID SDID table Poniter.
  The address of the table of SVID SDID to customize each SVID SDID entry. This is
  only valid when SkipSsidProgramming is FALSE.
**/
  UINT64                      SiSsidTablePtr;

/** Offset 0x1550 - Number of ssid table.
  SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
  This is only valid when SkipSsidProgramming is FALSE.
**/
  UINT16                      SiNumberOfSsidTableEntry;

/** Offset 0x1552 - Skip DFX.
  Skip DFX.
  $EN_DIS
**/
  UINT8                       DfxSkipBiosDone;

/** Offset 0x1553 - SiPostMemRsvd
  Reserved for SI Post-Mem
  $EN_DIS
**/
  UINT8                       SiPostMemRsvd[6];

/** Offset 0x1559
**/
  UINT8                       FspsUpdRsvd23[3];

/** Offset 0x155C - LogoPixelHeight Address
  Address of LogoPixelHeight
**/
  UINT32                      LogoPixelHeight;

/** Offset 0x1560 - LogoPixelWidth Address
  Address of LogoPixelWidth
**/
  UINT32                      LogoPixelWidth;

/** Offset 0x1564
**/
  UINT8                       FspsUpdRsvd24[4];

/** Offset 0x1568 - Blt Buffer Address
  Address of Blt buffer
**/
  UINT64                      BltBufferAddress;

/** Offset 0x1570 - Graphics Configuration Ptr
  Points to VBT
**/
  UINT64                      GraphicsConfigPtr;

/** Offset 0x1578 - Enable/Disable SkipFspGop
  Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
  $EN_DIS
**/
  UINT8                       SkipFspGop;

/** Offset 0x1579 - Enable/Disable Media Configuration
  Enable(Default): Configure Media for use, Disable: Skip Media Configuration
  $EN_DIS
**/
  UINT8                       ConfigureMedia;

/** Offset 0x157A - Enable/Disable IGFX RenderStandby
  Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
  $EN_DIS
**/
  UINT8                       RenderStandby;

/** Offset 0x157B - Enable/Disable GT Configuration
  Enable(Default): Configure GT for use, Disable: Skip GT Configuration
  $EN_DIS
**/
  UINT8                       ConfigureGT;

/** Offset 0x157C - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
  0(Default)=Disable, 1=Enable
  $EN_DIS
**/
  UINT8                       RC1pGtFreqEnable;

/** Offset 0x157D - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
  0(Default)=Disable, 1=Enable
  $EN_DIS
**/
  UINT8                       RC1pMediaFreqEnable;

/** Offset 0x157E - Enable/Disable PavpEnable
  Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
  $EN_DIS
**/
  UINT8                       PavpEnable;

/** Offset 0x157F - Enable/Disable PeiGraphicsPeimInit
  <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
  Disable: FSP will NOT initialize the framebuffer.
  $EN_DIS
**/
  UINT8                       PeiGraphicsPeimInit;

/** Offset 0x1580 - Enable/Disable IGFX Media Standby
  Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby
  $EN_DIS
**/
  UINT8                       MediaStandby;

/** Offset 0x1581 - Enable/Disable Gfx Workstation
  Enable(Default): Is a workstation, Disable: Is not a workstation
  $EN_DIS
**/
  UINT8                       Dev2IsGfxWorkstation;

/** Offset 0x1582
**/
  UINT8                       FspsUpdRsvd25[2];

/** Offset 0x1584 - Intel Graphics VBT (Video BIOS Table) Size
  Size of Internal Graphics VBT Image
**/
  UINT32                      VbtSize;

/** Offset 0x1588 - Platform LID Status for LFP Displays.
  LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
  0: LidClosed, 1: LidOpen
**/
  UINT8                       LidStatus;

/** Offset 0x1589 - Select MaxActiveDisplays
  Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
  is 2 displays only
**/
  UINT8                       MaxActiveDisplays;

/** Offset 0x158A
**/
  UINT8                       FspsUpdRsvd26[2];

/** Offset 0x158C - HorizontalResolution for PEI Logo
  HorizontalResolution from PEIm Gfx for PEI Logo
**/
  UINT32                      HorizontalResolution;

/** Offset 0x1590 - VerticalResolution for PEI Logo
  VerticalResolution from PEIm Gfx for PEI Logo
**/
  UINT32                      VerticalResolution;

/** Offset 0x1594
**/
  UINT8                       FspsUpdRsvd388[56];

/** Offset 0x15CC - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
  The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
**/
  UINT32                      DevIntConfigPtr;

/** Offset 0x15D0 - Number of DevIntConfig Entry
  Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
  must not be NULL.
**/
  UINT8                       NumOfDevIntConfig;

/** Offset 0x15D1 - Select GPIO IRQ Route
  GPIO IRQ Select. The valid value is 14 or 15.
**/
  UINT8                       GpioIrqRoute;

/** Offset 0x15D2 - Select SciIrqSelect
  SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
**/
  UINT8                       SciIrqSelect;

/** Offset 0x15D3 - Select TcoIrqSelect
  TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
**/
  UINT8                       TcoIrqSelect;

/** Offset 0x15D4 - Enable/Disable Tco IRQ
  Enable/disable TCO IRQ
  $EN_DIS
**/
  UINT8                       TcoIrqEnable;

/** Offset 0x15D5 - PMC ADR enable
  Enable/disable asynchronous DRAM refresh
  $EN_DIS
**/
  UINT8                       PmcAdrEn;

/** Offset 0x15D6 - PMC ADR timer configuration enable
  Enable/disable ADR timer configuration
  $EN_DIS
**/
  UINT8                       PmcAdrTimerEn;

/** Offset 0x15D7 - PMC ADR phase 1 timer value
  Enable/disable ADR timer configuration
**/
  UINT8                       PmcAdrTimer1Val;

/** Offset 0x15D8 - PMC ADR phase 1 timer multiplier value
  Specify the multiplier value for phase 1 ADR timer
**/
  UINT8                       PmcAdrMultiplier1Val;

/** Offset 0x15D9 - PMC ADR host reset partition enable
  Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
  $EN_DIS
**/
  UINT8                       PmcAdrHostPartitionReset;

/** Offset 0x15DA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
  Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
  UINT8                       PchFivrExtV1p05RailEnabledStates;

/** Offset 0x15DB - Mask to enable the platform configuration of external V1p05 VR rail
  External V1P05 Rail Supported Configuration
**/
  UINT8                       PchFivrExtV1p05RailSupportedVoltageStates;

/** Offset 0x15DC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
  Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
  UINT16                      PchFivrExtV1p05RailVoltage;

/** Offset 0x15DE - External V1P05 Icc Max Value
  Granularity of this setting is 1mA and maximal possible value is 200mA
**/
  UINT8                       PchFivrExtV1p05RailIccMax;

/** Offset 0x15DF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
  Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
  UINT8                       PchFivrExtVnnRailEnabledStates;

/** Offset 0x15E0 - Mask to enable the platform configuration of external Vnn VR rail
  External Vnn Rail Supported Configuration
**/
  UINT8                       PchFivrExtVnnRailSupportedVoltageStates;

/** Offset 0x15E1
**/
  UINT8                       FspsUpdRsvd27;

/** Offset 0x15E2 - External Vnn Voltage Value that will be used in S0ix/Sx states
  Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
**/
  UINT16                      PchFivrExtVnnRailVoltage;

/** Offset 0x15E4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
  Granularity of this setting is 1mA and maximal possible value is 200mA
**/
  UINT8                       PchFivrExtVnnRailIccMax;

/** Offset 0x15E5 - Mask to enable the usage of external Vnn VR rail in Sx states
  Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
  Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
**/
  UINT8                       PchFivrExtVnnRailSxEnabledStates;

/** Offset 0x15E6 - External Vnn Voltage Value that will be used in Sx states
  Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
  (0=0mV, 1=2.5mV, 2=5mV...)
**/
  UINT16                      PchFivrExtVnnRailSxVoltage;

/** Offset 0x15E8 - External Vnn Icc Max Value that will be used in Sx states
  Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
  is 1mA and maximal possible value is 200mA
**/
  UINT8                       PchFivrExtVnnRailSxIccMax;

/** Offset 0x15E9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
  to low current mode voltage.
**/
  UINT8                       PchFivrVccinAuxLowToHighCurModeVolTranTime;

/** Offset 0x15EA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
  to retention mode voltage.
**/
  UINT8                       PchFivrVccinAuxRetToHighCurModeVolTranTime;

/** Offset 0x15EB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
  This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
  to retention mode voltage.
**/
  UINT8                       PchFivrVccinAuxRetToLowCurModeVolTranTime;

/** Offset 0x15EC - Transition time in microseconds from Off (0V) to High Current Mode Voltage
  This field has 1us resolution. When value is 0 Transition to 0V is disabled.
**/
  UINT16                      PchFivrVccinAuxOffToHighCurModeVolTranTime;

/** Offset 0x15EE - FIVR Dynamic Power Management
  Enable/Disable FIVR Dynamic Power Management.
  $EN_DIS
**/
  UINT8                       PchFivrDynPm;

/** Offset 0x15EF
**/
  UINT8                       FspsUpdRsvd28;

/** Offset 0x15F0 - External V1P05 Icc Max Value
  Granularity of this setting is 1mA and maximal possible value is 500mA
**/
  UINT16                      PchFivrExtV1p05RailIccMaximum;

/** Offset 0x15F2 - External Vnn Icc Max Value that will be used in S0ix/Sx states
  Granularity of this setting is 1mA and maximal possible value is 500mA
**/
  UINT16                      PchFivrExtVnnRailIccMaximum;

/** Offset 0x15F4 - External Vnn Icc Max Value that will be used in Sx states
  Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
  is 1mA and maximal possible value is 500mA
**/
  UINT16                      PchFivrExtVnnRailSxIccMaximum;

/** Offset 0x15F6 - External V1P05 Control Ramp Timer value
  Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
**/
  UINT8                       PchFivrExtV1p05RailCtrlRampTmr;

/** Offset 0x15F7 - External VNN Control Ramp Timer value
  Hold off time to be used when changing the vnn_ctrl for external bypass value in us
**/
  UINT8                       PchFivrExtVnnRailCtrlRampTmr;

/** Offset 0x15F8 - PCH Compatibility Revision ID
  This member describes whether or not the CRID feature of PCH should be enabled.
  $EN_DIS
**/
  UINT8                       PchCrid;

/** Offset 0x15F9 - PCH Legacy IO Low Latency Enable
  Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
  $EN_DIS
**/
  UINT8                       PchLegacyIoLowLatency;

/** Offset 0x15FA - PCH P2SB
  PCH P2SB
  $EN_DIS
**/
  UINT8                       SvTestUnhideP2sb;

/** Offset 0x15FB - PCH Unlock SideBand access
  The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
  3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
  $EN_DIS
**/
  UINT8                       PchSbAccessUnlock;

/** Offset 0x15FC - Enable 8254 Static Clock Gating
  Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
  might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
  legacy OS using 8254 timer. Also enable this while S0ix is enabled.
  $EN_DIS
**/
  UINT8                       Enable8254ClockGating;

/** Offset 0x15FD - Enable 8254 Static Clock Gating On S3
  This is only applicable when Enable8254ClockGating is disabled. FSP will do the
  8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
  avoids the SMI requirement for the programming.
  $EN_DIS
**/
  UINT8                       Enable8254ClockGatingOnS3;

/** Offset 0x15FE - Enable PCH Io Apic Entry 24-119
  0: Disable; 1: Enable.
  $EN_DIS
**/
  UINT8                       PchIoApicEntry24_119;

/** Offset 0x15FF - PCH Io Apic ID
  This member determines IOAPIC ID. Default is 0x02.
**/
  UINT8                       PchIoApicId;

/** Offset 0x1600 - CNVi Configuration
  This option allows for automatic detection of Connectivity Solution. [Auto Detection]
  assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
  0:Disable, 1:Auto
**/
  UINT8                       CnviMode;

/** Offset 0x1601 - CNVi Wi-Fi Core
  Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
  $EN_DIS
**/
  UINT8                       CnviWifiCore;

/** Offset 0x1602 - CNVi BT Core
  Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
  $EN_DIS
**/
  UINT8                       CnviBtCore;

/** Offset 0x1603 - CNVi BT Interface
  This option configures BT device interface to either USB/PCI
  1:USB, 2:PCI
**/
  UINT8                       CnviBtInterface;

/** Offset 0x1604 - CNVi BT Audio Offload
  Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
  $EN_DIS
**/
  UINT8                       CnviBtAudioOffload;

/** Offset 0x1605 - WWAN Coex
  WWAN Coex is getting updated from UEFI variable
**/
  UINT8                       CnviWwanCoex;

/** Offset 0x1606 - Skip BtPreInit
  BtPreInit can be skipped if SkipBtPreInit is enabled
**/
  UINT8                       SkipBtPreInit;

/** Offset 0x1607
**/
  UINT8                       FspsUpdRsvd29[1];

/** Offset 0x1608 - CNVi RF_RESET pin muxing
  Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
  or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
  UINT32                      CnviRfResetPinMux;

/** Offset 0x160C - CNVi CLKREQ pin muxing
  Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
  or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
  GpioPins*.h.
**/
  UINT32                      CnviClkreqPinMux;

/** Offset 0x1610 - CNVi BT Audio OffOffloadInterfaceload
  Enable/Disable BT Audio OffloadInterface, Default is ENABLE. 0: DISABLE, 1: ENABLE
  $EN_DIS
**/
  UINT8                       CnviBtAudioOffloadInterface;

/** Offset 0x1611 - Enable Device 4
  Enable/disable Device 4
  $EN_DIS
**/
  UINT8                       Device4Enable;

/** Offset 0x1612 - Skip PAM regsiter lock
  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
  PAM registers will be locked by RC
  $EN_DIS
**/
  UINT8                       SkipPamLock;

/** Offset 0x1613 - TCSS LSx OE Enable
  Bits 0, 1, ... max Type C Rettimerless port LSx OE enables
**/
  UINT8                       TcssLsxOe;

/** Offset 0x1614 - PCH HDA Verb Table Entry Number
  Number of Entries in Verb Table.
**/
  UINT8                       PchHdaVerbTableEntryNum;

/** Offset 0x1615
**/
  UINT8                       FspsUpdRsvd30[3];

/** Offset 0x1618 - PCH HDA Verb Table Pointer
  Pointer to Array of pointers to Verb Table.
**/
  UINT64                      PchHdaVerbTablePtr;

/** Offset 0x1620 - PCH HDA Codec Sx Wake Capability
  Capability to detect wake initiated by a codec in Sx
**/
  UINT8                       PchHdaCodecSxWakeCapability;

/** Offset 0x1621 - Enable Pme
  Enable Azalia wake-on-ring.
  $EN_DIS
**/
  UINT8                       PchHdaPme;

/** Offset 0x1622 - HD Audio Link Frequency
  HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
  0: 6MHz, 1: 12MHz, 2: 24MHz
**/
  UINT8                       PchHdaLinkFrequency;

/** Offset 0x1623 - HD Audio Microphone Privacy Mode
  HD Audio Microphone Privacy Mode: 0: No Microphone Privacy Support; 1: HW Managed
  Microphone Privacy; 2: FW Managed Microphone Privacy; 3: Force Microphone Mute
  0: No Microphone Privacy Support, 1: HW Managed Microphone Privacy, 2: FW Managed
  Microphone Privacy, 3: Force Microphone Mute
**/
  UINT8                       PchHdaMicPrivacyMode;

/** Offset 0x1624 - HD Audio Microphone Privacy Deglitch
  HD Audio Microphone Privacy Deglitch: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyDeglitch;

/** Offset 0x1625 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
  HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeSoundWire0;

/** Offset 0x1626 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
  HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeSoundWire1;

/** Offset 0x1627 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
  HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeSoundWire2;

/** Offset 0x1628 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
  HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeSoundWire3;

/** Offset 0x1629 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
  HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeSoundWire4;

/** Offset 0x162A - HD Audio Microphone Privacy applied for Dmic in HW Mode
  HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
  $EN_DIS
**/
  UINT8                       PchHdaMicPrivacyHwModeDmic;

/** Offset 0x162B
**/
  UINT8                       FspsUpdRsvd31;

/** Offset 0x162C - HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before forcing the actual microphone privacy DMA data zeroing.
  HD Audio Microphone Privacy Timeout. Indicates the time-out duration to wait before
  forcing the actual microphone privacy DMA data zeroing.
**/
  UINT32                      PchHdaMicPrivacyTimeout;

/** Offset 0x1630
**/
  UINT8                       PchHdaRsvd[5];

/** Offset 0x1635
**/
  UINT8                       FspsUpdRsvd32[3];

/** Offset 0x1638 - Pointer to ChipsetInit Binary
  ChipsetInit Binary Pointer.
**/
  UINT64                      ChipsetInitBinPtr;

/** Offset 0x1640 - Length of ChipsetInit Binary
  ChipsetInit Binary Length.
**/
  UINT32                      ChipsetInitBinLen;

/** Offset 0x1644
**/
  UINT8                       FspsUpdRsvd33[4];

/** Offset 0x1648 - Pointer to NPHY Binary
  Nphy Binary Pointer.
**/
  UINT64                      NphyBinPtr;

/** Offset 0x1650 - Length of NPHY Binary
  Nphy Binary Length.
**/
  UINT32                      NphyBinLen;

/** Offset 0x1654
**/
  UINT8                       FspsUpdRsvd34[4];

/** Offset 0x1658 - Pointer to SYNPS PHY Binary
  Synps Binary Pointer.
**/
  UINT64                      SynpsPhyBinPtr;

/** Offset 0x1660 - Length of SYNPS PHY Binary
  Synps Binary Length.
**/
  UINT32                      SynpsPhyBinLen;

/** Offset 0x1664 - Skip setting BIOS_DONE When Fw Update.
  When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,skip setting BIOS_DONE MSR
  at EndofPei. Note: BIOS_DONE MSR should be set in later phase before executing
  3rd party code if SiSkipBiosDoneWhenFwUpdate set to TRUE.
  $EN_DIS
**/
  UINT8                       SiSkipBiosDoneWhenFwUpdate;

/** Offset 0x1665 - PMC WDT enable
  Enable/disable PMC WDT configuration
  $EN_DIS
**/
  UINT8                       PmcWdtTimerEn;

/** Offset 0x1666
**/
  UINT8                       FspsUpdRsvd35;

/** Offset 0x1667
**/
  UINT8                       ReservedFspsUpd;
} FSP_S_CONFIG;

/** Fsp S UPD Configuration
**/
typedef struct {

/** Offset 0x0000
**/
  FSP_UPD_HEADER              FspUpdHeader;

/** Offset 0x0020
**/
  FSPS_ARCH2_UPD              FspsArchUpd;

/** Offset 0x0040
**/
  FSP_S_CONFIG                FspsConfig;

/** Offset 0x1668
**/
  UINT8                       FspsUpdRsvd36[6];

/** Offset 0x166E - GP Fault UC Lock
  Enable/Disable GP Fault check on US lock. <b>0: Disable</b>; 1: Enable.
  $EN_DIS
**/
  UINT8                       GpfaultUcLock;

/** Offset 0x166F
**/
  UINT8                       EmbReserved1FspsUpd[3];

/** Offset 0x1672
**/
  UINT8                       UnusedUpdSpace7[4];

/** Offset 0x1676
**/
  UINT16                      UpdTerminator;
} FSPS_UPD;

#pragma pack()

#endif
