Developer Manual/RAM init

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Introduction

One of the most important tasks of coreboot is to initialize your system RAM.

This initialization depends on the type of RAM in your motherboard. To detect the type of RAM the SPD (Serial Presence Detect) must be read for each DIMM. This reading is done using I2C communication using one of the Developer Manual/I2C buses on the motherboard. The exact method of reading depends on the motherboard.

Coreboot supports two methods to initialize your RAM:

  • native RAM init
  • using the MRC blob

Main Goals

  • Use highest clock-rate supported by the board and every DIMM installed
  • Find common settings like CAS Latency
  • Calibrate delay units, impedance and driver strength

SDRAM

There are a number of steps you have to perform to properly initialize SDRAM. This depends on the chipset, as well as the DIMMs which are inserted into the mainboard (and their properties, such as CAS latencies, and so on).

Sample northbridge datasheets:

Sample SDRAM datasheets:

DDR

Duties:

  • Configure extended mode register
  • Configure load mode register

DDR2

Duties:

  • program Mode Registers and Extended Mode Registers
  • calibrate On-Die-Termination resistors
  • set output drive levels
  • find working command rate (1T or 2T)

DDR3

To easy PCB design the fly-by topology has been adopted. It requires additional measurements and calibration in comparison to DDR2.

Duties:

  • program Mode Registers and Extended Mode Registers
  • calibrate On-Die-Termination resistors and dynamic On-Die-Termination resistors
  • compensate delay between DQS and DQ signals
  • compensate delay between CMD and DQ signals
  • find working command rate (1T or 2T)
  • set output driver strength

Resources

SDRAM:

DDR SDRAM:

DDR2 SDRAM

DDR3 SDRAM

Note: Micron lists SPD values for all the memory they produce. This really helps when trying to trouble shoot memory and SPD values. Micron SPD Lookup.