[coreboot-gerrit] Patch merged into coreboot/master: e0e784a Add UCB RISCV support for architecture, soc, and emulation mainboard..
gerrit at coreboot.org
gerrit at coreboot.org
Mon Dec 1 19:06:44 CET 2014
the following patch was just integrated into master:
commit e0e784a456c4d64e5e88ce578371fe6c538db559
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Wed Nov 26 19:25:47 2014 +0000
Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi at google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/7584 for details.
-gerrit
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