[coreboot-gerrit] New patch to review for coreboot: 469bc8c Drop VIA Epia-M series of boards
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Dec 17 22:45:01 CET 2014
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7854
-gerrit
commit 469bc8c5e83808fba12db30863f2723f841bd090
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Wed Dec 17 13:42:13 2014 -0800
Drop VIA Epia-M series of boards
ROMCC cleanups
Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/mainboard/via/Kconfig | 9 -
src/mainboard/via/epia-m/Kconfig | 33 --
src/mainboard/via/epia-m/acpi_tables.c | 36 --
src/mainboard/via/epia-m/board_info.txt | 3 -
src/mainboard/via/epia-m/cmos.layout | 72 ----
src/mainboard/via/epia-m/devicetree.cb | 61 ---
src/mainboard/via/epia-m/dsdt.asl | 256 ------------
src/mainboard/via/epia-m/fadt.c | 157 --------
src/mainboard/via/epia-m/irq_tables.c | 34 --
src/mainboard/via/epia-m/romstage.c | 109 ------
src/mainboard/via/epia-mii/Kconfig | 9 -
src/mainboard/via/epia-mii/board_info.txt | 4 -
src/mainboard/via/epia-ml/Kconfig | 9 -
src/mainboard/via/epia-ml/board_info.txt | 4 -
src/northbridge/via/Kconfig | 1 -
src/northbridge/via/Makefile.inc | 1 -
src/northbridge/via/vt8623/Kconfig | 3 -
src/northbridge/via/vt8623/Makefile.inc | 22 --
src/northbridge/via/vt8623/northbridge.c | 194 ---------
src/northbridge/via/vt8623/raminit.c | 628 ------------------------------
src/northbridge/via/vt8623/raminit.h | 8 -
src/northbridge/via/vt8623/vga.c | 171 --------
22 files changed, 1824 deletions(-)
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index c3fcb14..328d33d 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -12,12 +12,6 @@ config BOARD_VIA_EPIA_M850
help
STOP RIGHT HERE AND READ THIS!!!
Read http://www.coreboot.org/VIA_EPIA-M850 before you proceed.
-config BOARD_VIA_EPIA_M
- bool "EPIA-M"
-config BOARD_VIA_EPIA_MII
- bool "EPIA-MII"
-config BOARD_VIA_EPIA_ML
- bool "EPIA-ML"
config BOARD_VIA_EPIA_N
bool "EPIA-N"
config BOARD_VIA_PC2500E
@@ -30,9 +24,6 @@ endchoice
source "src/mainboard/via/epia-cn/Kconfig"
source "src/mainboard/via/epia-m700/Kconfig"
source "src/mainboard/via/epia-m850/Kconfig"
-source "src/mainboard/via/epia-m/Kconfig"
-source "src/mainboard/via/epia-mii/Kconfig"
-source "src/mainboard/via/epia-ml/Kconfig"
source "src/mainboard/via/epia-n/Kconfig"
source "src/mainboard/via/pc2500e/Kconfig"
source "src/mainboard/via/vt8454c/Kconfig"
diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig
deleted file mode 100644
index 843b7f4..0000000
--- a/src/mainboard/via/epia-m/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-if BOARD_VIA_EPIA_M || BOARD_VIA_EPIA_MII || BOARD_VIA_EPIA_ML
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_VIA_C3
- select NORTHBRIDGE_VIA_VT8623
- select SOUTHBRIDGE_VIA_VT8235
- select SOUTHBRIDGE_RICOH_RL5C476
- select SUPERIO_VIA_VT1211
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_256
- select ROMCC
- select PER_DEVICE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default via/epia-m
-
-if BOARD_VIA_EPIA_M
-
-config MAINBOARD_PART_NUMBER
- string
- default "EPIA-M"
-
-endif # BOARD_VIA_EPIA_M
-
-config IRQ_SLOT_COUNT
- int
- default 5
-
-endif # BOARD_VIA_EPIA_M || BOARD_VIA_EPIA_MII || BOARD_VIA_EPIA_ML
diff --git a/src/mainboard/via/epia-m/acpi_tables.c b/src/mainboard/via/epia-m/acpi_tables.c
deleted file mode 100644
index d02bac2..0000000
--- a/src/mainboard/via/epia-m/acpi_tables.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * coreboot ACPI Table support
- * written by Stefan Reinauer <stepan at openbios.org>
- * ACPI FADT, FACS, and DSDT table support added by
- * Nick Barker <nick.barker9 at btinternet.com>, and those portions
- * (C) Copyright 2004 Nick Barker
- * (C) Copyright 2005 Stefan Reinauer
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- /* Nothing to do */
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* Nothing to do */
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- /* No NUMA, no SRAT */
- return current;
-}
diff --git a/src/mainboard/via/epia-m/board_info.txt b/src/mainboard/via/epia-m/board_info.txt
deleted file mode 100644
index 3d084e0..0000000
--- a/src/mainboard/via/epia-m/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: mini
-Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=81
-Flashrom support: y
diff --git a/src/mainboard/via/epia-m/cmos.layout b/src/mainboard/via/epia-m/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/via/epia-m/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb
deleted file mode 100644
index 98f6b4f..0000000
--- a/src/mainboard/via/epia-m/devicetree.cb
+++ /dev/null
@@ -1,61 +0,0 @@
-chip northbridge/via/vt8623
-
- device cpu_cluster 0 on
- chip cpu/via/c3
- device lapic 0 on end
- end
- end
-
- device domain 0 on
-
- device pci 0.0 on end
- device pci 1.0 on end
-
- chip southbridge/via/vt8235
-
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.3 on end # USB 2
-
- device pci 11.0 on # Southbridge
- chip superio/via/vt1211
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
-
- end
- end
-
- device pci 11.1 on end # IDE
- # 2-4 non existant?
- device pci 11.5 on end # AC97 Audio
- device pci 11.6 off end # AC97 Modem
- device pci 12.0 on end # Ethernet
- end
-# This is on the EPIA MII, not the M.
- chip southbridge/ricoh/rl5c476
- register "enable_cf" = "1"
- device pci 0a.0 on end
- device pci 0a.1 on end
- end
- end
-end
diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl
deleted file mode 100644
index d8553a2..0000000
--- a/src/mainboard/via/epia-m/dsdt.asl
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-M / MII
- * (C) Copyright 2004 Nick Barker <Nick.Barker9 at btinternet.com>
- *
- *
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- /*
- * Define the main processor
- */
- Scope (\_PR)
- {
- Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {}
- }
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * any others would involve declaring the wake up methods
- */
- Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Define how interrupt Link A is plumbed in */
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5}
- })
- Return (BUFF)
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5,9,10}
- })
- Return (BUFF)
- }
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKA
-
- /* Define how interrupt Link B is plumbed in */
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {9}
- })
- Return (BUFF)
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5,9,10}
- })
- Return (BUFF)
- }
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKB
-
- /* Define how interrupt Link C is plumbed in */
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {9}
- })
- Return (BUFF)
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5,9,10}
- })
- Return (BUFF)
- }
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKC
-
- /* Define how interrupt Link D is plumbed in */
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0B)
- }
- /* Current Resources - return irq set up in BIOS */
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5}
- })
- Return (BUFF)
- }
- /* Possible Resources - return the range of irqs
- * we are using for PCI - only here to keep Linux ACPI
- * happy
- */
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFF, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {5,9,10}
- })
- Return (BUFF)
- }
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized ) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
- } // End of LNKD
-
-
- /* top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- /* Epia-MII 6000e cardbus: */
- Package () {0x000AFFFF, 0x00, LNKA, 0x00}, // Cardbus Link A
- Package () {0x000AFFFF, 0x01, LNKB, 0x00}, // Cardbus Link B
- Package () {0x000AFFFF, 0x02, LNKC, 0x00}, // Cardbus Link C
- Package () {0x000AFFFF, 0x03, LNKD, 0x00}, // Cardbus Link D
-
- Package () {0x000DFFFF, 0x00, LNKB, 0x00}, // Firewire Link B
- Package () {0x000DFFFF, 0x01, LNKC, 0x00}, // Firewire Link C
- Package () {0x000DFFFF, 0x02, LNKD, 0x00}, // Firewire Linc D
- Package () {0x000DFFFF, 0x03, LNKA, 0x00}, // Firewire Link A
-
- Package () {0x0010FFFF, 0x00, LNKA, 0x00}, // USB Link A
- Package () {0x0010FFFF, 0x01, LNKB, 0x00}, // USB Link B
- Package () {0x0010FFFF, 0x02, LNKC, 0x00}, // USB Link C
- Package () {0x0010FFFF, 0x03, LNKD, 0x00}, // USB Link D
-
- Package () {0x0011FFFF, 0x00, LNKA, 0x00}, // vt8623 Link A
- Package () {0x0011FFFF, 0x01, LNKB, 0x00}, // vt8623 Link B
- Package () {0x0011FFFF, 0x02, LNKC, 0x00}, // vt8623 Link C
- Package () {0x0011FFFF, 0x03, LNKD, 0x00}, // vt8623 Link D
-
- Package () {0x0012FFFF, 0x00, LNKA, 0x00}, // LAN Link A
- Package () {0x0012FFFF, 0x01, LNKB, 0x00}, // LAN Link B
- Package () {0x0012FFFF, 0x02, LNKC, 0x00}, // LAN Link C
- Package () {0x0012FFFF, 0x03, LNKD, 0x00}, // LAN Link D
-
- Package () {0x0013FFFF, 0x00, LNKA, 0x00}, // Riser slot LinkA
- Package () {0x0013FFFF, 0x01, LNKB, 0x00}, // Riser slot LinkB
- Package () {0x0013FFFF, 0x02, LNKC, 0x00}, // Riser slot LinkC
- Package () {0x0013FFFF, 0x03, LNKD, 0x00}, // Riser slot LinkD
-
- Package () {0x0014FFFF, 0x00, LNKB, 0x00}, // Slot 1, Link B
- Package () {0x0014FFFF, 0x01, LNKC, 0x00}, // Slot 1, Link C
- Package () {0x0014FFFF, 0x02, LNKD, 0x00}, // Slot 1, Link D
- Package () {0x0014FFFF, 0x03, LNKA, 0x00}, // Slot 1, Link A
-
- Package () {0x0001FFFF, 0x00, LNKA, 0x00}, // VGA Link A
- Package () {0x0001FFFF, 0x01, LNKB, 0x00}, // VGA Link B
- Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C
- Package () {0x0001FFFF, 0x03, LNKD, 0x00} // VGA Link D
-
- })
-
-
- } // End of PCI0
-
- } // End of _SB
-
-} // End of Definition Block
diff --git a/src/mainboard/via/epia-m/fadt.c b/src/mainboard/via/epia-m/fadt.c
deleted file mode 100644
index 101ff19..0000000
--- a/src/mainboard/via/epia-m/fadt.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) Copyright 2004 Nick Barker <nick.barker9 at btinternet.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- */
-
-#include <string.h>
-#include <arch/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
- acpi_header_t *header=&(fadt->header);
-
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
- header->length = 244;
- header->revision = 3;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
-
- fadt->firmware_ctrl=(u32)facs;
- fadt->dsdt=(u32)dsdt;
- fadt->preferred_pm_profile=0;
- fadt->sci_int=5;
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0;
- fadt->acpi_disable = 0;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0x0;
-
- fadt->pm1a_evt_blk = 0x400;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = 0x404;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = 0x0;
- fadt->pm_tmr_blk = 0x408;
- fadt->gpe0_blk = 0x420;
- fadt->gpe1_blk = 0x0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 90;
- fadt->p_lvl3_lat = 900;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 0;
- fadt->duty_width = 1;
- fadt->day_alrm = 125;
- fadt->mon_alrm = 126;
- fadt->century = 50;
- fadt->iapc_boot_arch = 0x1;
- fadt->flags = 0x4a5;
-
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = (u32)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 4;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = 0x400;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 2;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = 0x404;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 4;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = 0x408;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 0;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0x420;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
diff --git a/src/mainboard/via/epia-m/irq_tables.c b/src/mainboard/via/epia-m/irq_tables.c
deleted file mode 100644
index 1f2634e..0000000
--- a/src/mainboard/via/epia-m/irq_tables.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0xc20, /* IRQs devoted exclusively to PCI usage */
- 0, /* Vendor */
- 0, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x68, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0x0deb8}}, 0x3, 0x0},
- {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x4, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
deleted file mode 100644
index f63b6a8..0000000
--- a/src/mainboard/via/epia-m/romstage.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include "northbridge/via/vt8623/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "lib/debug.c"
-#include "southbridge/via/vt8235/early_smbus.c"
-#include "southbridge/via/vt8235/early_serial.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/via/vt8623/raminit.c"
-
-static void enable_mainboard_devices(void)
-{
- device_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_8235), 0);
-
- if (dev == PCI_DEV_INVALID) {
- die("Southbridge not found!!!\n");
- }
- pci_write_config8(dev, 0x50, 0x80);
- pci_write_config8(dev, 0x51, 0x1f);
-#if 0
- // This early setup switches IDE into compatibility mode before PCI gets
- // a chance to assign I/Os
- // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
- // // movb $0x09, %dl
- // movb $0x00, %dl
- // PCI_WRITE_CONFIG_BYTE
-#endif
- /* we do this here as in V2, we can not yet do raw operations
- * to pci!
- */
- dev += 0x100; /* ICKY */
-
- pci_write_config8(dev, 0x04, 7);
- pci_write_config8(dev, 0x40, 3);
- pci_write_config8(dev, 0x42, 0);
- pci_write_config8(dev, 0x3c, 0xe);
- pci_write_config8(dev, 0x3d, 0);
-}
-
-static void enable_shadow_ram(void)
-{
- device_t dev = 0; /* no need to look up 0:0.0 */
- unsigned char shadowreg;
- /* dev 0 for southbridge */
- shadowreg = pci_read_config8(dev, 0x63);
- /* 0xf0000-0xfffff */
- shadowreg |= 0x30;
- pci_write_config8(dev, 0x63, shadowreg);
-}
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
- device_t dev;
-
- /* Enable VGA; 32MB buffer. */
- pci_write_config8(0, 0xe1, 0xdd);
-
- /*
- * Disable the firewire stuff, which apparently steps on IO 0+ on
- * reset. Doh!
- */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_6305), 0);
- if (dev != PCI_DEV_INVALID)
- pci_write_config8(dev, 0x15, 0x1c);
-
- enable_vt8235_serial();
- console_init();
-
- enable_smbus();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- // init_timer();
-
- post_code(0x05);
-
- print_debug(" Enabling mainboard devices\n");
- enable_mainboard_devices();
-
- print_debug(" Enabling shadow ram\n");
- enable_shadow_ram();
-
- ddr_ram_setup((const struct mem_controller *)0);
-
- if (bist == 0)
- early_mtrr_init();
-
- //dump_pci_devices();
-}
diff --git a/src/mainboard/via/epia-mii/Kconfig b/src/mainboard/via/epia-mii/Kconfig
deleted file mode 100644
index ff31b93..0000000
--- a/src/mainboard/via/epia-mii/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_VIA_EPIA_MII
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "EPIA-MII"
-
-endif
diff --git a/src/mainboard/via/epia-mii/board_info.txt b/src/mainboard/via/epia-mii/board_info.txt
deleted file mode 100644
index 78b956d..0000000
--- a/src/mainboard/via/epia-mii/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=202
-Flashrom support: y
-Category: mini
-Clone of: via/epia-m
diff --git a/src/mainboard/via/epia-ml/Kconfig b/src/mainboard/via/epia-ml/Kconfig
deleted file mode 100644
index 5e7b6ab..0000000
--- a/src/mainboard/via/epia-ml/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_VIA_EPIA_ML
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "EPIA-ML"
-
-endif
diff --git a/src/mainboard/via/epia-ml/board_info.txt b/src/mainboard/via/epia-ml/board_info.txt
deleted file mode 100644
index cbea112..0000000
--- a/src/mainboard/via/epia-ml/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=301
-Flashrom support: y
-Category: mini
-Clone of: via/epia-m
diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig
index 8a85e2a..9fe6e8d 100644
--- a/src/northbridge/via/Kconfig
+++ b/src/northbridge/via/Kconfig
@@ -1,6 +1,5 @@
source src/northbridge/via/cn700/Kconfig
source src/northbridge/via/cx700/Kconfig
source src/northbridge/via/cn400/Kconfig
-source src/northbridge/via/vt8623/Kconfig
source src/northbridge/via/vx800/Kconfig
source src/northbridge/via/vx900/Kconfig
diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc
index 6c54bef..9c0f431 100644
--- a/src/northbridge/via/Makefile.inc
+++ b/src/northbridge/via/Makefile.inc
@@ -1,4 +1,3 @@
-subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8623) += vt8623
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400
diff --git a/src/northbridge/via/vt8623/Kconfig b/src/northbridge/via/vt8623/Kconfig
deleted file mode 100644
index c2aa82b..0000000
--- a/src/northbridge/via/vt8623/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-config NORTHBRIDGE_VIA_VT8623
- bool
-
diff --git a/src/northbridge/via/vt8623/Makefile.inc b/src/northbridge/via/vt8623/Makefile.inc
deleted file mode 100644
index 7c0012f..0000000
--- a/src/northbridge/via/vt8623/Makefile.inc
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-ramstage-y += northbridge.c
-ramstage-y += vga.c
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
deleted file mode 100644
index 546db4c..0000000
--- a/src/northbridge/via/vt8623/northbridge.c
+++ /dev/null
@@ -1,194 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/hypertransport.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cbmem.h>
-
-/*
- * This fixup is based on capturing values from an Award BIOS. Without
- * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
- * slower than normal, ethernet drops packets).
- * Apparently these registers govern some sort of bus master behavior.
- */
-
-static void northbridge_init(device_t dev)
-{
- device_t fb_dev;
- unsigned long fb;
- unsigned char c;
-
- printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
- pci_write_config8(dev, 0x0d, 0x08);
- pci_write_config8(dev, 0x70, 0x82);
- pci_write_config8(dev, 0x71, 0xc8);
- pci_write_config8(dev, 0x72, 0x00);
- pci_write_config8(dev, 0x73, 0x01);
- pci_write_config8(dev, 0x74, 0x01);
- pci_write_config8(dev, 0x75, 0x08);
- pci_write_config8(dev, 0x76, 0x52);
- pci_write_config8(dev, 0x13, 0xd0);
- pci_write_config8(dev, 0x84, 0x80);
- pci_write_config16(dev, 0x80, 0x610f);
- pci_write_config32(dev, 0x88, 0x00000002);
-
- fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
- if (fb_dev) {
- /* Fixup GART and framebuffer addresses properly.
- * First setup frame buffer properly.
- */
- //fb = pci_read_config32(dev, 0x10); /* Base addres of framebuffer */
- fb = 0xd0000000;
- printk(BIOS_DEBUG, "Frame buffer at %8lx\n",fb);
-
- c = pci_read_config8(dev, 0xe1) & 0xf0; /* size of vga */
- c |= fb>>28; /* upper nibble of frame buffer address */
- c = 0xdd;
- pci_write_config8(dev, 0xe1, c);
- c = 0x81; /* enable framebuffer */
- pci_write_config8(dev, 0xe0, c);
- pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */
- }
-}
-
-static void nullfunc(device_t dev)
-{
- /* Nothing to do */
-}
-
-static struct device_operations northbridge_operations = {
- .read_resources = nullfunc,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_8623,
-};
-
-static void agp_init(device_t dev)
-{
- printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
-
- pci_write_config8(dev, 0x3e, 0x0c);
- pci_write_config8(dev, 0x40, 0x83);
- pci_write_config8(dev, 0x41, 0xc5);
- pci_write_config8(dev, 0x43, 0x44);
- pci_write_config8(dev, 0x44, 0x34);
- pci_write_config8(dev, 0x83, 0x02);
-}
-
-static struct device_operations agp_operations = {
- .read_resources = nullfunc,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = agp_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = 0,
-};
-
-static const struct pci_driver agp_driver __pci_driver = {
- .ops = &agp_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_8633_1,
-};
-
-static void pci_domain_set_resources(device_t dev)
-{
- static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
- device_t mc_dev;
- uint32_t pci_tolm;
-
- printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
-
- pci_tolm = find_pci_tolm(dev->link_list);
- mc_dev = dev->link_list->children;
- if (mc_dev) {
- unsigned long tomk, tolmk;
- unsigned char rambits;
- int i, idx;
-
- for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
- unsigned char reg;
- reg = pci_read_config8(mc_dev, ramregs[i]);
- /* these are ENDING addresses, not sizes.
- * if there is memory in this slot, then reg will be > rambits.
- * So we just take the max, that gives us total.
- * We take the highest one to cover for once and future coreboot
- * bugs. We warn about bugs.
- */
- if (reg > rambits)
- rambits = reg;
- if (reg < rambits)
- printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
- ramregs[i]);
- }
- printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
- tomk = rambits*16*1024 - 32768;
- /* Compute the top of Low memory */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory.
- */
- tolmk = tomk;
- }
-
- set_top_of_ram(tolmk * 1024);
-
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, 640); /* first 640k */
- ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
- }
- assign_resources(dev->link_list);
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
-
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_via_vt8623_ops = {
- CHIP_NAME("VIA VT8623 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
deleted file mode 100644
index f281ce0..0000000
--- a/src/northbridge/via/vt8623/raminit.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Nick Barker <nick.barker9 at btinternet.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- Automatically detect and set up ddr dram on the CLE266 chipset.
- Assumes DDR memory, though chipset also supports SDRAM
- Assumes at least 266MHz memory as no attempt is made to clock
- the chipset down if slower memory is installed.
- So far tested on:
- 256 Mb 266MHz 1 Bank (i.e. single sided)
- 256 Mb 266MHz 2 Bank (i.e. double sided)
- 512 Mb 266MHz 2 Bank (i.e. double sided)
-*/
-/* ported and enhanced from assembler level code in coreboot v1 */
-
-#include <spd.h>
-#include <cpu/x86/mtrr.h>
-#include "raminit.h"
-
-
-
-void dimm_read(unsigned long bank,unsigned long x)
-{
- //unsigned long eax;
- volatile unsigned long y;
- //eax = x;
- y = * (volatile unsigned long *) (x+ bank) ;
-
-}
-
-
-void
-dumpnorth(device_t north)
-{
- uint16_t r, c;
- for(r = 0; r < 256; r += 16) {
- print_debug_hex8(r);
- print_debug(":");
- for(c = 0; c < 16; c++) {
- print_debug_hex8(pci_read_config8(north, r+c));
- print_debug(" ");
- }
- print_debug("\n");
- }
-}
-void print_val(char *str, int val)
-{
- print_debug(str);
- print_debug_hex8(val);
-}
-
-static void ddr_ram_setup(const struct mem_controller *ctrl)
-{
- device_t north = (device_t) 0;
- uint8_t b, c, bank;
- uint16_t i;
- unsigned long bank_address;
-
- print_debug("vt8623 init starting\n");
- north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
- north = 0;
-
-
- pci_write_config8(north,0x75,0x08);
-
- /* setup cpu */
- pci_write_config8(north,0x50,0xc8);
- pci_write_config8(north,0x51,0xde);
- pci_write_config8(north,0x52,0xcf);
- pci_write_config8(north,0x53,0x88);
- pci_write_config8(north,0x55,0x04);
-
-/*
- DRAM MA Map Type Device 0 Offset 58
-
- Determine memory addressing based on the module's memory technology and
- arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
-
- Bank 1/0 MA map type 58[7-5]
- Bank 1/0 command rate 58[4]
- Bank 3/2 MA map type 58[3-1]
- Bank 3/2 command rate 58[0]
-
-
- Read SPD byte 17, Number of banks on SDRAM device.
-*/
- c = 0;
- b = smbus_read_byte(DIMM0,17);
- print_val("Detecting Memory\nNumber of Banks ",b);
-
- if( b != 2 ){ // not 16 Mb type
-
-/*
- Read SPD byte 3, Number of row addresses.
-*/
- b = smbus_read_byte(DIMM0,3);
- print_val("\nNumber of Rows ",b);
- if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
-
-/*
- Read SPD byte 13, Primary DRAM width.
-*/
- b = smbus_read_byte(DIMM0,13);
- print_val("\nPriamry DRAM width",b);
- if( b != 4 ) // mot 64/128Mb (x4)
- c = 0x80; // 256Mb
- }
-
-/*
- 64/128Mb chip
-
- Read SPD byte 4, Number of column addresses.
-*/
- b = smbus_read_byte(DIMM0,4);
- print_val("\nNo Columns ",b);
- if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
- if( b == 9 ) c |= 0x40; // 9 bit col addr
- if( b == 8 ) c |= 0x20; // 8 bit col addr
-
- }
- print_val("\nMA type ",c);
- pci_write_config8(north,0x58,c);
-
-/*
- DRAM bank size. See 4.3.1 pg 35
-
- 5a->5d set to end address for each bank. 1 bit == 16MB
- 5a = bank 0
- 5b = bank 0 + b1
- 5c = bank 0 + b1 + b2
- 5d = bank 0 + b1 + b2 + b3
-*/
-
-// Read SPD byte 31 Module bank density
- c = 0;
- b = smbus_read_byte(DIMM0,31);
- if( b & 0x02 ) c = 0x80; // 2GB
- else if( b & 0x01) c = 0x40; // 1GB
- else if( b & 0x80) c = 0x20; // 512Mb
- else if( b & 0x40) c = 0x10; // 256Mb
- else if( b & 0x20) c = 0x08; // 128Mb
- else if( b & 0x10) c = 0x04; // 64Mb
- else if( b & 0x08) c = 0x02; // 32Mb
- else if( b & 0x04) c = 0x01; // 16Mb / 4Gb
- else c = 0x01; // Error, use default
-
-
- print_val("\nBank 0 (*16 Mb) ",c);
-
- // set bank zero size
- pci_write_config8(north,0x5a,c);
- // SPD byte 5 # of physical banks
- b = smbus_read_byte(DIMM0,5);
-
- print_val("\nNo Physical Banks ",b);
- if( b == 2)
- c <<=1;
-
- print_val("\nTotal Memory (*16 Mb) ",c);
- // set banks 1,2,3
- pci_write_config8(north,0x5b,c);
- pci_write_config8(north,0x5c,c);
- pci_write_config8(north,0x5d,c);
-
-
- /* Read SPD byte 18 CAS Latency */
- b = smbus_read_byte(DIMM0,18);
- print_debug("\nCAS Supported ");
- if(b & 0x04)
- print_debug("2 ");
- if(b & 0x08)
- print_debug("2.5 ");
- if(b & 0x10)
- print_debug("3");
- print_val("\nCycle time at CL X (nS)",smbus_read_byte(DIMM0,9));
- print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(DIMM0,23));
- print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(DIMM0,25));
-
-
- if( b & 0x10 ){ // DDR offering optional CAS 3
- print_debug("\nStarting at CAS 3");
- c = 0x30;
- /* see if we can better it */
- if( b & 0x08 ){ // DDR mandatory CAS 2.5
- if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133MHz at CAS 2.5
- print_debug("\nWe can do CAS 2.5");
- c = 0x20;
- }
- }
- if( b & 0x04 ){ // DDR mandatory CAS 2
- if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133MHz at CAS 2
- print_debug("\nWe can do CAS 2");
- c = 0x10;
- }
- }
- }else{ // no optional CAS values just 2 & 2.5
- print_debug("\nStarting at CAS 2.5");
- c = 0x20; // assume CAS 2.5
- if( b & 0x04){ // Should always happen
- if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133MHz at CAS 2
- print_debug("\nWe can do CAS 2");
- c = 0x10;
- }
- }
- }
-
-
-
-/*
- DRAM Timing Device 0 Offset 64
-
- Row pre-charge 64[7]
- RAS Pulse width 64[6]
- CAS Latency 64[5,4]
-
- SDR DDR
- 00 1T -
- 01 2T 2T
- 10 3T 2.5T
- 11 - 3T
-
- RAS/CAS delay 64[2]
- Bank Interleave 64[1,0]
-
-
- Determine row pre-charge time (tRP)
-
- T nS SPD*4 SPD
- 1T 7.5 0x1e
- 2T 15 0x3c
- 3T 22.5 0x5a
- 4T 30 0x1e
- 5T 37.5 0x25 .5?
- 6T 45 0x2d
-
-
- Read SPD byte 27, min row pre-charge time.
-*/
-
- b = smbus_read_byte(DIMM0,27);
- print_val("\ntRP ",b);
- if( b > 0x3c ) // set tRP = 3T
- c |= 0x80;
-
-
-/*
- Determine RAS to CAS delay (tRCD)
-
- Read SPD byte 29, min row pre-charge time.
-*/
-
- b = smbus_read_byte(DIMM0,29);
- print_val("\ntRCD ",b);
- if( b > 0x3c ) // set tRCD = 3T
- c |= 0x04;
-
-/*
- Determine RAS pulse width (tRAS)
-
-
- Read SPD byte 30, device min active to pre-charge time.
-*/
-
- b = smbus_read_byte(DIMM0,30);
- print_val("\ntRAS ",b);
- if( b > 0x25 ) // set tRAS = 6T
- c |= 0x40;
-
-
-/*
- Determine bank interleave
-
- Read SPD byte 17, Number of banks on SDRAM device.
-*/
- b = smbus_read_byte(DIMM0,17);
- if( b == 4) c |= 0x02;
- else if (b == 2) c |= 0x01;
-
-
- /* set DRAM timing for all banks */
- pci_write_config8(north,0x64,c);
-
- /* set DRAM type to DDR */
- pci_write_config8(north,0x60,0x02);
-
-
- /* DRAM arbitration timer */
- pci_write_config8(north,0x65,0x32);
-
-
-/*
- CPU Frequency Device 0 Offset 54
-
- CPU Frequency 54[7,6] bootstraps at 0xc0 (133MHz)
- DRAM burst length = 8 54[5]
-*/
- pci_write_config8(north,0x54,0xe0);
-
-
-/*
- DRAM Clock Device 0 Offset 69
-
- DRAM/CPU speed 69[7,6] (leave at default 00 == CPU)
- Controller que > 2 69[5]
- Controller que != 4 69[4]
- DRAM 8k page size 69[3]
- DRAM 4k page size 69[2]
- Multiple page mode 69[0]
-*/
-
- pci_write_config8(north,0x69,0x2d);
-
- /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
- udelay(200);
-
-
- /* Enable CKE */
- pci_write_config8(north,0x6b,0x10);
- udelay(200);
-
- /* Disable DRAM refresh */
- pci_write_config8(north,0x6a,0x0);
-
-
- /* Set drive for 1 bank DDR (Table 4.4.2, pg 40) */
- pci_write_config8(north,0x6d,0x044);
- pci_write_config8(north,0x67,0x3a);
-
- b = smbus_read_byte(DIMM0,5); // SPD byte 5 # of physical banks
- if( b > 1) {
- // Increase drive control when there is more than 1 physical bank
- pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE
- pci_write_config8(north,0x6d,0x55); // DC: Early clock select, DQM, CS#, MD
- }
- /* place frame buffer on last bank */
- if( !b) b++; // make sure at least 1 bank reported
- pci_write_config8(north,0xe3,b-1);
-
- for( bank = 0 , bank_address=0; bank < b ; bank++){
-/*
- DDR init described in Via BIOS Porting Guide. Pg 28 (4.2.3.1)
-*/
-
-
- /* NOP command enable */
- pci_write_config8(north,0x6b,0x11);
-
- /* read a double word from any address of the dimm */
- dimm_read(bank_address,0x1f000);
- //udelay(200);
-
- /* All bank precharge Command Enable */
- pci_write_config8(north,0x6b,0x12);
- dimm_read(bank_address,0x1f000);
-
-
- /* MSR Enable */
- pci_write_config8(north,0x6b,0x13);
- dimm_read(bank_address,0x2000);
- udelay(1);
- dimm_read(bank_address,0x800);
- udelay(1);
-
- /* All banks precharge Command Enable */
- pci_write_config8(north,0x6b,0x12);
- dimm_read(bank_address,0x1f200);
-
- /* CBR Cycle Enable */
- pci_write_config8(north,0x6b,0x14);
-
- /* Read 8 times */
- dimm_read(bank_address,0x1f300);
- udelay(100);
- dimm_read(bank_address,0x1f400);
- udelay(100);
- dimm_read(bank_address,0x1f500);
- udelay(100);
- dimm_read(bank_address,0x1f600);
- udelay(100);
- dimm_read(bank_address,0x1f700);
- udelay(100);
- dimm_read(bank_address,0x1f800);
- udelay(100);
- dimm_read(bank_address,0x1f900);
- udelay(100);
- dimm_read(bank_address,0x1fa00);
- udelay(100);
-
- /* MSR Enable */
- pci_write_config8(north,0x6b,0x13);
-
-/*
- Mode Register Definition
- with adjustement so that address calculation is correct - 64 bit technology, therefore
- a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
- to DIMM as a row or column address.
-
- MR[9-7] CAS Latency
- MR[6] Burst Type 0 = sequential, 1 = interleaved
- MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
- MR[0-2] dont care
-
- CAS Latency
- 000 reserved
- 001 reserved
- 010 2
- 011 3
- 100 reserved
- 101 1.5
- 110 2.5
- 111 reserved
-
- CAS 2 0101011000 = 0x158
- CAS 2.5 1101011000 = 0x358
- CAS 3 0111011000 = 0x1d8
-
-*/
- c = pci_read_config8(north,0x64);
- if( (c & 0x30) == 0x10 )
- dimm_read(bank_address,0x150);
- else if((c & 0x30) == 0x20 )
- dimm_read(bank_address,0x350);
- else
- dimm_read(bank_address,0x1d0);
-
- //dimm_read(bank_address,0x350);
-
- /* Normal SDRAM Mode */
- pci_write_config8(north,0x6b,0x58 );
-
-
- bank_address = pci_read_config8(north,0x5a+bank) * 0x1000000;
- } // end of for each bank
-
- /* Adjust DQS (data strobe output delay). See 4.2.3.2 pg 29 */
- pci_write_config8(north,0x66,0x41);
-
- /* determine low bond */
- if( b == 2)
- bank_address = pci_read_config8(north,0x5a) * 0x1000000;
- else
- bank_address = 0;
-
- for(i = 0 ; i < 0x0ff; i++){
- c = i ^ (i>>1); // convert to gray code
- pci_write_config8(north,0x68,c);
- // clear
- *(volatile unsigned long*)(0x4000) = 0;
- *(volatile unsigned long*)(0x4100+bank_address) = 0;
- *(volatile unsigned long*)(0x4200) = 0;
- *(volatile unsigned long*)(0x4300+bank_address) = 0;
- *(volatile unsigned long*)(0x4400) = 0;
- *(volatile unsigned long*)(0x4500+bank_address) = 0;
-
-
- // fill
- *(volatile unsigned long*)(0x4000) = 0x12345678;
- *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
- *(volatile unsigned long*)(0x4200) = 0x78123456;
- *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
- *(volatile unsigned long*)(0x4400) = 0x56781234;
- *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
-
- // verify
- if( *(volatile unsigned long*)(0x4000) != 0x12345678)
- continue;
-
- if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
- continue;
-
- if( *(volatile unsigned long*)(0x4200) != 0x78123456)
- continue;
-
- if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
- continue;
-
- if( *(volatile unsigned long*)(0x4400) != 0x56781234)
- continue;
-
- if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
- continue;
-
- // if everything verified then found low bond
- break;
-
- }
- print_val("\nLow Bond ",i);
- if( i < 0xff ){
- c = i++;
- for( ; i <0xff ; i++){
- pci_write_config8(north,0x68,i ^ (i>>1) );
-
- // clear
- *(volatile unsigned long*)(0x8000) = 0;
- *(volatile unsigned long*)(0x8100+bank_address) = 0;
- *(volatile unsigned long*)(0x8200) = 0x0;
- *(volatile unsigned long*)(0x8300+bank_address) = 0;
- *(volatile unsigned long*)(0x8400) = 0x0;
- *(volatile unsigned long*)(0x8500+bank_address) = 0;
-
- // fill
- *(volatile unsigned long*)(0x8000) = 0x12345678;
- *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
- *(volatile unsigned long*)(0x8200) = 0x78123456;
- *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
- *(volatile unsigned long*)(0x8400) = 0x56781234;
- *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
-
- // verify
- if( *(volatile unsigned long*)(0x8000) != 0x12345678)
- break;
-
- if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
- break;
-
- if( *(volatile unsigned long*)(0x8200) != 0x78123456)
- break;
-
- if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
- break;
-
- if( *(volatile unsigned long*)(0x8400) != 0x56781234)
- break;
-
- if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
- break;
-
- }
- print_val(" High Bond",i);
- c = ((i - c)<<1)/3 +c;
- print_val(" Setting DQS delay",c);
- c = c ^ (c>>1); // convert to gray code
- pci_write_config8(north,0x68,c);
- pci_write_config8(north,0x68,0x42);
- }else{
- print_debug("Unable to determine low bond - Setting default\n");
- pci_write_config8(north,0x68,0x59);
- }
-
-
- pci_write_config8(north,0x66,0x01);
- pci_write_config8(north,0x55,0x07);
-
-
-
-/*
- DRAM refresh rate Device 0 Offset 6a
-
- Units of 16 DRAM clock cycles. (See 4.4.1 pg 39)
-
- Rx69 (DRAM freq) Rx58 (chip tech) Rx6a
-
- 133MHz 64/128Mb 0x86
- 133MHz 256/512Mb 0x43
- 100MHz 64/128Mb 0x65
- 100MHz 256/512Mb 0x32
-*/
-
- b = pci_read_config8(north,0x58);
- if( b < 0x80 ) // 256 tech
- pci_write_config8(north,0x6a,0x86);
- else
- pci_write_config8(north,0x6a,0x43);
-
- pci_write_config8(north,0x61,0xff);
- //pci_write_config8(north,0x67,0x22);
-
- /* pci */
- pci_write_config8(north,0x70,0x82);
- pci_write_config8(north,0x73,0x01);
- pci_write_config8(north,0x76,0x50);
-
-
- pci_write_config8(north,0x71,0xc8);
-
-
- /* graphics aperture base */
-
- pci_write_config8(north,0x13,0xd0);
-
- //pci_write_config8(north,0xe1,0xdf);
- //pci_write_config8(north,0xe2,0x42);
- pci_write_config8(north,0xe0,0x00);
-
- pci_write_config8(north,0x84,0x80);
- pci_write_config16(north,0x80,0x610f);
- pci_write_config32(north,0x88,0x00000002);
-
-
-
- pci_write_config8(north,0xa8,0x04);
- pci_write_config8(north,0xac,0x2f);
- pci_write_config8(north,0xae,0x04);
-
- print_debug("vt8623 done\n");
- dumpnorth(north);
-
- print_debug("AGP\n");
- north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
- pci_write_config32(north,0x20,0xddf0dc00);
- pci_write_config32(north,0x24,0xdbf0d800);
- pci_write_config8(north,0x3e,0x0c);
- //dumpnorth(north);
-
- //print_err("VGA\n");
- //north = pci_locate_device(PCI_ID(0x1106, 0x3122), 0);
- //pci_write_config32(north,0x10,0xd8000008);
- //pci_write_config32(north,0x14,0xdc000000);
- //dumpnorth(north);
-
-}
diff --git a/src/northbridge/via/vt8623/raminit.h b/src/northbridge/via/vt8623/raminit.h
deleted file mode 100644
index b6d2339..0000000
--- a/src/northbridge/via/vt8623/raminit.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-struct mem_controller {
- int empty;
-};
-
-#endif /* RAMINIT_H */
diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c
deleted file mode 100644
index 7ed2792..0000000
--- a/src/northbridge/via/vt8623/vga.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <arch/interrupt.h>
-#include <x86emu/regs.h>
-#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-#include <device/oprom/realmode/x86.h>
-#endif
-
-static int via_vt8623_int15_handler(void)
-{
- int res=0;
- printk(BIOS_DEBUG, "via_vt8623_int15_handler\n");
- switch(X86_EAX & 0xffff) {
- case 0x5f19:
- break;
- case 0x5f18:
- X86_EAX=0x5f;
- X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
- X86_ECX=0x060;
- res=1;
- break;
- case 0x5f00:
- X86_EAX = 0x8600;
- break;
- case 0x5f01:
- X86_EAX = 0x5f;
- X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
- res = 1;
- break;
- case 0x5f02:
- X86_EAX=0x5f;
- X86_EBX= (X86_EBX & 0xffff0000) | 2;
- X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only
- X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default
- res=1;
- break;
- case 0x5f0f:
- X86_EAX=0x860f;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- X86_EAX & 0xffff);
- break;
- }
- return res;
-}
-
-#ifdef UNUSED_CODE
-static void write_protect_vgabios(void)
-{
- device_t dev;
-
- printk(BIOS_DEBUG, "write_protect_vgabios\n");
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
- if (dev)
- pci_write_config8(dev, 0x61, 0xaa);
-
- dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
- if (dev)
- pci_write_config8(dev, 0x61, 0xaa);
-}
-#endif
-
-static void vga_random_fixup(device_t dev)
-{
- printk(BIOS_DEBUG, "VGA random fixup ...\n");
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x0d, 0x20);
- pci_write_config32(dev,0x10,0xd8000008);
- pci_write_config32(dev,0x14,0xdc000000);
-}
-
-static void vga_enable_console(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
- /* Call VGA BIOS int10 function 0x4f14 to enable main console
- * Epia-M does not always autosense the main console so forcing
- * it on is good.
- */
-
- /* int#, EAX, EBX, ECX, EDX, ESI, EDI */
- realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000);
-#endif
-}
-
-static void vga_init(device_t dev)
-{
- vga_random_fixup(dev);
-
- mainboard_interrupt_handlers(0x15, &via_vt8623_int15_handler);
-
-#ifdef MEASURE_VGA_INIT_TIME
- msr_t clocks1, clocks2, instructions, setup;
-
- // set up performnce counters for debugging vga init sequence
- setup.lo = 0x1c0; // count instructions
- wrmsr(0x187,setup);
- instructions.hi = 0;
- instructions.lo = 0;
- wrmsr(0xc2,instructions);
- clocks1 = rdmsr(0x10);
-#endif
- printk(BIOS_DEBUG, "Initializing VGA...\n");
-
- pci_dev_init(dev);
-
- printk(BIOS_DEBUG, "Enable VGA console\n");
- vga_enable_console();
-
-#ifdef MEASURE_VGA_INIT_TIME
- clocks2 = rdmsr(0x10);
- instructions = rdmsr(0xc2);
-
- printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
- printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
- printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
-#endif
-
- pci_write_config32(dev, 0x30, 0);
-
-#if 0
- /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
- unsigned long fb;
- add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
- fb = pci_read_config32(dev,0x10); // get the fb address
- add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
-#endif
-}
-
-static struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x3122,
-};
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