[coreboot-gerrit] New patch to review for coreboot: 55bd37b Drop VIA Epia-N
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Dec 17 23:02:30 CET 2014
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7855
-gerrit
commit 55bd37b4f5773f8f2d7aa704ec0de764e08a5d89
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Wed Dec 17 13:59:20 2014 -0800
Drop VIA Epia-N
ROMCC cleanup.
Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/mainboard/via/Kconfig | 2 -
src/mainboard/via/epia-n/Kconfig | 30 -
src/mainboard/via/epia-n/acpi/irq_links.asl | 571 -----------------
src/mainboard/via/epia-n/acpi/pata_methods.asl | 132 ----
src/mainboard/via/epia-n/acpi/pci_init.asl | 30 -
src/mainboard/via/epia-n/acpi/sb_physical.asl | 548 -----------------
src/mainboard/via/epia-n/acpi_tables.c | 117 ----
src/mainboard/via/epia-n/board_info.txt | 2 -
src/mainboard/via/epia-n/cmos.layout | 72 ---
src/mainboard/via/epia-n/devicetree.cb | 101 ---
src/mainboard/via/epia-n/dsdt.asl | 353 -----------
src/mainboard/via/epia-n/irq_tables.c | 47 --
src/mainboard/via/epia-n/mptable.c | 50 --
src/mainboard/via/epia-n/romstage.c | 135 ----
src/northbridge/via/Kconfig | 1 -
src/northbridge/via/Makefile.inc | 1 -
src/northbridge/via/cn400/Kconfig | 36 --
src/northbridge/via/cn400/Makefile.inc | 24 -
src/northbridge/via/cn400/agp.c | 238 -------
src/northbridge/via/cn400/cn400.h | 49 --
src/northbridge/via/cn400/northbridge.c | 267 --------
src/northbridge/via/cn400/northbridge.h | 26 -
src/northbridge/via/cn400/raminit.c | 819 -------------------------
src/northbridge/via/cn400/raminit.h | 31 -
src/northbridge/via/cn400/vga.c | 153 -----
src/northbridge/via/cn400/vlink.c | 245 --------
26 files changed, 4080 deletions(-)
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index 328d33d..91379ef 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -12,8 +12,6 @@ config BOARD_VIA_EPIA_M850
help
STOP RIGHT HERE AND READ THIS!!!
Read http://www.coreboot.org/VIA_EPIA-M850 before you proceed.
-config BOARD_VIA_EPIA_N
- bool "EPIA-N"
config BOARD_VIA_PC2500E
bool "pc2500e"
config BOARD_VIA_VT8454C
diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig
deleted file mode 100644
index 9b30beb..0000000
--- a/src/mainboard/via/epia-n/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-if BOARD_VIA_EPIA_N
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_VIA_C3
- select NORTHBRIDGE_VIA_CN400
- select SOUTHBRIDGE_VIA_VT8237R
- select SUPERIO_WINBOND_W83697HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select EPIA_VT8237R_INIT
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select ROMCC
- select PER_DEVICE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default via/epia-n
-
-config MAINBOARD_PART_NUMBER
- string
- default "EPIA-N"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_VIA_EPIA_N
diff --git a/src/mainboard/via/epia-n/acpi/irq_links.asl b/src/mainboard/via/epia-n/acpi/irq_links.asl
deleted file mode 100644
index 29b2a1b..0000000
--- a/src/mainboard/via/epia-n/acpi/irq_links.asl
+++ /dev/null
@@ -1,571 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of PCI Interrupt Assignments.
- * This is expected to be included into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison at blueyonder.co.uk>
- *
- */
-
- /* PCI PnP Routing Links */
-
- /* Define how interrupt Link A is plumbed in */
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- /* Status - always return ready */
- Method (_STA, 0, NotSerialized)
- {
- /* See if coreboot has allocated INTA# */
- And (PIRA, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y07)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFA, \_SB.PCI0.LNKA._CRS._Y07._INT, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIRA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
- Return (BUFA)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIRA, 0x0F, PIRA)
- }
- } // End of LNKA
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- /* See if coreboot has allocated INTB# */
- And (PIBC, 0x0F, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y08)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFB, \_SB.PCI0.LNKB._CRS._Y08._INT, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIBC, 0x0F, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
- Return (BUFB)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIBC, 0xF0, PIBC)
- }
-
- } // End of LNKB
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- /* See if coreboot has allocated INTC# */
- And (PIBC, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFC, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFC, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y09)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFC, \_SB.PCI0.LNKC._CRS._Y09._INT, IRC1)
- CreateByteField (BUFC, 0x02, IRC2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIBC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRC1)
- Store (Local4, IRC2)
- }
- Return (BUFC)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIBC, 0x0F, PIBC)
- }
-
-} // End of LNKC
-
-Device (LNKD)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- /* See if coreboot has allocated INTD# */
- And (PIRD, 0xF0, Local0)
- If (LEqual (Local0, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFD, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, )
- {3,4,6,7,10,11,12}
- })
- Return (BUFD)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFD, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared, _Y0A)
- {}
- })
- /* Read the Binary Encoded Field and Map this */
- /* onto the bitwise _INT field in the IRQ descriptor */
- /* See ACPI Spec for detail of _IRQ Descriptor */
- CreateByteField (BUFD, \_SB.PCI0.LNKD._CRS._Y0A._INT, IRD1)
- CreateByteField (BUFD, 0x02, IRD2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (PIRD, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNotEqual (Local1, 0x00))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRD1)
- Store (Local4, IRD2)
- }
- Return (BUFD)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - Set PnP Routing Reg to 0 */
- Method (_DIS, 0, NotSerialized )
- {
- And (PIRD, 0x0F, PIRD)
- }
-
-} // End of LNKD
-
-
-/* APIC IRQ Links */
-
-Device (ATAI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x05)
- Method (_STA, 0, NotSerialized)
- {
- /* ATFL == 0x02 if SATA Enabled */
- If (LNotEqual (ATFL, 0x02))
- {
- /* Double Check By Reading SATA VID */
- /* Otherwise Compatibility Mode */
- If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
- Else
- {
- /* Serial ATA Enabled Check if PATA is in */
- /* Compatibility Mode */
- If (LEqual (\_SB.PCI0.PATA.ENAT, 0x0A))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (ATAN, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000014,
- }
- })
- Return (ATAN)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (ATAB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y10)
- {
- 0x00000000,
- }
- })
- CreateByteField (ATAB, \_SB.PCI0.ATAI._CRS._Y10._INT, IRAI)
- Store (0x14, IRAI)
- Return (ATAB)
-
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-} // End of ATA Interface Link
-
-
-Device (USBI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0A)
- Method (_STA, 0, NotSerialized)
- {
- /* Check that at least one of the USB */
- /* functions is enabled */
- And (IDEB, 0x37, Local0)
- If (LEqual (Local0, 0x37))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (USBB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000015,
- }
- })
-
- Return(USBB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (USBB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y12)
- {
- 0x00000000,
- }
- })
- CreateByteField (USBB, \_SB.PCI0.USBI._CRS._Y12._INT, IRBI)
- Store (0x15, IRBI)
- Return (USBB)
- }
-
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-}
-
-Device (VT8I)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0B)
- Method (_STA, 0, NotSerialized)
- {
- /* Check Whether Sound and/or Modem are Activated */
- If (LEqual (EAMC, 0x03))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (A97C, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000016,
- }
- })
- Return (A97C)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (A97B, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y14)
- {
- 0x00000000,
- }
- })
- CreateByteField (A97B, \_SB.PCI0.VT8I._CRS._Y14._INT, IRCI)
- Store (0x16, IRCI)
- Return (A97B)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-}
-
-
-Device (NICI)
-{
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x0C)
- Method (_STA, 0, NotSerialized)
- {
- /* Check if LAN Function is Enabled */
- /* Note that LAN Enable Polarity is different */
- /* from other functions in VT8237R !? */
- If (LEqual (ELAN, 0x00))
- {
- Return (0x09)
- }
- Else
- {
- Return (0x0B)
- }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (NICB, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
- {
- 0x00000017,
- }
- })
- Return (NICB)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (NICD, ResourceTemplate ()
- {
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y16)
- {
- 0x00000000,
- }
- })
- CreateByteField (NICD, \_SB.PCI0.NICI._CRS._Y16._INT, IRDI)
- Store (0x17, IRDI)
- Return (NICD)
- }
-
- /* Set Resources - dummy function to keep Linux ACPI happy
- * Linux is more than happy not to tinker with irq
- * assignments as long as the CRS and STA functions
- * return good values
- */
- Method (_SRS, 1, NotSerialized) {}
- /* Disable - dummy function to keep Linux ACPI happy */
- Method (_DIS, 0, NotSerialized ) {}
-
-
-}
diff --git a/src/mainboard/via/epia-n/acpi/pata_methods.asl b/src/mainboard/via/epia-n/acpi/pata_methods.asl
deleted file mode 100644
index 1f3e137..0000000
--- a/src/mainboard/via/epia-n/acpi/pata_methods.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of some hardware resources to allow
- * interrupt assignments to be done. This is expected to be included
- * into the PATA Device definition in ab_physical.asl
- * (C) Copyright 2009 Jon Harrison <jon.harrison at blueyonder.co.uk>
- *
- */
-
-Name (TIM0, Package (0x07)
-{
- Package (0x05)
- {
- 0x78, 0xB4, 0xF0, 0x017F, 0x0258
- },
-
- Package (0x05)
- {
- 0x20, 0x22, 0x33, 0x47, 0x5D
- },
-
- Package (0x05)
- {
- 0x04, 0x03, 0x02, 0x01, 0x00
- },
-
- Package (0x04)
- {
- 0x02, 0x01, 0x00, 0x00
- },
-
- Package (0x07)
- {
- 0x78, 0x50, 0x3C, 0x2D, 0x1E, 0x14, 0x0F
- },
-
- Package (0x0F)
- {
- 0x06, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,0x00
- },
-
- Package (0x07)
- {
- 0x0E, 0x08, 0x06, 0x04, 0x02, 0x01, 0x00
- }
-})
-
-
-/* This method sets up the PATA Timing Control.
- * Note that a lot of this is done in the
- * coreboot VT8237R init code, but this is
- * already getting very cluttered with board
- * specific code. Using ACPI will allow this
- * to be de-cluttered a bit (so long as we're
- * running a ACPI capable OS!)
- */
-
-Method (PMEX, 0, Serialized)
-{
- If (REGF)
- {
- /* Check if these regs are still at defaults */
- /* Board specific timing improvement if not */
- /* Already changed */
- If (LEqual (PMPT, 0xA8))
- {
- Store (0x5D, PMPT)
- }
-
- If (LEqual (PSPT, 0xA8))
- {
- Store (0x5D, PSPT)
- }
-
- If (LEqual (SMPT, 0xA8))
- {
- Store (0x5D, SMPT)
- }
-
- If (LEqual (SSPT, 0xA8))
- {
- Store (0x5D, SSPT)
- }
-
- }
-}
-
-/* This Method Provides the method that is used to */
-/* Reset ATA Drives to POST reset condition */
-Method (GTF, 4, Serialized)
-{
- Store (Buffer (0x07)
- {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
- }, Local1)
- Store (Buffer (0x07)
- {
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF
- }, Local2)
- CreateByteField (Local1, 0x01, MODE)
- CreateByteField (Local2, 0x01, UMOD)
- CreateByteField (Local1, 0x05, PCHA)
- CreateByteField (Local2, 0x05, UCHA)
- And (Arg0, 0x03, Local3)
- If (LEqual (And (Local3, 0x01), 0x01))
- {
- Store (0xB0, PCHA)
- Store (0xB0, UCHA)
- }
-
- If (Arg1)
- {
- Store (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Arg2)),
- UMOD)
- Or (UMOD, 0x40, UMOD)
- }
- Else
- {
- Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
- 0x00, 0x00), Local0)
- Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
- )), UMOD)
- }
-
- Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR,
- 0x00, 0x00), Local0)
- Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
- )), MODE)
- Concatenate (Local1, Local2, Local6)
- Return (Local6)
-}
diff --git a/src/mainboard/via/epia-n/acpi/pci_init.asl b/src/mainboard/via/epia-n/acpi/pci_init.asl
deleted file mode 100644
index 3169a03..0000000
--- a/src/mainboard/via/epia-n/acpi/pci_init.asl
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of PCI Interrupt Assignments.
- * This is expected to be included into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison at blueyonder.co.uk>
- *
- */
-
-/* This file provides a PCI Bus Initialisation Method that sets
- * some flags for use in the interrupt link assignment
- */
-
-Method (\_SB.PCI0._INI, 0, NotSerialized)
-{
-
- /* Checking for ATA Interface Enabled */
- Store (0x00, ATFL)
- If (LEqual (EIDE, 0x01))
- {
- Store (0x02, ATFL)
- }
- Else
- {
- If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
- {
- Store (0x01, ATFL)
- }
- }
-
-}
diff --git a/src/mainboard/via/epia-n/acpi/sb_physical.asl b/src/mainboard/via/epia-n/acpi/sb_physical.asl
deleted file mode 100644
index 7dd7b1d..0000000
--- a/src/mainboard/via/epia-n/acpi/sb_physical.asl
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * Basic description of some hardware resources to allow
- * interrupt assignments to be done. This is expected to be included
- * into _SB.PCI0 namespace
- * (C) Copyright 2009 Jon Harrison <jon.harrison at blueyonder.co.uk>
- *
- */
-
-
-/* Basic description of the VT8237R LPC Interface
- * PCI Configuration Space
- */
-
-Device (VT8R)
-{
- Name (_ADR, 0x00110000)
- OperationRegion (USBC, PCI_Config, 0x50, 0x02)
- Scope (\)
- {
- Field (\_SB.PCI0.VT8R.USBC, ByteAcc, NoLock, Preserve)
- {
- IDEB, 8
- }
- }
-
- OperationRegion (VTSB, PCI_Config, 0x00, 0xE8)
- Scope (\)
- {
- Field (\_SB.PCI0.VT8R.VTSB, ByteAcc, NoLock, Preserve)
- {
- Offset (0x02),
- DEID, 16,
- Offset (0x2C),
- ID2C, 8,
- ID2D, 8,
- ID2E, 8,
- ID2F, 8,
- Offset (0x44),
- PIRE, 4,
- PIRF, 4,
- PIRG, 4,
- PIRH, 4,
- POLE, 1,
- POLF, 1,
- POLG, 1,
- POLH, 1,
- ENR8, 1,
- Offset (0x50),
- ESB4, 1,
- ESB3, 1,
- ESB2, 1,
- EIDE, 1,
- EUSB, 1,
- ESB1, 1,
- EAMC, 2,
- EKBC, 1,
- KBCC, 1,
- EPS2, 1,
- ERTC, 1,
- ELAN, 1,
- , 2,
- USBD, 1,
- SIRQ, 8,
- Offset (0x55),
- PIRA, 8,
- PIBC, 8,
- PIRD, 8,
- Offset (0x75),
- BSAT, 1,
- Offset (0x94),
- PWC1, 2,
- GPO1, 1,
- GPO2, 1,
- GPO3, 1,
- PLLD, 1
- }
- }
-}
-
-/* Basic Description of Serial ATA Interface */
-Device (SATA)
-{
- Name (_ADR, 0x000F0000)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.SATA.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.SATA.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-
- OperationRegion (SAPR, PCI_Config, 0x00, 0xC2)
- Field (SAPR, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- IDEI, 8,
- Offset (0x49),
- , 6,
- EPHY, 1
- }
-}
-
-/* Basic Description of Parallel ATA Interface */
-/* An some initialisation of the interface */
-Device (PATA)
-{
- Name (_ADR, 0x000F0001)
- Name (REGF, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.PATA.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- PMEX ()
- /* Check if the Interface is Enabled */
- If (LEqual (\_SB.PCI0.PATA.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-
- /* ACPI Spec says to check that regions are accessible */
- /* before trying to access them */
- Method (_REG, 2, NotSerialized)
- {
- /* Arg0 = Operating Region (0x02 == PCI_Config) */
- If (LEqual (Arg0, 0x02))
- {
- /* Arg1 = Handler Connection Mode (0x01 == Connect) */
- Store (Arg1, REGF)
- }
- }
-
- #include "pata_methods.asl"
-
-
- OperationRegion (PAPR, PCI_Config, 0x00, 0xC2)
- Field (PAPR, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x09),
- ENAT, 4,
- Offset (0x3C),
- IDEI, 8,
- Offset (0x40),
- ESCH, 1,
- EPCH, 1,
- Offset (0x48),
- SSPT, 8,
- SMPT, 8,
- PSPT, 8,
- PMPT, 8,
- Offset (0x50),
- SSUT, 4,
- SSCT, 1,
- SSUE, 3,
- SMUT, 4,
- SMCT, 1,
- SMUE, 3,
- PSUT, 4,
- PSCT, 1,
- PSUE, 3,
- PMUT, 4,
- PMCT, 1,
- PMUE, 3
- }
-
-
- Device (CHN0)
- {
- Name (_ADR, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.PATA.EPCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
-
- Device (DRV0)
- {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x00, PMUE, PMUT, PMPT))
- }
- }
-
- Device (DRV1)
- {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x01, PSUE, PSUT, PSPT))
- }
- }
- }
-
- Device (CHN1)
- {
- Name (_ADR, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (ATFL, 0x02))
- {
- If (LEqual (\_SB.PCI0.SATA.EPHY, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
- Else
- {
- If (LEqual (ATFL, 0x02))
- {
- If (LNotEqual (\_SB.PCI0.PATA.ESCH, 0x01))
- {
- Return (0x00)
- }
- Else
- {
- Return (0x0F)
- }
- }
- Else
- {
- Return(0x00)
- }
- }
- }
-
- Device (DRV0)
- {
- Name (_ADR, 0x00)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x02, SMUE, SMUT, SMPT))
- }
- }
-
- Device (DRV1)
- {
- Name (_ADR, 0x01)
- Method (_GTF, 0, NotSerialized)
- {
- Return (GTF (0x03, SSUE, SSUT, SSPT))
- }
- }
- }
-} // End of PATA Device
-
-
-/* Implement Basic USB Presence detect and */
-/* Power Management Event mask */
-Device (USB0)
-{
- Name (_ADR, 0x00100000)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F0, PCI_Config, 0x00, 0xC2)
- Field (U2F0, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U0IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB0.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB0.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB1)
-{
- Name (_ADR, 0x00100001)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F1, PCI_Config, 0x00, 0xC2)
- Field (U2F1, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U1IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB1.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB1.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB2)
-{
- Name (_ADR, 0x00100002)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F2, PCI_Config, 0x00, 0xC2)
- Field (U2F2, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U2IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB2.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB2.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB3)
-{
- Name (_ADR, 0x00100003)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F3, PCI_Config, 0x00, 0xC2)
- Field (U2F3, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U3IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB3.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB3.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-Device (USB4)
-{
- Name (_ADR, 0x00100004)
- Name (_PRW, Package (0x02)
- {
- 0x0E,
- 0x03
- })
-
- OperationRegion (U2F4, PCI_Config, 0x00, 0xC2)
- Field (U2F4, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- U4IR, 4,
- Offset (0x84),
- ECDX, 2
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.USB4.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.USB4.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-/* Basic Definition of Ethernet Interface */
-Device (NIC0)
-{
- Name (_ADR, 0x00120000)
- Name (_PRW, Package (0x02)
- {
- 0x03,
- 0x05
- })
-
- OperationRegion (NIC0, PCI_Config, 0x00, 0xC2)
- Field (NIC0, ByteAcc, NoLock, Preserve)
- {
- VID, 16,
- Offset (0x04),
- CMDR, 3,
- Offset (0x3C),
- NIIR, 4,
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LNotEqual (\_SB.PCI0.NIC0.VID, 0x1106))
- {
- Return (0x00)
- }
- Else
- {
- If (LEqual (\_SB.PCI0.NIC0.CMDR, 0x00))
- {
- Return (0x0D)
- }
- Else
- {
- Return (0x0F)
- }
- }
- }
-}
-
-/* Very Basic Definition of Sound Controller */
-Device (AC97)
-{
- Name (_ADR, 0x00110005)
- Name (_PRW, Package (0x02)
- {
- 0x0D,
- 0x05
- })
-}
diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c
deleted file mode 100644
index a48a438..0000000
--- a/src/mainboard/via/epia-n/acpi_tables.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * coreboot ACPI Table support
- * written by Stefan Reinauer <stepan at openbios.org>
- * ACPI FADT, FACS, and DSDT table support added by
- * Nick Barker <nick.barker9 at btinternet.com>, and those portions
- * (C) Copyright 2004 Nick Barker
- * (C) Copyright 2005 Stefan Reinauer
- * (C) Copyright 2009 Jon Harrison <bothlyn at blueyonder.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-/*
- * Most parts of this file copied from via\epia-m\acpi_tables.c,
- * and via\epia-m700\acpi_tables.c
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-/*
- * These 8 macros are copied from <arch/smp/mpspec.h>, I have to do this
- * since the "CONFIG_GENERATE_MP_TABLE = 0", and also since
- * mainboard/via/... have no mptable.c (so that I can not set
- * "CONFIG_GENERATE_MP_TABLE = 1" as many other mainboards.
- * So I have to copy these four to here. acpi_fill_madt() needs this.
- */
-#define MP_IRQ_POLARITY_DEFAULT 0x0
-#define MP_IRQ_POLARITY_HIGH 0x1
-#define MP_IRQ_POLARITY_LOW 0x3
-#define MP_IRQ_POLARITY_MASK 0x3
-#define MP_IRQ_TRIGGER_DEFAULT 0x0
-#define MP_IRQ_TRIGGER_EDGE 0x4
-#define MP_IRQ_TRIGGER_LEVEL 0xc
-#define MP_IRQ_TRIGGER_MASK 0xc
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- /* Nothing to do */
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
- u8 lint)
-{
- device_t cpu;
- int cpu_index = 0;
-
- for (cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
- continue;
- }
- if (!cpu->enabled)
- continue;
- current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
- current, cpu_index, flags, lint);
- cpu_index++;
- }
- return current;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x00;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, gsi_base);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- /* No NUMA, no SRAT */
- return current;
-}
diff --git a/src/mainboard/via/epia-n/board_info.txt b/src/mainboard/via/epia-n/board_info.txt
deleted file mode 100644
index d7bb1d9..0000000
--- a/src/mainboard/via/epia-n/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: mini
-Board URL: http://www.idotpc.com/TheStore/pc/viewCategories.asp?idCategory=56
diff --git a/src/mainboard/via/epia-n/cmos.layout b/src/mainboard/via/epia-n/cmos.layout
deleted file mode 100644
index 9050c3d..0000000
--- a/src/mainboard/via/epia-n/cmos.layout
+++ /dev/null
@@ -1,72 +0,0 @@
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/via/epia-n/devicetree.cb b/src/mainboard/via/epia-n/devicetree.cb
deleted file mode 100644
index d17b96d..0000000
--- a/src/mainboard/via/epia-n/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-chip northbridge/via/cn400 # Northbridge
-
- device cpu_cluster 0 on # APIC cluster
- chip cpu/via/c3 # VIA C3
- device lapic 0 on end # APIC
- end
- end
-
- device domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- device pci f.0 on end # IDE/SATA
- device pci f.1 on end # IDE
- register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97
- register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating
- device pci 10.0 on end # OHCI
- device pci 10.1 on end # OHCI
- device pci 10.2 on end # OHCI
- device pci 10.3 on end # OHCI
- device pci 10.4 on end # EHCI
- device pci 10.5 off end # USB Direct
- device pci 11.0 on # Southbridge LPC
- chip superio/winbond/w83697hf # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.6 off # IR Port
- io 0x60 = 0x000
- end
- device pnp 2e.7 off # GPIO 1
- io 0x60 = 0x201 # 0x201
- end
- device pnp 2e.8 off # GPIO 5
- io 0x60 = 0x330 # 0x330
- end
- device pnp 2e.9 off # GPIO 2, 3,and 4
- io 0x60 = 0x000 #
- end
- device pnp 2e.a off # ACPI
- io 0x60 = 0x000 #
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 11.5 off end # AC'97 audio
- device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
-end
diff --git a/src/mainboard/via/epia-n/dsdt.asl b/src/mainboard/via/epia-n/dsdt.asl
deleted file mode 100644
index f8d47ce..0000000
--- a/src/mainboard/via/epia-n/dsdt.asl
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Minimalist ACPI DSDT table for EPIA-N / NL
- * (C) Copyright 2009 Jon Harrison <jon.harrison at blueyonder.co.uk>
- * Heavily based on EPIA-M dstd.asl
- * (C) Copyright 2004 Nick Barker <Nick.Barker9 at btinternet.com>
- *
- */
-DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1)
-{
- Scope (\_PR)
- {
- Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00) {}
- }
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * any others would involve declaring the wake up methods
- */
- Name (\_S0, Package (0x04)
- {
- 0x00,
- 0x00,
- 0x00,
- 0x00
- })
- Name (\_S5, Package (0x04)
- {
- 0x02,
- 0x02,
- 0x02,
- 0x02
- })
-
- /* Global Flag Used to Indicate State of */
- /* ATA Interface */
- Name (ATFL, 0x00)
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
-
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x01)
- Name (_BBN, 0x00)
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
-
- Package (0x04) {0x000FFFFF, 0x00, ATAI, 0x00}, // SATA Link A
- Package (0x04) {0x000FFFFF, 0x01, ATAI, 0x00}, // SATA Link B
- Package (0x04) {0x000FFFFF, 0x02, ATAI, 0x00}, // SATA Link C
- Package (0x04) {0x000FFFFF, 0x03, ATAI, 0x00}, // SATA Link D
-
- Package (0x04) {0x0010FFFF, 0x00, USBI, 0x00}, // USB Link A
- Package (0x04) {0x0010FFFF, 0x01, USBI, 0x00}, // USB Link B
- Package (0x04) {0x0010FFFF, 0x02, USBI, 0x00}, // USB Link C
- Package (0x04) {0x0010FFFF, 0x03, USBI, 0x00}, // USB Link D
-
- Package (0x04) {0x0011FFFF, 0x00, VT8I, 0x00}, // VT8237 Link A
- Package (0x04) {0x0011FFFF, 0x01, VT8I, 0x00}, // VT8237 Link B
- Package (0x04) {0x0011FFFF, 0x02, VT8I, 0x00}, // VT8237 Link C
- Package (0x04) {0x0011FFFF, 0x03, VT8I, 0x00}, // VT8237 Link D
-
- Package (0x04) {0x0012FFFF, 0x00, NICI, 0x00}, // LAN Link A
- Package (0x04) {0x0012FFFF, 0x01, NICI, 0x00}, // LAN Link B
- Package (0x04) {0x0012FFFF, 0x02, NICI, 0x00}, // LAN Link C
- Package (0x04) {0x0012FFFF, 0x03, NICI, 0x00}, // LAN Link D
-
- Package (0x04) {0x0001FFFF, 0x00, 0, 0x10}, // VGA Link A (GSI)
- Package (0x04) {0x0001FFFF, 0x01, 0, 0x11}, // VGA Link B (GSI)
- Package (0x04) {0x0001FFFF, 0x02, 0, 0x12}, // VGA Link C (GSI)
- Package (0x04) {0x0001FFFF, 0x03, 0, 0x13}, // VGA Link D (GSI)
-
- Package (0x04) {0x0014FFFF, 0x00, 0, 0x12}, // Slot 1 Link C (GSI)
- Package (0x04) {0x0014FFFF, 0x01, 0, 0x13}, // Slot 1 Link D (GSI)
- Package (0x04) {0x0014FFFF, 0x02, 0, 0x10}, // Slot 1 Link A (GSI)
- Package (0x04) {0x0014FFFF, 0x03, 0, 0x11}, // Slot 1 Link B (GSI)
-
- Package (0x04) {0x0013FFFF, 0x00, 0, 0x13}, // Riser Slot Link D (GSI)
- Package (0x04) {0x0013FFFF, 0x01, 0, 0x12}, // Riser Slot Link C (GSI)
- Package (0x04) {0x0013FFFF, 0x02, 0, 0x11}, // Riser Slot Link B (GSI)
- Package (0x04) {0x0013FFFF, 0x03, 0, 0x10} // Riser Slot Link A (GSI)
-
- })
-
- /* PCI Devices Included Here */
- #include "acpi/sb_physical.asl"
-
- /* Legacy PNP Devices Defined Here */
-
- /* Disable PS2 Mouse Support */
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x09)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF1, ResourceTemplate ()
- {
- IRQNoFlags ()
- {12}
- })
- Return (BUF1)
- }
- }
-
- /* Disable Legacy PS2 Keyboard Support */
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CID, 0x0B03D041)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x09)
- }
-
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0060, // Range Minimum
- 0x0060, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IO (Decode16,
- 0x0064, // Range Minimum
- 0x0064, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- IRQNoFlags ()
- {1}
- })
- }
-
- /* Legacy PIC Description */
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0020, // Range Minimum
- 0x0020, // Range Maximum
- 0x01, // Alignment
- 0x02, // Length
- )
- IO (Decode16,
- 0x00A0, // Range Minimum
- 0x00A0, // Range Maximum
- 0x01, // Alignment
- 0x02, // Length
- )
- IRQNoFlags ()
- {2}
- })
- }
-
- /* Legacy DMA Description */
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- DMA (Compatibility, BusMaster, Transfer8, )
- {4}
- IO (Decode16,
- 0x0000, // Range Minimum
- 0x0000, // Range Maximum
- 0x01, // Alignment
- 0x10, // Length
- )
- IO (Decode16,
- 0x0080, // Range Minimum
- 0x0080, // Range Maximum
- 0x01, // Alignment
- 0x11, // Length
- )
- IO (Decode16,
- 0x0094, // Range Minimum
- 0x0094, // Range Maximum
- 0x01, // Alignment
- 0x0C, // Length
- )
- IO (Decode16,
- 0x00C0, // Range Minimum
- 0x00C0, // Range Maximum
- 0x01, // Alignment
- 0x20, // Length
- )
- })
- }
-
- /* Legacy Timer Description */
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0040, // Range Minimum
- 0x0040, // Range Maximum
- 0x01, // Alignment
- 0x04, // Length
- )
- IRQNoFlags ()
- {0}
- })
- }
-
- /* Legacy RTC Description */
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0070, // Range Minimum
- 0x0070, // Range Maximum
- 0x04, // Alignment
- 0x04, // Length
- )
- IRQNoFlags ()
- {8}
- })
- }
-
- /* Legacy Speaker Description */
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0061, // Range Minimum
- 0x0061, // Range Maximum
- 0x01, // Alignment
- 0x01, // Length
- )
- })
- }
-
- /* Legacy Math Co-Processor Description */
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x00F0, // Range Minimum
- 0x00F0, // Range Maximum
- 0x01, // Alignment
- 0x10, // Length
- )
- IRQNoFlags ()
- {13}
- })
- }
-
- /* General Legacy IO Reservations */
- /* Covering items that are not explicitly reserved */
- /* from coreboot. */
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0010, // Range Minimum
- 0x0010, // Range Maximum
- 0x01, // Alignment
- 0x10, // Length
- )
- IO (Decode16,
- 0x0022, // Range Minimum
- 0x0022, // Range Maximum
- 0x01, // Alignment
- 0x1E, // Length
- )
- IO (Decode16,
- 0x0044, // Range Minimum
- 0x0044, // Range Maximum
- 0x01, // Alignment
- 0x1C, // Length
- )
- IO (Decode16,
- 0x0062, // Range Minimum
- 0x0062, // Range Maximum
- 0x01, // Alignment
- 0x02, // Length
- )
- IO (Decode16,
- 0x0065, // Range Minimum
- 0x0065, // Range Maximum
- 0x01, // Alignment
- 0x0B, // Length
- )
- IO (Decode16,
- 0x0074, // Range Minimum
- 0x0074, // Range Maximum
- 0x01, // Alignment
- 0x0C, // Length
- )
- IO (Decode16,
- 0x0091, // Range Minimum
- 0x0091, // Range Maximum
- 0x01, // Alignment
- 0x03, // Length
- )
- IO (Decode16,
- 0x00A2, // Range Minimum
- 0x00A2, // Range Maximum
- 0x01, // Alignment
- 0x1E, // Length
- )
- IO (Decode16,
- 0x00E0, // Range Minimum
- 0x00E0, // Range Maximum
- 0x01, // Alignment
- 0x10, // Length
- )
- IO (Decode16,
- 0x04D0, // Range Minimum
- 0x04D0, // Range Maximum
- 0x01, // Alignment
- 0x02, // Length
- )
- IO (Decode16,
- 0x0294, // Range Minimum
- 0x0294, // Range Maximum
- 0x01, // Alignment
- 0x04, // Length
- )
- })
- }
-
- #include "acpi/irq_links.asl"
- #include "acpi/pci_init.asl"
-
- } //End of PCI0
-
- } // End of _SB
-
-} // End of Definition Block
diff --git a/src/mainboard/via/epia-n/irq_tables.c b/src/mainboard/via/epia-n/irq_tables.c
deleted file mode 100644
index 9c1ee4e..0000000
--- a/src/mainboard/via/epia-n/irq_tables.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- * (but if you do, please run checkpir on it to verify)
- *
- * Contains the IRQ Routing Table dumped directly from your
- * memory, which BIOS sets up.
- *
- * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
- */
-
-#ifdef GETPIR
-#include "pirq_routing.h"
-#else
-#include <arch/pirq_routing.h>
-#endif
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */
- 0x1c00, /* IRQs devoted exclusively to PCI usage */
- 0x1106, /* Vendor */
- 0x3227, /* Device */
- 0, /* Miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xf, /* u8 checksum. This has to be set to some
- value that would give 0 after the sum of all
- bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x14<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x1, 0x0},
- {0x00,(0x13<<3)|0x0, {{0x05, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0},
- {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
- {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
- {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0},
- }
-};
-#ifndef GETPIR
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
-#endif
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
deleted file mode 100644
index de25d0e..0000000
--- a/src/mainboard/via/epia-n/mptable.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* generated by MPTable, version 2.0.15*/
-/* as modified by RGM for coreboot */
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
- mptable_write_buses(mc, NULL, &isa_bus);
-
-/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- mptable_lintsrc(mc, 0x0);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
deleted file mode 100644
index 0de7556..0000000
--- a/src/mainboard/via/epia-n/romstage.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include "northbridge/via/cn400/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "southbridge/via/vt8237r/early_smbus.c"
-#include "superio/winbond/w83697hf/early_serial.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
-#define DUMMY_DEV PNP_DEV(0x2e, 0)
-
-static const struct mem_controller ctrl = {
- .d0f0 = 0x0000,
- .d0f2 = 0x2000,
- .d0f3 = 0x3000,
- .d0f4 = 0x4000,
- .d0f7 = 0x7000,
- .d1f0 = 0x8000,
- .channel0 = { DIMM0 },
-};
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/via/cn400/raminit.c"
-
-static void enable_mainboard_devices(void)
-{
- device_t dev;
- u8 reg;
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- die("Southbridge not found!!!\n");
-
- /* bit=0 means enable function (per VT8237R datasheet)
- * 7 17.6 MC97
- * 6 17.5 AC97
- * 5 16.1 USB 2
- * 4 16.0 USB 1
- * 3 15.0 SATA and PATA
- * 2 16.2 USB 3
- * 1 16.4 USB EHCI
- */
- pci_write_config8(dev, 0x50, 0xC0);
-
- /*bit=0 means enable internal function (per VT8237R datasheet)
- * 7 USB Device Mode
- *bit=1 means enable internal function (per VT8237R datasheet)
- * 6 Reserved
- * 5 LAN Controller Clock Gating
- * 4 LAN Controller
- * 3 Internal RTC
- * 2 Internal PS2 Mouse
- * 1 Internal KBC Configuration
- * 0 Internal Keyboard Controller
- */
- pci_write_config8(dev, 0x51, 0x9d);
-}
-
-static void enable_shadow_ram(void)
-{
- unsigned char shadowreg;
-
- shadowreg = pci_read_config8(ctrl.d0f3, 0x82);
- /* 0xf0000-0xfffff Read/Write*/
- shadowreg |= 0x30;
- pci_write_config8(ctrl.d0f3, 0x82, shadowreg);
-}
-
-#include <cpu/intel/romstage.h>
-static void main(unsigned long bist)
-{
- unsigned long x;
- device_t dev;
-
- /* Enable multifunction for northbridge. */
- pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
-
- w83697hf_set_clksel_48(DUMMY_DEV);
- w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- enable_smbus();
- smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
- report_bist_failure(bist);
-
- print_debug("Enabling mainboard devices\n");
- enable_mainboard_devices();
-
- print_debug("Enable F-ROM Shadow RAM\n");
- enable_shadow_ram();
-
- print_debug("Setup CPU Interface\n");
- c3_cpu_setup(ctrl.d0f2);
-
- ddr_ram_setup();
-
- if (bist == 0)
- early_mtrr_init();
-}
diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig
index 9fe6e8d..7b9fa1d 100644
--- a/src/northbridge/via/Kconfig
+++ b/src/northbridge/via/Kconfig
@@ -1,5 +1,4 @@
source src/northbridge/via/cn700/Kconfig
source src/northbridge/via/cx700/Kconfig
-source src/northbridge/via/cn400/Kconfig
source src/northbridge/via/vx800/Kconfig
source src/northbridge/via/vx900/Kconfig
diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc
index 9c0f431..b3d595e 100644
--- a/src/northbridge/via/Makefile.inc
+++ b/src/northbridge/via/Makefile.inc
@@ -1,5 +1,4 @@
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700
-subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900
diff --git a/src/northbridge/via/cn400/Kconfig b/src/northbridge/via/cn400/Kconfig
deleted file mode 100644
index 42fa096..0000000
--- a/src/northbridge/via/cn400/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-config NORTHBRIDGE_VIA_CN400
- bool
-
-# TODO: Values are from the CX700 datasheet, not sure if this matches CN400.
-# TODO: What should be the per-chipset default value here?
-choice
- prompt "Onboard graphics"
- default CN400_VIDEO_MB_32MB
- depends on NORTHBRIDGE_VIA_CN400
-
-# TODO: Disabling onboard graphics is not yet supported in the source code.
-config CN400_VIDEO_MB_OFF
- bool "Disabled, 0KB"
-config CN400_VIDEO_MB_8MB
- bool "Enabled, 8MB"
-config CN400_VIDEO_MB_16MB
- bool "Enabled, 16MB"
-config CN400_VIDEO_MB_32MB
- bool "Enabled, 32MB"
-config CN400_VIDEO_MB_64MB
- bool "Enabled, 64MB"
-config CN400_VIDEO_MB_128MB
- bool "Enabled, 128MB"
-
-endchoice
-
-config VIDEO_MB
- int
- default 0 if CN400_VIDEO_MB_OFF
- default 8 if CN400_VIDEO_MB_8MB
- default 16 if CN400_VIDEO_MB_16MB
- default 32 if CN400_VIDEO_MB_32MB
- default 64 if CN400_VIDEO_MB_64MB
- default 128 if CN400_VIDEO_MB_128MB
- depends on NORTHBRIDGE_VIA_CN400
-
diff --git a/src/northbridge/via/cn400/Makefile.inc b/src/northbridge/via/cn400/Makefile.inc
deleted file mode 100644
index 667c71a..0000000
--- a/src/northbridge/via/cn400/Makefile.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-ramstage-y += northbridge.c
-ramstage-y += agp.c
-ramstage-y += vga.c
-ramstage-y += vlink.c
diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c
deleted file mode 100644
index ece71e0..0000000
--- a/src/northbridge/via/cn400/agp.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "northbridge.h"
-#include "cn400.h"
-
-/* This is the main AGP device, and only one used when configured for AGP 2.0 */
-static void agp_init(device_t dev)
-{
- u32 reg32;
- u8 reg8;
- int i, j;
-
- /* Some of this may not be necessary (should be handled by the OS). */
- printk(BIOS_DEBUG, "Enabling AGP.\n");
-
- /* Allow R/W access to AGP registers. */
- pci_write_config8(dev, 0x4d, 0x05);
-
- /* Setup PCI latency timer. */
- pci_write_config8(dev, 0xd, 0x8);
-
- /* Write Secondary Vendor Ids */
- pci_write_config32(dev, 0x2C, 0xAA071106);
-
- /*
- * Set to AGP 3.0 Mode, which should theoretically render the rest of
- * the registers set here pointless.
- */
- pci_write_config8(dev, 0x84, 0x1b);
-
- /* AGP Request Queue Size */
- pci_write_config8(dev, 0x4a, 0x1f);
-
- /*
- * AGP Hardware Support (default 0xc4)
- * 7: AGP SBA Enable (1 to Enable)
- * 6: AGP Enable
- * 5: Reserved
- * 4: Fast Write Enable
- * 3: AGP8X Mode Enable
- * 2: AGP4X Mode Enable
- * 1: AGP2X Mode Enable
- * 0: AGP1X Mode Enable
- */
- pci_write_config8(dev, 0x4b, 0xc4);
-
- /* Enable AGP Backdoor */
- pci_write_config8(dev, 0xb5, 0x03);
-
- /* Set aperture to 128 MB. */
- /* TODO: Use config option, explain how it works. */
- pci_write_config32(dev, 0x94, 0x00010f20);
- /* Set GART Table Base Address (31:12). */
- pci_write_config32(dev, 0x98, (0x37b20 << 12));
- /* Set AGP Aperture Base. */
- pci_write_config32(dev, 0x10, 0xe8000008);
-
- /* NMI/AGPBUSY# Function Select */
- pci_write_config8(dev, 0xbe, 0x80);
-
- /* AGP Misc Control 1 */
- pci_write_config8(dev, 0xc2, 0x40);
-
- /* Enable CPU/PMSTR GART Access and DBI function. */
- reg32 = pci_read_config8(dev, 0xbf);
- reg32 |= 0x8c;
- pci_write_config8(dev, 0xbf, reg32);
-
- /* Enable AGP Aperture. */
- pci_write_config32(dev, 0x90, 0x0180);
-
- /* AGP Control */
- pci_write_config8(dev, 0xbc, 0x25);
- pci_write_config8(dev, 0xbd, 0xd2);
-
- /*
- * AGP Pad, driving strength, and delay control. All this should be
- * constant, seeing as the VGA controller is onboard.
- */
- pci_write_config8(dev, 0x40, 0xda);
- pci_write_config8(dev, 0x41, 0xca);
- pci_write_config8(dev, 0x42, 0x01);
- pci_write_config8(dev, 0x43, 0xca);
- pci_write_config8(dev, 0x44, 0x04);
-
- /* AGPC CKG Control */
- pci_write_config8(dev, 0xc0, 0x04);
- pci_write_config8(dev, 0xc1, 0x02);
-
-#ifdef DEBUG_CN400
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-#endif
-}
-
-static const struct device_operations agp_operations = {
- .read_resources = DEVICE_NOOP,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = agp_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver agp_driver __pci_driver = {
- .ops = &agp_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_AGP,
-};
-
-static void agp_bridge_read_resources (device_t dev)
-{
- struct resource *res;
-
- res = new_resource(dev, 1);
- res->base = 0xF0000000ULL;
- res->size = 0x06000000ULL;
- res->limit = 0xffffffffULL;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- res = new_resource(dev, 2);
- res->base = 0xB000UL;
- res->size = 4096;
- res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
-}
-/*
- * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
- * config in this device takes presidence. We configure both just to be safe.
- */
-static void agp_bridge_init(device_t dev)
-{
- u8 reg8;
- int i, j;
-
- printk(BIOS_DEBUG, "Entering %s\n", __func__);
-
- pci_write_config16(dev, 0x4, 0x0107);
-
- /* Secondary Bus Number */
- pci_write_config8(dev, 0x19, 0x01);
- /* Subordinate Bus Number */
- pci_write_config8(dev, 0x1a, 0x01);
-
- /* I/O Base */
- pci_write_config8(dev, 0x1c, 0xf0);
-
- /* I/O Limit */
- pci_write_config8(dev, 0x1d, 0x00);
-
- /* Memory Base */
- pci_write_config16(dev, 0x20, 0xf400);
-
- /* Memory Limit */
- pci_write_config16(dev, 0x22, 0xf5f0);
-
- /* Prefetchable Memory Base */
- pci_write_config16(dev, 0x24, 0xf000);
-
- /* Prefetchable Memory Limit */
- pci_write_config16(dev, 0x26, 0xf3f0);
-
- /* Enable VGA Compatible Memory/IO Range */
- pci_write_config8(dev, 0x3e, 0x0e);
-
- /* AGP Bus Control */
- pci_write_config8(dev, 0x40, 0x83);
- pci_write_config8(dev, 0x41, 0xC7);
- pci_write_config8(dev, 0x42, 0x02);
- pci_write_config8(dev, 0x43, 0x44);
- pci_write_config8(dev, 0x44, 0x34);
- pci_write_config8(dev, 0x45, 0x72);
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-
-}
-
-static const struct device_operations agp_bridge_operations = {
- .read_resources = agp_bridge_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = agp_bridge_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = 0,
-};
-
-static const struct pci_driver agp_bridge_driver __pci_driver = {
- .ops = &agp_bridge_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_BRIDGE,
-};
diff --git a/src/northbridge/via/cn400/cn400.h b/src/northbridge/via/cn400/cn400.h
deleted file mode 100644
index 4921bef..0000000
--- a/src/northbridge/via/cn400/cn400.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DEBUG_CN400
-
-/* VGA stuff */
-#define SR_INDEX 0x3c4
-#define SR_DATA 0x3c5
-#define CRTM_INDEX 0x3b4
-#define CRTM_DATA 0x3b5
-#define CRTC_INDEX 0x3d4
-#define CRTC_DATA 0x3d5
-
-/* Memory controller registers */
-#define RANK0_END 0x40
-#define RANK1_END 0x41
-#define RANK2_END 0x42
-#define RANK3_END 0x43
-
-#define DDR_PAGE_CTL 0x69
-#define DRAM_REFRESH_COUNTER 0x6a
-#define DRAM_MISC_CTL 0x6b
-#define CH_A_DQS_OUTPUT_DELAY 0x70
-#define CH_A_MD_OUTPUT_DELAY 0x71
-
-/* RAM init commands */
-#define RAM_COMMAND_NORMAL (const char) 0x00
-#define RAM_COMMAND_NOP (const char) 0x01
-#define RAM_COMMAND_PRECHARGE (const char) 0x02
-#define RAM_COMMAND_MSR_LOW (const char) 0x03
-#define RAM_COMMAND_CBR (const char) 0x04
-#define RAM_COMMAND_MSR_HIGH (const char) 0x05
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
deleted file mode 100644
index b797179..0000000
--- a/src/northbridge/via/cn400/northbridge.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe at gmail.com> for VIA)
- * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <lib.h>
-#include <cbmem.h>
-#include <cpu/cpu.h>
-#include "northbridge.h"
-#include "cn400.h"
-
-static void memctrl_init(device_t dev)
-{
- device_t vlink_dev;
- u16 reg16;
- u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8;
- int i, j;
-
- printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n");
- /* vlink mirror */
- vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
-
- /* Setup Low Memory Top */
- /* 0x47 == HA(32:25) */
- /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
- ranks = pci_read_config8(dev, 0x47);
- reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
-
- pci_write_config16(dev, 0x84, reg16);
- printk(BIOS_SPEW, "Low Top Address = 0x%04X\n", reg16);
-
- /* Set up the VGA framebuffer size and Base Address */
- /* Note dependencies between agp.c and vga.c and here */
- reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15) | 0xF00;
- pci_write_config16(dev, 0xa0, reg16);
-
-
- for (ranks = 0x4b; ranks >= 0x48; ranks--) {
- if (pci_read_config8(dev, ranks)) {
- ranks -= 0x48;
- break;
- }
- }
- if (ranks == 0x47)
- ranks = 0x00;
- reg16 = 0xaaf0;
- reg16 |= ranks;
- /* GMINT Misc. FrameBuffer rank */
- pci_write_config16(dev, 0xb0, reg16);
- /* AGPCINT Misc. */
- pci_write_config8(dev, 0xb8, 0x08);
-
- /* Arbritation Counters */
- pci_write_config8(dev, 0xb2, 0xaa);
-
- /* Write FIFO Setup */
- pci_write_config8(dev, 0xb3, 0x5a);
-
- /* Graphics control optimisation */
- pci_write_config8(dev, 0xb4, 0x0f);
-
- /* Shadow RAM */
- pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
- /* PAGE C, D, E are all read write enable */
- pci_write_config8(dev, 0x80, pagec);
- pci_write_config8(dev, 0x81, paged);
- pci_write_config8(dev, 0x83, pagee);
- /* PAGE F are read/writable */
- shadowreg = pci_read_config8(dev, 0x82);
- shadowreg |= pagef;
- pci_write_config8(dev, 0x82, shadowreg);
- pci_write_config8(vlink_dev, 0x61, pagec);
- pci_write_config8(vlink_dev, 0x62, paged);
- pci_write_config8(vlink_dev, 0x64, pagee);
-
- shadowreg = pci_read_config8(vlink_dev, 0x63);
- shadowreg |= pagef;
- pci_write_config8(vlink_dev, 0x63, shadowreg);
-
- /* Activate VGA Frame Buffer */
-
- reg8 = pci_read_config8(dev, 0xA0);
- reg8 |= 0x01;
- pci_write_config8(dev, 0xA0, reg8);
-
-#ifdef DEBUG_CN400
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-#endif
- printk(BIOS_SPEW, "Leaving cn400 %s.\n", __func__);
-}
-
-static const struct device_operations memctrl_operations = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = memctrl_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver memctrl_driver __pci_driver = {
- .ops = &memctrl_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
-};
-
-static void cn400_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- printk(BIOS_SPEW, "Entering %s.\n", __func__);
-
- /* Initialize the system wide I/O space constraints. */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints. */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED;
-
- printk(BIOS_SPEW, "Leaving %s.\n", __func__);
-}
-
-#ifdef UNUSED_CODE
-static void ram_reservation(device_t dev, unsigned long index,
- unsigned long base, unsigned long size)
-{
- struct resource *res;
-
- printk(BIOS_SPEW, "Configuring Via C3 LAPIC Fixed Resource\n");
- /* Fixed LAPIC resource */
- res = new_resource(dev, 1);
- res->base = (resource_t) base;
- res->size = size;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-#endif
-
-static void cn400_domain_set_resources(device_t dev)
-{
- device_t mc_dev;
- u32 pci_tolm;
-
- printk(BIOS_SPEW, "Entering %s.\n", __func__);
-
- pci_tolm = find_pci_tolm(dev->link_list);
- mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0);
-
- if (mc_dev) {
- unsigned long tomk, tolmk;
- unsigned char rambits;
- int idx;
-
- rambits = pci_read_config8(mc_dev, 0x47);
- tomk = rambits * 32 * 1024;
- /* Compute the Top Of Low Memory (TOLM), in Kb. */
- tolmk = pci_tolm >> 10;
- printk(BIOS_SPEW, "tomk is 0x%lx, tolmk is 0x%08lX\n", tomk, tolmk);
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory. */
- tolmk = tomk;
- }
-
- /* Locate the High Tables at the Top of Low Memory below the Video RAM */
- set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024);
-
- /* Report the memory regions. */
- idx = 10;
- /* TODO: Hole needed? */
- ram_resource(dev, idx++, 0, 640); /* First 640k */
- /* Leave a hole for VGA, 0xa0000 - 0xc0000 */
- ram_resource(dev, idx++, 768,
- (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
- }
- assign_resources(dev->link_list);
-
- printk(BIOS_SPEW, "Leaving %s.\n", __func__);
-}
-
-static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
-{
- printk(BIOS_DEBUG, "Entering %s.\n", __func__);
-
- max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = cn400_domain_read_resources,
- .set_resources = cn400_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = cn400_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev));
-
- /* Set the operations if it is a special bus type. */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_via_cn400_ops = {
- CHIP_NAME("VIA CN400 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/via/cn400/northbridge.h b/src/northbridge/via/cn400/northbridge.h
deleted file mode 100644
index 1fa848f..0000000
--- a/src/northbridge/via/cn400/northbridge.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef NORTHBRIDGE_VIA_CN400_H
-#define NORTHBRIDGE_VIA_CN400_H
-
-extern unsigned int cn400_scan_root_bus(device_t root, unsigned int max);
-
-#endif /* NORTHBRIDGE_VIA_CN400_H */
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
deleted file mode 100644
index d15a633..0000000
--- a/src/northbridge/via/cn400/raminit.c
+++ /dev/null
@@ -1,819 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Nick Barker <nick.barker9 at btinternet.com>
- * Copyright (C) 2009 Jon Harrison <bothlyn at blueyonder.co.uk
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- Automatically detect and set up ddr dram on the CN400 chipset.
- Assumes DDR400 memory as no attempt is made to clock
- the chipset down if slower memory is installed.
- So far tested on:
- 512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
-*/
-/* ported from Via VT8263 Code*/
-
-#include <spd.h>
-#include <delay.h>
-#include <cpu/x86/mtrr.h>
-#include "cn400.h"
-
-static void dimm_read(unsigned long bank,unsigned long x)
-{
- //unsigned long eax;
- volatile unsigned long y;
- //eax = x;
- y = * (volatile unsigned long *) (x+ bank) ;
-
-}
-
-
-static void print_val(char *str, int val)
-{
- print_debug(str);
- print_debug_hex8(val);
-}
-
-/**
- * Configure the bus between the CPU and the northbridge. This might be able to
- * be moved to post-ram code in the future. For the most part, these registers
- * should not be messed around with. These are too complex to explain short of
- * copying the datasheets into the comments, but most of these values are from
- * the BIOS Porting Guide, so they should work on any board. If they don't,
- * try the values from your factory BIOS.
- *
- * TODO: Changing the DRAM frequency doesn't work (hard lockup).
- *
- * @param dev The northbridge's CPU Host Interface (D0F2).
- */
-static void c3_cpu_setup(device_t dev)
-{
- /* Host bus interface registers (D0F2 0x50-0x67) */
- /* Taken from CN700 and updated from running CN400 */
- uint8_t reg8;
-
- /* Host Bus I/O Circuit (see datasheet) */
- /* Host Address Pullup/down Driving */
- pci_write_config8(dev, 0x70, 0x33);
- pci_write_config8(dev, 0x71, 0x44);
- pci_write_config8(dev, 0x72, 0x33);
- pci_write_config8(dev, 0x73, 0x44);
-
- /* Output Delay Stagger Control */
- pci_write_config8(dev, 0x74, 0x70);
-
- /* AGTL+ I/O Circuit */
- pci_write_config8(dev, 0x75, 0x08);
-
- /* AGTL+ Compensation Status */
- pci_write_config8(dev, 0x76, 0x74);
-
- /* AGTL+ Auto Compensation Offest */
- pci_write_config8(dev, 0x77, 0x00);
- pci_write_config8(dev, 0x78, 0x94);
-
- /* Request phase control */
- pci_write_config8(dev, 0x50, 0xA8);
-
- /* Line DRDY# Timing Control */
- pci_write_config8(dev, 0x60, 0x00);
- pci_write_config8(dev, 0x61, 0x00);
- pci_write_config8(dev, 0x62, 0x00);
-
- /* QW DRDY# Timing Control */
- pci_write_config8(dev, 0x63, 0x00);
- pci_write_config8(dev, 0x64, 0x00);
- pci_write_config8(dev, 0x65, 0x00);
-
- /* Read Line Burst DRDY# Timing Control */
- pci_write_config8(dev, 0x66, 0x00);
- pci_write_config8(dev, 0x67, 0x00);
-
- /* CPU Interface Control */
- pci_write_config8(dev, 0x51, 0xFE);
- pci_write_config8(dev, 0x52, 0xEF);
-
- /* Arbitration */
- pci_write_config8(dev, 0x53, 0x88);
-
- /* Write Policy & Reorder Latecy */
- pci_write_config8(dev, 0x56, 0x00);
-
- /* Delivery-Trigger Control */
- pci_write_config8(dev, 0x58, 0x00);
-
- /* IPI Control */
- pci_write_config8(dev, 0x59, 0x30);
-
- /* CPU Misc Control */
- pci_write_config8(dev, 0x5C, 0x00);
-
- /* Write Policy */
- pci_write_config8(dev, 0x5d, 0xb2);
-
- /* Bandwidth Timer */
- pci_write_config8(dev, 0x5e, 0x88);
-
- /* CPU Miscellaneous Control */
- pci_write_config8(dev, 0x5f, 0xc7);
-
- /* CPU Miscellaneous Control */
- pci_write_config8(dev, 0x55, 0x28);
- pci_write_config8(dev, 0x57, 0x69);
-
- /* CPU Host Bus Final Setup */
- reg8 = pci_read_config8(dev, 0x54);
- reg8 |= 0x08;
- pci_write_config8(dev, 0x54, reg8);
-
-}
-
-static void ddr_ram_setup(void)
-{
- uint8_t b, c, bank, ma;
- uint16_t i;
- unsigned long bank_address;
-
-
- print_debug("CN400 RAM init starting\n");
-
- pci_write_config8(ctrl.d0f7, 0x75, 0x08);
-
-
- /* No Interleaving or Multi Page */
- pci_write_config8(ctrl.d0f3, 0x69, 0x00);
- pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
-
-/*
- DRAM MA Map Type Device 0 Fn3 Offset 50-51
-
- Determine memory addressing based on the module's memory technology and
- arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
-
- Bank 1/0 MA map type 50[7-5]
- Bank 1/0 command rate 50[4]
- Bank 3/2 MA map type 50[3-1]
- Bank 3/2 command rate 50[0]
-
-
- Read SPD byte 17, Number of banks on SDRAM device.
-*/
- c = 0;
- b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
- //print_val("Detecting Memory\nNumber of Banks ",b);
-
- // Only supporting 4 bank chips just now
- if( b == 4 ){
- /* Read SPD byte 3, Number of row addresses. */
- c = 0x01;
- bank = 0x40;
- b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
- //print_val("\nNumber of Rows ", b);
-
- if( b >= 0x0d ){ // 256/512Mb
-
- if (b == 0x0e)
- bank = 0x48;
- else
- bank = 0x44;
-
- /* Read SPD byte 13, Primary DRAM width. */
- b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
- //print_val("\nPrimary DRAM width", b);
- if( b != 4 ) // not 64/128Mb (x4)
- c = 0x81; // 256Mb
- }
-
- /* Read SPD byte 4, Number of column addresses. */
- b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
- //print_val("\nNo Columns ",b);
- if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
- if( b == 9 ) c |= 0x40; // 9 bit col addr
- if( b == 8 ) c |= 0x20; // 8 bit col addr
-
- //print_val("\nMA type ", c);
- pci_write_config8(ctrl.d0f3, 0x50, c);
-
- }
-
- /* Disable Upper Banks */
- pci_write_config8(ctrl.d0f3, 0x51, 0x00);
-
-/* else
- {
- die("DRAM module size is not supported by CN400\n");
- }
-*/
-
-/*
- DRAM bank size. See 4.3.1 pg 35
-
- 5a->5d set to end address for each bank. 1 bit == 32MB
- 5a = bank 0
- 5b = bank 0 + b1
- 5c = bank 0 + b1 + b2
- 5d = bank 0 + b1 + b2 + b3
-*/
-
- // Read SPD byte 31 Module bank density
- //c = 0;
- b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
- if( b & 0x02 )
- {
- c = 0x40; // 2GB
- bank |= 0x02;
- }
- else if( b & 0x01)
- {
- c = 0x20; // 1GB
- if (bank == 0x48) bank |= 0x01;
- else bank |= 0x03;
- }
- else if( b & 0x80)
- {
- c = 0x10; // 512MB
- if (bank == 0x44) bank |= 0x02;
- }
- else if( b & 0x40)
- {
- c = 0x08; // 256MB
- if (bank == 0x44) bank |= 0x01;
- else bank |= 0x03;
- }
- else if( b & 0x20)
- {
- c = 0x04; // 128MB
- if (bank == 0x40) bank |= 0x02;
- }
- else if( b & 0x10)
- {
- c = 0x02; // 64MB
- bank |= 0x01;
- }
- else if( b & 0x08) c = 0x01; // 32MB
- else c = 0x01; // Error, use default
-
- // set bank zero size
- pci_write_config8(ctrl.d0f3, 0x40, c);
-
- // SPD byte 5 # of physical banks
- b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
-
- //print_val("\nNo Physical Banks ",b);
- if( b == 2)
- {
- c <<=1;
- bank |= 0x80;
- }
-/* else
- {
- die("Only a single DIMM is supported by EPIA-N(L)\n");
- }
-*/
- // set banks 1,2,3...
- pci_write_config8(ctrl.d0f3, 0x41,c);
- pci_write_config8(ctrl.d0f3, 0x42,c);
- pci_write_config8(ctrl.d0f3, 0x43,c);
- pci_write_config8(ctrl.d0f3, 0x44,c);
- pci_write_config8(ctrl.d0f3, 0x45,c);
- pci_write_config8(ctrl.d0f3, 0x46,c);
- pci_write_config8(ctrl.d0f3, 0x47,c);
-
- /* Top Rank Address Mirrored to the South Bridge */
- /* over the VLink */
- pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
-
- ma = bank;
-
- /* Read SPD byte 18 CAS Latency */
- b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
-/* print_debug("\nCAS Supported ");
- if(b & 0x04)
- print_debug("2 ");
- if(b & 0x08)
- print_debug("2.5 ");
- if(b & 0x10)
- print_debug("3");
-
- c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- print_val("\nCycle time at CL X (nS)", c);
- c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
- print_val("\nCycle time at CL X-0.5 (nS)", c);
- c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
- print_val("\nCycle time at CL X-1 (nS)", c);
-*/
- /* Scaling of Cycle Time SPD data */
- /* 7 4 3 0 */
- /* ns x0.1ns */
- bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-
- if( b & 0x10 ){ // DDR offering optional CAS 3
- //print_debug("\nStarting at CAS 3");
- c = 0x30;
- /* see if we can better it */
- if( b & 0x08 ){ // DDR mandatory CAS 2.5
- if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
- //print_debug("\nWe can do CAS 2.5");
- c = 0x20;
- }
- }
- if( b & 0x04 ){ // DDR mandatory CAS 2
- if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2
- //print_debug("\nWe can do CAS 2");
- c = 0x10;
- }
- }
- }else{ // no optional CAS values just 2 & 2.5
- //print_debug("\nStarting at CAS 2.5");
- c = 0x20; // assume CAS 2.5
- if( b & 0x04){ // Should always happen
- if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2
- //print_debug("\nWe can do CAS 2");
- c = 0x10;
- }
- }
- }
-
- /* Scale DRAM Cycle Time to tRP/tRCD */
- /* 7 2 1 0 */
- /* ns x0.25ns */
- if ( bank <= 0x50 ) bank = 0x14;
- else if (bank <= 0x60) bank = 0x18;
- else bank = 0x1E;
-
-/*
- DRAM Timing Device 0 Fn 3 Offset 56
-
- RAS Pulse width 56[7,6]
- CAS Latency 56[5,4]
- Row pre-charge 56[1,0]
-
- SDR DDR
- 00 1T -
- 01 2T 2T
- 10 3T 2.5T
- 11 - 3T
-
- RAS/CAS delay 56[3,2]
-
- Determine row pre-charge time (tRP)
-
-
- Read SPD byte 27, min row pre-charge time.
-*/
-
- b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
-
- //print_val("\ntRP ",b);
- if ( b >= (5 * bank)) {
- c |= 0x03; // set tRP = 5T
- }
- else if ( b >= (4 * bank)) {
- c |= 0x02; // set tRP = 4T
- }
- else if ( b >= (3 * bank)) {
- c |= 0x01; // set tRP = 3T
- }
-
-/*
- Determine RAS to CAS delay (tRCD)
-
- Read SPD byte 29, min row pre-charge time.
-*/
-
- b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
- //print_val("\ntRCD ",b);
-
- if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
- else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
- else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T
-
-/*
- Determine RAS pulse width (tRAS)
-
-
- Read SPD byte 30, device min active to pre-charge time.
-*/
-
- /* tRAS is in whole ns */
- bank = bank >> 2;
-
- b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- //print_val("\ntRAS ",b);
- //print_val("\nBank ", bank);
- if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
- else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
- else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
-
- /* Write DRAM Timing All Banks I */
- pci_write_config8(ctrl.d0f3, 0x56, c);
-
- /* TWrite DRAM Timing All Banks II */
- pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
-
- /* DRAM arbitration timer */
- pci_write_config8(ctrl.d0f3, 0x65, 0x99);
-
-/*
- DRAM Clock Device 0 Fn 3 Offset 68
-*/
- bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-
- /* Setup DRAM Cycle Time */
- if ( bank <= 0x50 )
- {
- /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
- /* This sets to 133MHz FSB / DDR400. */
- pci_write_config8(ctrl.d0f3, 0x68, 0x85);
- }
- else if (bank <= 0x60)
- {
- /* DRAM DDR Control Alert! Alert! This hardwires to */
- /* 133MHz FSB / DDR333. See also c3_cpu_setup */
- pci_write_config8(ctrl.d0f3, 0x68, 0x81);
- }
- else
- {
- /* DRAM DDR Control Alert! Alert! This hardwires to */
- /* 133MHz FSB / DDR266. See also c3_cpu_setup */
- pci_write_config8(ctrl.d0f3, 0x68, 0x80);
- }
-
- /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
- udelay(200);
-
-/*
- Determine bank interleave
-
- Read SPD byte 17, Number of banks on SDRAM device.
-*/
- c = 0x0F;
- b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
- if( b == 4) c |= 0x80;
- else if (b == 2) c |= 0x40;
-
- /* 4-Way Interleave With Multi-Paging (From Running System)*/
- pci_write_config8(ctrl.d0f3, 0x69, c);
-
- /*DRAM Controller Internal Options */
- pci_write_config8(ctrl.d0f3, 0x54, 0x01);
-
- /* DRAM Arbitration Control */
- pci_write_config8(ctrl.d0f3, 0x66, 0x82);
-
- /* DRAM Control */
- pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
-
- /* Disable refresh for now */
- pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
-
- /* DDR Clock Gen Duty Cycle Control */
- pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
-
-
- /* DRAM Clock Control */
- pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
-
- /* DRAM Bus Turn-Around Setting */
- pci_write_config8(ctrl.d0f3, 0x60, 0x01);
-
- /* Disable DRAM refresh */
- pci_write_config8(ctrl.d0f3,0x6a,0x0);
-
-
- /* Memory Pads Driving and Range Select */
- pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
- pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
- pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
-
- /* DRAM signal timing control */
- pci_write_config8(ctrl.d0f3, 0x74, 0x99);
- pci_write_config8(ctrl.d0f3, 0x76, 0x09);
- pci_write_config8(ctrl.d0f3, 0x77, 0x12);
-
- pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
- pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
- pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
- pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
- pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
-
-
- /* SPD byte 5 # of physical banks */
- b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
- c = b | 0x40;
-
- pci_write_config8(ctrl.d0f3, 0xb0, c);
-
- /* Set RAM Decode method */
- pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
-
- /* Enable DIMM Ranks */
- pci_write_config8(ctrl.d0f3, 0x48, ma);
- udelay(200);
-
- c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
- c &= 0x08;
- if ( c == 0x08 )
- {
- print_debug("Setting Burst Length 8\n");
- /*
- CPU Frequency Device 0 Function 2 Offset 54
-
- CPU FSB Operating Frequency (bits 7:5)
- 000 : 100MHz 001 : 133MHz
- 010 : 200MHz
- 011->111 : Reserved
-
- SDRAM BL8 (4)
-
- Don't change Frequency from power up defaults
- This seems to lockup the RAM interface
- */
- c = pci_read_config8(ctrl.d0f2, 0x54);
- c |= 0x10;
- pci_write_config8(ctrl.d0f2, 0x54, c);
- i = 0x008; // Used later to set SDRAM MSR
- }
-
-
- for( bank = 0 , bank_address=0; bank <= b ; bank++) {
-/*
- DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1)
-*/
-
- /* NOP command enable */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_NOP;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
-
- /* read a double word from any address of the dimm */
- dimm_read(bank_address,0x1f000);
- //udelay(200);
-
- /* All bank precharge Command Enable */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_PRECHARGE;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
- dimm_read(bank_address,0x1f000);
-
-
- /* MSR Enable Low DIMM*/
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_MSR_LOW;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
- /* TODO: Bank Addressing for Different Numbers of Row Addresses */
- dimm_read(bank_address,0x2000);
- udelay(1);
- dimm_read(bank_address,0x800);
- udelay(1);
-
- /* All banks precharge Command Enable */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_PRECHARGE;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
- dimm_read(bank_address,0x1f200);
-
- /* CBR Cycle Enable */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_CBR;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
-
- /* Read 8 times */
- for (c=0;c<8;c++) {
- dimm_read(bank_address,0x1f300);
- udelay(100);
- }
-
- /* MSR Enable */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_MSR_LOW;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
-
-
-/*
- Mode Register Definition
- with adjustement so that address calculation is correct - 64 bit technology, therefore
- a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
- to DIMM as a row or column address.
-
- MR[9-7] CAS Latency
- MR[6] Burst Type 0 = sequential, 1 = interleaved
- MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
- MR[0-2] dont care
-
- CAS Latency
- 000 reserved
- 001 reserved
- 010 2
- 011 3
- 100 reserved
- 101 1.5
- 110 2.5
- 111 reserved
-
- CAS 2 0101011000 = 0x158
- CAS 2.5 1101011000 = 0x358
- CAS 3 0111011000 = 0x1d8
-
-*/
- c = pci_read_config8(ctrl.d0f3, 0x56);
- if( (c & 0x30) == 0x10 )
- dimm_read(bank_address,(0x150 + i));
- else if((c & 0x30) == 0x20 )
- dimm_read(bank_address,(0x350 + i));
- else
- dimm_read(bank_address,(0x1d0 + i));
-
-
- /* Normal SDRAM Mode */
- c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
- c &= 0xf8; /* Clear bits 2-0. */
- c |= RAM_COMMAND_NORMAL;
- pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
-
- bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
- } // end of for each bank
-
-
- /* Set DRAM DQS Output Control */
- pci_write_config8(ctrl.d0f3, 0x79, 0x11);
-
- /* Set DQS A/B Input delay to defaults */
- pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
- pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
-
- /* DQS Duty Cycle Control */
- pci_write_config8(ctrl.d0f3, 0xED, 0x11);
-
- /* SPD byte 5 # of physical banks */
- b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
-
- /* determine low bond */
- if( b == 2)
- bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
- else
- bank_address = 0;
-
- for(i = 0x30 ; i < 0x0ff; i++){
- pci_write_config8(ctrl.d0f3,0x70,i);
- // clear
- *(volatile unsigned long*)(0x4000) = 0;
- *(volatile unsigned long*)(0x4100+bank_address) = 0;
- *(volatile unsigned long*)(0x4200) = 0;
- *(volatile unsigned long*)(0x4300+bank_address) = 0;
- *(volatile unsigned long*)(0x4400) = 0;
- *(volatile unsigned long*)(0x4500+bank_address) = 0;
-
- // fill
- *(volatile unsigned long*)(0x4000) = 0x12345678;
- *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
- *(volatile unsigned long*)(0x4200) = 0x78123456;
- *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
- *(volatile unsigned long*)(0x4400) = 0x56781234;
- *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
-
- // verify
- if( *(volatile unsigned long*)(0x4000) != 0x12345678)
- continue;
-
- if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
- continue;
-
- if( *(volatile unsigned long*)(0x4200) != 0x78123456)
- continue;
-
- if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
- continue;
-
- if( *(volatile unsigned long*)(0x4400) != 0x56781234)
- continue;
-
- if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
- continue;
-
- // if everything verified then found low bond
- break;
-
- }
- print_val("\nLow Bond ",i);
- if( i < 0xff ){
- c = i++;
- for( ; i <0xff ; i++){
- pci_write_config8(ctrl.d0f3,0x70, i);
- // clear
- *(volatile unsigned long*)(0x8000) = 0;
- *(volatile unsigned long*)(0x8100+bank_address) = 0;
- *(volatile unsigned long*)(0x8200) = 0x0;
- *(volatile unsigned long*)(0x8300+bank_address) = 0;
- *(volatile unsigned long*)(0x8400) = 0x0;
- *(volatile unsigned long*)(0x8500+bank_address) = 0;
-
- // fill
- *(volatile unsigned long*)(0x8000) = 0x12345678;
- *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
- *(volatile unsigned long*)(0x8200) = 0x78123456;
- *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
- *(volatile unsigned long*)(0x8400) = 0x56781234;
- *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
-
- // verify
- if( *(volatile unsigned long*)(0x8000) != 0x12345678)
- break;
-
- if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
- break;
-
- if( *(volatile unsigned long*)(0x8200) != 0x78123456)
- break;
-
- if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
- break;
-
- if( *(volatile unsigned long*)(0x8400) != 0x56781234)
- break;
-
- if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
- break;
-
- }
- print_val(" High Bond ",i);
- c = ((i - c)<<1)/3 + c;
- print_val(" Setting DQS delay",c);
- print_debug("\n");
- pci_write_config8(ctrl.d0f3,0x70,c);
- }else{
- pci_write_config8(ctrl.d0f3,0x70,0x67);
- }
-
- /* Set DQS ChA Data Output Delay to the default */
- pci_write_config8(ctrl.d0f3, 0x71, 0x65);
-
- /* Set Ch B DQS Output Delays */
- pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
- pci_write_config8(ctrl.d0f3, 0x73, 0x29);
-
- pci_write_config8(ctrl.d0f3, 0x78, 0x03);
-
- /* Mystery Value */
- pci_write_config8(ctrl.d0f3, 0x67, 0x50);
-
- /* Enable Toggle Limiting */
- pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
-
-/*
- DRAM refresh rate Device 0 F3 Offset 6a
- TODO :: Fix for different DRAM technologies
- other than 512Mb and DRAM Freq
- Units of 16 DRAM clock cycles - 1.
-*/
- //c = pci_read_config8(ctrl.d0f3, 0x68);
- //c &= 0x07;
- //b = smbus_read_byte(DIMM0, SPD_REFRESH);
- //print_val("SPD_REFRESH = ", b);
-
- pci_write_config8(ctrl.d0f3,0x6a,0x65);
-
- /* SMM and APIC decoding, we do not use SMM */
- b = 0x29;
- pci_write_config8(ctrl.d0f3, 0x86, b);
- /* SMM and APIC decoding mirror */
- pci_write_config8(ctrl.d0f7, 0xe6, b);
-
- /* Open Up the Rest of the Shadow RAM */
- pci_write_config8(ctrl.d0f3,0x80,0xff);
- pci_write_config8(ctrl.d0f3,0x81,0xff);
-
- /* pci */
- pci_write_config8(ctrl.d0f7,0x70,0x82);
- pci_write_config8(ctrl.d0f7,0x73,0x01);
- pci_write_config8(ctrl.d0f7,0x76,0x50);
-
- pci_write_config8(ctrl.d0f7,0x71,0xc8);
-
-
- /* VGA device. */
- pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
- pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
- print_debug("CN400 raminit.c done\n");
-}
diff --git a/src/northbridge/via/cn400/raminit.h b/src/northbridge/via/cn400/raminit.h
deleted file mode 100644
index 89ea0d6..0000000
--- a/src/northbridge/via/cn400/raminit.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey_osgood at verizon.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-#define DIMM_SOCKETS 1 /* Only one works, for now. */
-
-struct mem_controller {
- device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
- u8 channel0[DIMM_SOCKETS];
-};
-
-#endif
diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c
deleted file mode 100644
index a2afdce..0000000
--- a/src/northbridge/via/cn400/vga.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * Note: Some of the VGA control registers are located on the memory
- * controller. Registers are set both in raminit.c and northbridge.c.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <arch/interrupt.h>
-#include "northbridge.h"
-#include "cn400.h"
-#include <x86emu/regs.h>
-
-static int via_cn400_int15_handler(void)
-{
- int res=0;
- printk(BIOS_DEBUG, "via_cn400_int15_handler\n");
- switch(X86_EAX & 0xffff) {
- case 0x5f19:
- break;
- case 0x5f18:
- X86_EAX=0x5f;
- X86_EBX=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
- X86_ECX=0x060;
- res=1;
- break;
- case 0x5f00:
- X86_EAX = 0x8600;
- break;
- case 0x5f01:
- X86_EAX = 0x5f;
- X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
- res = 1;
- break;
- case 0x5f02:
- X86_EAX=0x5f;
- X86_EBX= (X86_EBX & 0xffff0000) | 2;
- X86_ECX= (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only
- X86_EDX= (X86_EDX & 0xffff0000) | 0; // TV Layout - default
- res=1;
- break;
- case 0x5f0f:
- X86_EAX=0x860f;
- break;
- default:
- printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
- X86_EAX & 0xffff);
- break;
- }
- return res;
-}
-
-static void vga_init(device_t dev)
-{
- u8 reg8;
-
- mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler);
-
- /* Set memory rate to 200 MHz. */
- outb(0x3d, CRTM_INDEX);
- reg8 = inb(CRTM_DATA);
- reg8 &= 0x0f;
- reg8 |= (0x1 << 4);
- outb(0x3d, CRTM_INDEX);
- outb(reg8, CRTM_DATA);
-
- /* Set framebuffer size. */
- reg8 = (CONFIG_VIDEO_MB / 4);
- outb(0x39, SR_INDEX);
- outb(reg8, SR_DATA);
-
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x0d, 0x20);
- pci_write_config32(dev, 0x10, 0xf0000008);
- pci_write_config32(dev, 0x14, 0xf4000000);
-
- printk(BIOS_DEBUG, "Initializing VGA...\n");
-
- pci_dev_init(dev);
-
- /* It's not clear if these need to be programmed before or after
- * the VGA BIOS runs. Try both, clean up later. */
-
- /* Set memory rate to 200 MHz (again). */
- outb(0x3d, CRTM_INDEX);
- reg8 = inb(CRTM_DATA);
- reg8 &= 0x0f;
- reg8 |= (0x1 << 4);
- outb(0x3d, CRTM_INDEX);
- outb(reg8, CRTM_DATA);
-
- /* Set framebuffer size (again). */
- reg8 = (CONFIG_VIDEO_MB / 4);
- outb(0x39, SR_INDEX);
- outb(reg8, SR_DATA);
-
-#ifdef DEBUG_CN400
- int i, j;
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-#endif
-}
-
-static const struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_VGA,
-};
diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c
deleted file mode 100644
index 2319e75..0000000
--- a/src/northbridge/via/cn400/vlink.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Jon Harrison <bothlyn at blueyonder.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "northbridge.h"
-#include "cn400.h"
-
-static void noop_1k(u32 knops)
-{
- u32 i;
-
- for (i = 0; i < 1024 * knops; i++) {
- __asm__ volatile ("nop\n\t");
- }
-
- return;
-}
-
-/* Vlink Performance Improvements */
-static void vlink_init(device_t dev)
-{
- u8 reg, reg8;
- int i, j;
-
- printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
-
- /* Disconnect the VLink Before Changing Settings */
- reg = pci_read_config8(dev, 0x47);
- reg |= 0x04;
- pci_write_config8(dev, 0x47, reg);
-
- /* Wait for anything pending to flush */
- noop_1k(20);
-
- /* Setup Vlink Mode 1 */
- pci_write_config8(dev, 0x4F, 0x01);
- pci_write_config8(dev, 0x48, 0x13);
-
- /* PCI Buffer Control */
- pci_write_config8(dev, 0x70, 0x82);
-
- /* CPU to PCI Flow Control */
- pci_write_config8(dev, 0x71, 0xc8);
- pci_write_config8(dev, 0x72, 0xee);
-
- /* PCI Master Control */
- pci_write_config8(dev, 0x73, 0x01);
- pci_write_config8(dev, 0x74, 0x20);
-
- /* PCI Arbitration 1 */
- pci_write_config8(dev, 0x75, 0x0f);
-
- /* PCI Arbitration 2 */
- pci_write_config8(dev, 0x76, 0x50);
- pci_write_config8(dev, 0x77, 0x6e);
- pci_write_config8(dev, 0x7F, 0x10);
-
- pci_write_config8(dev, 0x94, 0x20);
- pci_write_config8(dev, 0x95, 0x0f);
-
- /* V-Link CKG Control 1 */
- pci_write_config8(dev, 0xB0, 0x01);
-
- /* V-Link NB Compensation Control */
- pci_write_config8(dev, 0xB5, 0x46);
- pci_write_config8(dev, 0xB6, 0x68);
- reg = pci_read_config8(dev, 0xB4);
- reg |= 0x01;
- pci_write_config8(dev, 0xB4, reg);
-
- /* V-Link NB Receive Strobe Delay */
- pci_write_config8(dev, 0xB7, 0x02);
-
- /* V-Link SB Compensation Control */
- pci_write_config8(dev, 0xB9, 0x84);
- reg = pci_read_config8(dev, 0xB8);
- reg |= 0x01;
- pci_write_config8(dev, 0xB8, reg);
-
- pci_write_config8(dev, 0xBA, 0x6a);
- pci_write_config8(dev, 0xBB, 0x01);
-
-#ifdef DEBUG_CN400
- /* Reconnect the VLink Before Continuing*/
- reg = pci_read_config8(dev, 0x47);
- reg &= ~0x04;
- pci_write_config8(dev, 0x47, reg);
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-#endif
-}
-
-static const struct device_operations vlink_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vlink_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vlink_driver __pci_driver = {
- .ops = &vlink_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_VLINK,
-};
-
-static void c3_host_init(device_t dev)
-{
- u8 reg8;
- int i, j;
-
- printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-
-}
-
-static const struct device_operations c3_host_operations = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = c3_host_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver c3_host_driver __pci_driver = {
- .ops = &c3_host_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_HOST,
-};
-
-
-static void c3_err_init(device_t dev)
-{
- u8 reg8;
- int i, j;
-
- printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-
-}
-
-static const struct device_operations c3_err_operations = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = c3_err_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver c3_err_driver __pci_driver = {
- .ops = &c3_err_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_ERR,
-};
-
-static void cn400_pm_init(device_t dev)
-{
- u8 reg8;
- int i, j;
-
- printk(BIOS_SPEW, "Entering CN400 %s\n", __func__);
-
- printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
-
- for (i = 0 ; i < 16; i++)
- {
- printk(BIOS_SPEW, "%02X: ", i*16);
- for (j = 0; j < 16; j++)
- {
- reg8 = pci_read_config8(dev, j+(i*16));
- printk(BIOS_SPEW, "%02X ", reg8);
- }
- printk(BIOS_SPEW, "\n");
- }
-
-}
-
-static const struct device_operations cn400_pm_operations = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cn400_pm_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver cn400_pm_driver __pci_driver = {
- .ops = &c3_err_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_CN400_PM,
-};
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