[coreboot-gerrit] Patch set updated for coreboot: a424fe4 rambi: limit SD card controller to 2.0 spec
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Thu May 8 17:06:35 CEST 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4998
-gerrit
commit a424fe48b75f6577169381d00cdd6ed7c1fd02b8
Author: Aaron Durbin <adurbin at chromium.org>
Date: Tue Dec 10 09:01:41 2013 -0800
rambi: limit SD card controller to 2.0 spec
The rambi board can only meet the SD card 2.0 specification.
Therefore, the controller capabilities need to be overridden
to match.
BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
high speed as maximum timing as well as 3.3V signal voltage.
Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179415
---
src/mainboard/google/rambi/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 1c24d57..96772ac 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -27,6 +27,10 @@ chip soc/intel/baytrail
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
device cpu_cluster 0 on
device lapic 0 on end
end
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