[coreboot-gerrit] Patch set updated for coreboot: bcbf0b7 nyan: big: Set the i2c controller frequencies appropriately.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7418

-gerrit

commit bcbf0b7e19c6023d14904419b20f4630572990cf
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Mar 5 22:07:41 2014 -0800

    nyan: big: Set the i2c controller frequencies appropriately.
    
    These had been set to something fairly random which results in a very slow
    clock on the bus itself. The new settings take into consideration the speed
    the devices on the bus can run at. The TPM can't seem to handle speeds above
    40KHz, but some documentation suggests that it should be able to handle up to
    at least 100KHz.
    
    BUG=chrome-os-partner:25467
    TEST=Built and booted on nyan rev1. Built for big.
    BRANCH=None
    
    Original-Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/189015
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit afca97a29aeb99d3899b713d0e57a3b3214f0d96)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Iab0c50b2119ac322252564354c90b5cb2d255c97
---
 src/mainboard/google/nyan/bootblock.c     |  4 ++--
 src/mainboard/google/nyan/mainboard.c     | 15 +++++++++++----
 src/mainboard/google/nyan_big/bootblock.c |  4 ++--
 src/mainboard/google/nyan_big/mainboard.c | 15 +++++++++++----
 4 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index c168550..2b033a6 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -40,8 +40,8 @@ static void set_clock_sources(void)
 
 	clock_configure_source(mselect, PLLP, 102000);
 
-	/* TODO: is the 1.333MHz correct? This may have always been bogus... */
-	clock_configure_source(i2c5, CLK_M, 1333);
+	/* The PMIC is on I2C5 and can run at 400 KHz. */
+	clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
 
 	/* TODO: We should be able to set this to 50MHz, but that did not seem
 	 * reliable. */
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index 205051a..35ded72 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -34,10 +34,17 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
 
 static void set_clock_sources(void)
 {
-	clock_configure_source(i2c1, CLK_M, 1333);
-	clock_configure_source(i2c2, CLK_M, 1333);
-	clock_configure_source(i2c3, CLK_M, 1333);
-	clock_configure_source(i2c4, CLK_M, 1333);
+	/*
+	 * The max98090 codec and the temperature sensor are on I2C1. These
+	 * can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
+	 */
+	clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
+	/*
+	 * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
+	 * seem to work above around 40 KHz. It's set to run at 100 KHz in the
+	 * kernel.
+	 */
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
 
 	clock_configure_source(sbc1, PLLP, 5000);
 
diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c
index e88765f..05bb1c9 100644
--- a/src/mainboard/google/nyan_big/bootblock.c
+++ b/src/mainboard/google/nyan_big/bootblock.c
@@ -40,8 +40,8 @@ static void set_clock_sources(void)
 
 	clock_configure_source(mselect, PLLP, 102000);
 
-	/* TODO: is the 1.333MHz correct? This may have always been bogus... */
-	clock_configure_source(i2c5, CLK_M, 1333);
+	/* The PMIC is on I2C5 and can run at 400 KHz. */
+	clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
 
 	/* TODO: We should be able to set this to 50MHz, but that did not seem
 	 * reliable. */
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 309b0b9..49f644f 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -34,10 +34,17 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
 
 static void set_clock_sources(void)
 {
-	clock_configure_source(i2c1, CLK_M, 1333);
-	clock_configure_source(i2c2, CLK_M, 1333);
-	clock_configure_source(i2c3, CLK_M, 1333);
-	clock_configure_source(i2c4, CLK_M, 1333);
+	/*
+	 * The max98090 codec and the temperature sensor are on I2C1. These
+	 * can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
+	 */
+	clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
+	/*
+	 * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
+	 * seem to work above around 40 KHz. It's set to run at 100 KHz in the
+	 * kernel.
+	 */
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
 
 	clock_configure_source(sbc1, PLLP, 5000);