[coreboot-gerrit] New patch to review for coreboot: t210: sdram_lp0: also save EmcBctSpare2 field

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11401

-gerrit

commit 86269c56bb3b6b5d3a5d8ccc0ccfd3b44479dd33
Author: Yen Lin <yelin at nvidia.com>
Date:   Thu Aug 20 15:19:07 2015 -0700

    t210: sdram_lp0: also save EmcBctSpare2 field
    
    Need to save EmcBctSpare2 field to scratch register. Without it,
    system may not resume from LP0 suspend.
    
    BUG=chrome-os-partner:43797
    BRANCH=none
    TEST=able to suspend/resume >30 times on a known failed board
    
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230
    Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7
    Original-Signed-off-by: Yen Lin <yelin at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/294765
    Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
    Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815)
    Original-Reviewed-on: https://chromium-review.googlesource.com/294864
    Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
    Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
    
    Change-Id: I2ff21afbe9278413033101877c2581df51913709
---
 src/soc/nvidia/tegra210/sdram_lp0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c
index f3f2af3..890c285 100644
--- a/src/soc/nvidia/tegra210/sdram_lp0.c
+++ b/src/soc/nvidia/tegra210/sdram_lp0.c
@@ -724,6 +724,7 @@ void sdram_lp0_save_params(const struct sdram_params *sdram)
 	s32(EmcBctSpare5, scratch42);
 	s32(EmcBctSpare4, scratch44);
 	s32(SwizzleRankByteEncode, scratch45);
+	s32(EmcBctSpare2, scratch46);
 	s32(EmcBctSpare1, scratch47);
 	s32(EmcBctSpare0, scratch48);
 	s32(EmcBctSpare9, scratch50);