[coreboot-gerrit] Patch set updated for coreboot: intel/braswell: allow dirty cache line evictions for SMRAM to stick

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11412

-gerrit

commit dda53386ab99ed4687f07d6b96f89494e55681c2
Author: Chiranjeevi Rapolu <chiranjeevi.rapolu at intel.com>
Date:   Tue Aug 11 14:09:46 2015 -0700

    intel/braswell: allow dirty cache line evictions for SMRAM to stick
    
    The BUNIT controls the policy for read/write access to physical
    memory. For the SMRAM range the policy was not allowing dirty
    evictions to the SMRAM when the core causing the eviction was not
    in SMM mode. This could happen when the SMM handler dirtied a line
    and then RSM'd back into non-SMM mode. The cache line was dirtied
    while in SMM mode, but when that particular cache line was evicted
    it would be silently dropped. Fix this by allowing the BUNIT to honor
    writes to the SMRAM range while the evicting core is not in SMM mode.
    The core SMRR msr provides the mechanism for disallowing general access
    to the SMRAM region while it is not in SMM mode.
    
    BUG=chrome-os-partner:43091
    BRANCH=None
    TEST=Run suspend_stress_test and ensure there is no hang SMI handler
    on suspend-path.
    Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu at intel.com>
    
    Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
    Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
    Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
    Original-Reviewed-on: https://chromium-review.googlesource.com/292890
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Commit-Queue: Hannah Williams <hannah.williams at intel.com>
    Original-Tested-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/braswell/cpu.c              | 10 ++++++++++
 src/soc/intel/braswell/include/soc/iosf.h |  6 ++++++
 2 files changed, 16 insertions(+)

diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index e648ce0..2ab8725 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -30,6 +30,7 @@
 #include <cpu/x86/smm.h>
 #include <soc/intel/common/memmap.h>
 #include <reg_script.h>
+#include <soc/iosf.h>
 #include <soc/msr.h>
 #include <soc/pattrs.h>
 #include <soc/ramstage.h>
@@ -86,6 +87,7 @@ void soc_init_cpus(device_t dev)
 	const struct pattrs *pattrs = pattrs_get();
 	struct mp_params mp_params;
 	void *default_smm_area;
+	uint32_t bsmrwac;
 
 	printk(BIOS_SPEW, "%s/%s ( %s )\n",
 			__FILE__, __func__, dev_name(dev));
@@ -104,6 +106,14 @@ void soc_init_cpus(device_t dev)
 
 	default_smm_area = backup_default_smm_area();
 
+	/*
+	 * Configure the BUNIT to allow dirty cache line evictions in non-SMM
+	 * mode for the lines that were dirtied while in SMM mode. Otherwise
+	 * the writes would be silently dropped.
+	 */
+	bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
+	iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
+
 	/* Set package MSRs */
 	reg_script_run(package_msr_script);
 
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index 1cdfb8f..cf56a05 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -131,9 +131,15 @@ void reg_script_write_iosf(struct reg_script_context *ctx);
 #define BUNIT_MMCONF_REG	0x27
 #define BUNIT_BMISC		0x28
 /* The SMMRR registers define the SMM region in MiB granularity. */
+#define BUNIT_SMRWAC	0x2d
 #define BUNIT_SMRRL		0x2e
 #define BUNIT_SMRRH		0x2f
 
+/* SA ID bits. */
+#define SAI_IA_UNTRUSTED	(1 << 0)
+#define SAI_IA_SMM			(1 << 2)
+#define SAI_IA_BOOT			(1 << 4)
+
 /*
  * LPSS Registers
  */